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| author | rahulp13 | 2020-02-28 11:38:58 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-28 11:38:58 +0530 |
| commit | 246319682f60293b132fca1ce6e24689c6682617 (patch) | |
| tree | 6871b758a17869efecfd617f5513e31f9a933f4a /Windows/spice/examples/cider/parallel/clkfeed.cir | |
| parent | d9ab84106cac311d953f344386fef1c1e2bca1cf (diff) | |
| download | eSim-246319682f60293b132fca1ce6e24689c6682617.tar.gz eSim-246319682f60293b132fca1ce6e24689c6682617.tar.bz2 eSim-246319682f60293b132fca1ce6e24689c6682617.zip | |
initial commit
Diffstat (limited to 'Windows/spice/examples/cider/parallel/clkfeed.cir')
| -rw-r--r-- | Windows/spice/examples/cider/parallel/clkfeed.cir | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/Windows/spice/examples/cider/parallel/clkfeed.cir b/Windows/spice/examples/cider/parallel/clkfeed.cir new file mode 100644 index 00000000..d0a06f15 --- /dev/null +++ b/Windows/spice/examples/cider/parallel/clkfeed.cir @@ -0,0 +1,34 @@ +SWITCHED CURRENT CELL - CLOCK FEEDTHROUGH + +VDD 1 0 5.0V +VSS 2 0 0.0V + +IIN 13 0 0.0 +VIN 13 3 0.0 +VL 4 0 2.5V +VCK 6 0 5.0V PULSE 5.0V 0.0V 5.0NS 5NS 5NS 20NS 50NS + +M1 3 3 2 2 M_NMOS_5 W=5U L=5U +M2 4 5 2 2 M_NMOS_5 W=10U L=5U +M3 23 26 25 22 M_NMOS_5 W=5U L=5U +RLK1 3 0 100G +RLK2 5 0 100G +VD 3 23 0.0V +VG 6 26 0.0V +VS 5 25 0.0V +VB 2 22 0.0V + +M4 7 7 1 1 M_PMOS_IDEAL W=100U L=1U +M5 3 7 1 1 M_PMOS_IDEAL W=100U L=1U +M6 4 7 1 1 M_PMOS_IDEAL W=200U L=1U +IREF 7 0 50UA + +****** MODELS ****** +.MODEL M_PMOS_IDEAL PMOS VTO=-1.0V KP=100U + +.INCLUDE BICMOS.LIB + +.TRAN 0.1NS 50NS + +.OPTIONS ACCT BYPASS=1 METHOD=GEAR +.END |