Subject: Added eSim Examples

Description: Added eSim Examples

10 files changed, 588 insertions, 0 deletions

diff --git a/Examples/rc/analysis b/Examples/rc/analysis
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/Examples/rc/analysis
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/Examples/rc/plot_data_i.txt b/Examples/rc/plot_data_i.txt
new file mode 100644
index 00000000..dc758804
--- /dev/null
+++ b/Examples/rc/plot_data_i.txt
@@ -0,0 +1,71 @@
+* eeschema netlist version 1.1 (spice format) creation date: thu jun 11 10:11:01 2015
+Transient Analysis  Thu Jun 11 10:14:02  2015
+--------------------------------------------------------------------------------
+Index   time            alli            
+--------------------------------------------------------------------------------
+0	0.000000e+00	0.000000e+00	
+1	1.000000e-05	-6.22097e-06	
+2	1.084561e-05	-6.74657e-06	
+3	1.253682e-05	-7.79688e-06	
+4	1.591924e-05	-9.89218e-06	
+5	2.268408e-05	-1.40616e-05	
+6	3.621377e-05	-2.23161e-05	
+7	6.327316e-05	-3.84931e-05	
+8	1.173919e-04	-6.95590e-05	
+9	2.256294e-04	-1.26836e-04	
+10	4.421045e-04	-2.24094e-04	
+11	8.750546e-04	-3.63022e-04	
+12	1.561534e-03	-4.74794e-04	
+13	2.607354e-03	-4.89430e-04	
+14	4.103506e-03	-3.33740e-04	
+15	6.103506e-03	2.009336e-05	
+16	8.103506e-03	3.793351e-04	
+17	1.010351e-02	5.936837e-04	
+18	1.210351e-02	5.812653e-04	
+19	1.410351e-02	3.468234e-04	
+20	1.610351e-02	-2.00934e-05	
+21	1.810351e-02	-3.79335e-04	
+22	2.010351e-02	-5.93684e-04	
+23	2.210351e-02	-5.81265e-04	
+24	2.410351e-02	-3.46823e-04	
+25	2.610351e-02	2.009336e-05	
+26	2.810351e-02	3.793351e-04	
+27	3.010351e-02	5.936837e-04	
+28	3.210351e-02	5.812653e-04	
+29	3.410351e-02	3.468234e-04	
+30	3.610351e-02	-2.00934e-05	
+31	3.810351e-02	-3.79335e-04	
+32	4.010351e-02	-5.93684e-04	
+33	4.210351e-02	-5.81265e-04	
+34	4.410351e-02	-3.46823e-04	
+35	4.610351e-02	2.009336e-05	
+36	4.810351e-02	3.793351e-04	
+37	5.010351e-02	5.936837e-04	
+38	5.210351e-02	5.812653e-04	
+39	5.410351e-02	3.468234e-04	
+40	5.610351e-02	-2.00934e-05	
+41	5.810351e-02	-3.79335e-04	
+42	6.010351e-02	-5.93684e-04	
+43	6.210351e-02	-5.81265e-04	
+44	6.410351e-02	-3.46823e-04	
+45	6.610351e-02	2.009336e-05	
+46	6.810351e-02	3.793351e-04	
+47	7.010351e-02	5.936837e-04	
+48	7.210351e-02	5.812653e-04	
+49	7.410351e-02	3.468234e-04	
+50	7.610351e-02	-2.00934e-05	
+51	7.810351e-02	-3.79335e-04	
+52	8.010351e-02	-5.93684e-04	
+53	8.210351e-02	-5.81265e-04	
+54	8.410351e-02	-3.46823e-04	
+
+Index   time            alli            
+--------------------------------------------------------------------------------
+55	8.610351e-02	2.009336e-05	
+56	8.810351e-02	3.793351e-04	
+57	9.010351e-02	5.936837e-04	
+58	9.210351e-02	5.812653e-04	
+59	9.410351e-02	3.468234e-04	
+60	9.610351e-02	-2.00934e-05	
+61	9.810351e-02	-3.79335e-04	
+62	1.000000e-01	-5.86156e-04	
diff --git a/Examples/rc/plot_data_v.txt b/Examples/rc/plot_data_v.txt
new file mode 100644
index 00000000..1523c7e7
--- /dev/null
+++ b/Examples/rc/plot_data_v.txt
@@ -0,0 +1,71 @@
+* eeschema netlist version 1.1 (spice format) creation date: thu jun 11 10:11:01 2015
+Transient Analysis  Thu Jun 11 10:14:02  2015
+--------------------------------------------------------------------------------
+Index   time            V(1)            V(4)            
+--------------------------------------------------------------------------------
+0	0.000000e+00	0.000000e+00	0.000000e+00	
+1	1.000000e-05	6.220965e-05	6.283175e-03	
+2	1.084561e-05	6.791459e-05	6.814482e-03	
+3	1.253682e-05	8.021261e-05	7.877094e-03	
+4	1.591924e-05	1.101286e-04	1.000231e-02	
+5	2.268408e-05	1.911502e-04	1.425271e-02	
+6	3.621377e-05	4.372392e-04	2.275329e-02	
+7	6.327316e-05	1.259968e-03	3.975308e-02	
+8	1.173919e-04	4.183792e-03	7.374280e-02	
+9	2.256294e-04	1.481245e-02	1.416485e-01	
+10	4.421045e-04	5.279624e-02	2.768902e-01	
+11	8.750546e-04	1.798921e-01	5.429139e-01	
+12	1.561534e-03	4.674640e-01	9.422583e-01	
+13	2.607354e-03	9.716663e-01	1.461096e+00	
+14	4.103506e-03	1.587461e+00	1.921201e+00	
+15	6.103506e-03	1.901107e+00	1.881014e+00	
+16	8.103506e-03	1.501679e+00	1.122344e+00	
+17	1.010351e-02	5.286602e-01	-6.50235e-02	
+18	1.210351e-02	-6.46289e-01	-1.22755e+00	
+19	1.410351e-02	-1.57438e+00	-1.92120e+00	
+20	1.610351e-02	-1.90111e+00	-1.88101e+00	
+21	1.810351e-02	-1.50168e+00	-1.12234e+00	
+22	2.010351e-02	-5.28660e-01	6.502348e-02	
+23	2.210351e-02	6.462888e-01	1.227554e+00	
+24	2.410351e-02	1.574377e+00	1.921201e+00	
+25	2.610351e-02	1.901107e+00	1.881014e+00	
+26	2.810351e-02	1.501679e+00	1.122344e+00	
+27	3.010351e-02	5.286602e-01	-6.50235e-02	
+28	3.210351e-02	-6.46289e-01	-1.22755e+00	
+29	3.410351e-02	-1.57438e+00	-1.92120e+00	
+30	3.610351e-02	-1.90111e+00	-1.88101e+00	
+31	3.810351e-02	-1.50168e+00	-1.12234e+00	
+32	4.010351e-02	-5.28660e-01	6.502348e-02	
+33	4.210351e-02	6.462888e-01	1.227554e+00	
+34	4.410351e-02	1.574377e+00	1.921201e+00	
+35	4.610351e-02	1.901107e+00	1.881014e+00	
+36	4.810351e-02	1.501679e+00	1.122344e+00	
+37	5.010351e-02	5.286602e-01	-6.50235e-02	
+38	5.210351e-02	-6.46289e-01	-1.22755e+00	
+39	5.410351e-02	-1.57438e+00	-1.92120e+00	
+40	5.610351e-02	-1.90111e+00	-1.88101e+00	
+41	5.810351e-02	-1.50168e+00	-1.12234e+00	
+42	6.010351e-02	-5.28660e-01	6.502348e-02	
+43	6.210351e-02	6.462888e-01	1.227554e+00	
+44	6.410351e-02	1.574377e+00	1.921201e+00	
+45	6.610351e-02	1.901107e+00	1.881014e+00	
+46	6.810351e-02	1.501679e+00	1.122344e+00	
+47	7.010351e-02	5.286602e-01	-6.50235e-02	
+48	7.210351e-02	-6.46289e-01	-1.22755e+00	
+49	7.410351e-02	-1.57438e+00	-1.92120e+00	
+50	7.610351e-02	-1.90111e+00	-1.88101e+00	
+51	7.810351e-02	-1.50168e+00	-1.12234e+00	
+52	8.010351e-02	-5.28660e-01	6.502348e-02	
+53	8.210351e-02	6.462888e-01	1.227554e+00	
+54	8.410351e-02	1.574377e+00	1.921201e+00	
+
+Index   time            V(1)            V(4)            
+--------------------------------------------------------------------------------
+55	8.610351e-02	1.901107e+00	1.881014e+00	
+56	8.810351e-02	1.501679e+00	1.122344e+00	
+57	9.010351e-02	5.286602e-01	-6.50235e-02	
+58	9.210351e-02	-6.46289e-01	-1.22755e+00	
+59	9.410351e-02	-1.57438e+00	-1.92120e+00	
+60	9.610351e-02	-1.90111e+00	-1.88101e+00	
+61	9.810351e-02	-1.50168e+00	-1.12234e+00	
+62	1.000000e-01	-5.86156e-01	-2.44929e-15	
diff --git a/Examples/rc/rc-cache.lib b/Examples/rc/rc-cache.lib
new file mode 100644
index 00000000..35095f47
--- /dev/null
+++ b/Examples/rc/rc-cache.lib
@@ -0,0 +1,89 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C?
+ C_????_*
+ C_????
+ SMD*_c
+ Capacitor*
+$ENDFPLIST
+DRAW
+P 2 0 1 20  -80 -30  80 -30 N
+P 2 0 1 20  -80 30  80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 30 V V C CNN
+F3 "" 0 0 30 H V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 60 60 1 1 P
+X ~ 2 0 -150 50 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/rc/rc.bak b/Examples/rc/rc.bak
new file mode 100644
index 00000000..be41e011
--- /dev/null
+++ b/Examples/rc/rc.bak
@@ -0,0 +1,131 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Sources
+LIBS:rc-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L R R1
+U 1 1 556C372A
+P 5100 2300
+F 0 "R1" V 5180 2300 50  0000 C CNN
+F 1 "1k" V 5100 2300 50  0000 C CNN
+F 2 "" V 5030 2300 30  0000 C CNN
+F 3 "" H 5100 2300 30  0000 C CNN
+	1    5100 2300
+	0    1    1    0   
+$EndComp
+$Comp
+L C C1
+U 1 1 556C3744
+P 5600 2650
+F 0 "C1" H 5625 2750 50  0000 L CNN
+F 1 "1u" H 5625 2550 50  0000 L CNN
+F 2 "" H 5638 2500 30  0000 C CNN
+F 3 "" H 5600 2650 60  0000 C CNN
+	1    5600 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L sine v1
+U 1 1 556C37C5
+P 4650 2850
+F 0 "v1" H 4450 2950 60  0000 C CNN
+F 1 "sine" H 4450 2800 60  0000 C CNN
+F 2 "R1" H 4350 2850 60  0000 C CNN
+F 3 "" H 4650 2850 60  0000 C CNN
+	1    4650 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 556C3835
+P 5150 3400
+F 0 "#PWR01" H 5150 3150 50  0001 C CNN
+F 1 "GND" H 5150 3250 50  0000 C CNN
+F 2 "" H 5150 3400 60  0000 C CNN
+F 3 "" H 5150 3400 60  0000 C CNN
+	1    5150 3400
+	1    0    0    -1  
+$EndComp
+Text GLabel 5050 3400 0    60   Input ~ 0
+gnd
+Wire Wire Line
+	4650 2400 4650 2300
+Wire Wire Line
+	4650 2300 4950 2300
+Wire Wire Line
+	5250 2300 5600 2300
+Wire Wire Line
+	5600 2800 5600 3300
+Wire Wire Line
+	5600 3300 4650 3300
+Wire Wire Line
+	5150 3400 5150 3300
+Connection ~ 5150 3300
+Wire Wire Line
+	5050 3400 5100 3400
+Wire Wire Line
+	5100 3400 5100 3350
+Wire Wire Line
+	5100 3350 5150 3350
+Connection ~ 5150 3350
+Wire Wire Line
+	5600 2300 5600 2500
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 55795DBE
+P 5150 3300
+F 0 "#FLG02" H 5150 3395 50  0001 C CNN
+F 1 "PWR_FLAG" H 5150 3480 50  0000 C CNN
+F 2 "" H 5150 3300 60  0000 C CNN
+F 3 "" H 5150 3300 60  0000 C CNN
+	1    5150 3300
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/Examples/rc/rc.cir b/Examples/rc/rc.cir
new file mode 100644
index 00000000..1e5ca11e
--- /dev/null
+++ b/Examples/rc/rc.cir
@@ -0,0 +1,11 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jun 11 10:11:01 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+R1  1 4 1k		
+C1  1 2 1u		
+v1  4 2 sine		
+
+.end
diff --git a/Examples/rc/rc.cir.out b/Examples/rc/rc.cir.out
new file mode 100644
index 00000000..282ac877
--- /dev/null
+++ b/Examples/rc/rc.cir.out
@@ -0,0 +1,14 @@
+* eeschema netlist version 1.1 (spice format) creation date: thu jun 11 10:11:01 2015
+
+r1  1 4 1k
+c1  1 0 1u
+v1  4 0 sine(0 2 50 0 0)
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/rc/rc.pro b/Examples/rc/rc.pro
new file mode 100644
index 00000000..f1f5e0ac
--- /dev/null
+++ b/Examples/rc/rc.pro
@@ -0,0 +1,68 @@
+update=Wed Jun  3 15:51:38 2015
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
+LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
+LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
+LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
+LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
diff --git a/Examples/rc/rc.proj b/Examples/rc/rc.proj
new file mode 100644
index 00000000..c3d616a5
--- /dev/null
+++ b/Examples/rc/rc.proj
@@ -0,0 +1 @@
+schematicFile rc.sch
diff --git a/Examples/rc/rc.sch b/Examples/rc/rc.sch
new file mode 100644
index 00000000..7fa7a6d4
--- /dev/null
+++ b/Examples/rc/rc.sch
@@ -0,0 +1,131 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Sources
+LIBS:rc-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L R R1
+U 1 1 556C372A
+P 5100 2300
+F 0 "R1" V 5180 2300 50  0000 C CNN
+F 1 "1k" V 5100 2300 50  0000 C CNN
+F 2 "" V 5030 2300 30  0000 C CNN
+F 3 "" H 5100 2300 30  0000 C CNN
+	1    5100 2300
+	0    1    1    0   
+$EndComp
+$Comp
+L C C1
+U 1 1 556C3744
+P 5600 2650
+F 0 "C1" H 5625 2750 50  0000 L CNN
+F 1 "1u" H 5625 2550 50  0000 L CNN
+F 2 "" H 5638 2500 30  0000 C CNN
+F 3 "" H 5600 2650 60  0000 C CNN
+	1    5600 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L sine v1
+U 1 1 556C37C5
+P 4650 2850
+F 0 "v1" H 4450 2950 60  0000 C CNN
+F 1 "sine" H 4450 2800 60  0000 C CNN
+F 2 "R1" H 4350 2850 60  0000 C CNN
+F 3 "" H 4650 2850 60  0000 C CNN
+	1    4650 2850
+	1    0    0    -1  
+$EndComp
+Text GLabel 5050 3400 0    60   Input ~ 0
+gnd
+Wire Wire Line
+	4650 2400 4650 2300
+Wire Wire Line
+	4650 2300 4950 2300
+Wire Wire Line
+	5250 2300 5600 2300
+Wire Wire Line
+	5600 2800 5600 3300
+Wire Wire Line
+	5600 3300 4650 3300
+Connection ~ 5150 3300
+Wire Wire Line
+	5050 3400 5100 3400
+Wire Wire Line
+	5100 3400 5100 3350
+Wire Wire Line
+	5100 3350 5150 3350
+Connection ~ 5150 3350
+Wire Wire Line
+	5600 2300 5600 2500
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 55795DBE
+P 5150 3300
+F 0 "#FLG01" H 5150 3395 50  0001 C CNN
+F 1 "PWR_FLAG" H 5150 3480 50  0000 C CNN
+F 2 "" H 5150 3300 60  0000 C CNN
+F 3 "" H 5150 3300 60  0000 C CNN
+	1    5150 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 55796439
+P 5150 3400
+F 0 "#PWR?" H 5150 3400 30  0001 C CNN
+F 1 "GND" H 5150 3330 30  0001 C CNN
+F 2 "" H 5150 3400 60  0000 C CNN
+F 3 "" H 5150 3400 60  0000 C CNN
+	1    5150 3400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5150 3300 5150 3400
+$EndSCHEMATC