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authorFahim2016-03-03 23:00:00 +0530
committerFahim2016-03-03 23:00:00 +0530
commit7e4774656997c34eae3ab09b37c8f82b5b046d48 (patch)
treefe72483af0c1feba7f97d5b9290f647f50840fc1 /Examples/hwr6/scr.sub~
parent823d892cbafccc47287ffebd01316754e7efad56 (diff)
downloadeSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.gz
eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.bz2
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Remove unwanted example
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-rw-r--r--Examples/hwr6/scr.sub~23
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diff --git a/Examples/hwr6/scr.sub~ b/Examples/hwr6/scr.sub~
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-* Subcircuit scr
-.subckt scr 3 7 1
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-.include PowerDiode.lib
-* f2
-d1 5 2 PowerDiode
-c1 3 9 10u
-* f1
-v1 8 4 dc 0
-v2 6 5 dc 0
-* u1 9 1 6 aswitch
-r1 7 8 50
-r2 3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 [1 6 ] u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
-* Control Statements
-
-.ends scr \ No newline at end of file