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| author | Fahim | 2016-03-03 23:00:00 +0530 |
|---|---|---|
| committer | Fahim | 2016-03-03 23:00:00 +0530 |
| commit | 7e4774656997c34eae3ab09b37c8f82b5b046d48 (patch) | |
| tree | fe72483af0c1feba7f97d5b9290f647f50840fc1 /Examples/fullwaverec/scr.sub~ | |
| parent | 823d892cbafccc47287ffebd01316754e7efad56 (diff) | |
| download | eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.gz eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.bz2 eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.zip | |
Remove unwanted example
Diffstat (limited to 'Examples/fullwaverec/scr.sub~')
| -rw-r--r-- | Examples/fullwaverec/scr.sub~ | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/Examples/fullwaverec/scr.sub~ b/Examples/fullwaverec/scr.sub~ deleted file mode 100644 index 5e23f45d..00000000 --- a/Examples/fullwaverec/scr.sub~ +++ /dev/null @@ -1,24 +0,0 @@ -* Subcircuit scr -.subckt scr 3 5 1 -* /opt/esim/src/subcircuitlibrary/scr/scr.cir -.include D.lib -* f2 -d1 8 2 D1N750 -c1 3 4 10u -r2 3 4 1 -* f1 -r1 5 6 50 -v1 6 7 dc 0 -v2 9 8 dc 0 -* u1 4 1 9 aswitch -Vf2 2 3 0 -f2 3 4 Vf2 100 -Vf1 7 3 0 -f1 3 4 Vf1 10 -a1 4 (1 9) u1 -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) - -* Control Statements - -.ends scr |