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| author | saurabhb17 | 2019-12-30 14:25:28 +0530 |
|---|---|---|
| committer | saurabhb17 | 2019-12-30 14:25:28 +0530 |
| commit | b160249024764015260d6091962271d97d19b324 (patch) | |
| tree | d657a8fb0ed7595215e8eeb0df959623c63b58b5 /Examples/NGHDL_Examples/decadecounter/nghdl-count/nghdl-count.cir.out | |
| parent | 0fcd69b197c8c8ee99aec740f0345d6f761fd936 (diff) | |
| download | eSim-b160249024764015260d6091962271d97d19b324.tar.gz eSim-b160249024764015260d6091962271d97d19b324.tar.bz2 eSim-b160249024764015260d6091962271d97d19b324.zip | |
lm555 subcircuit modified
Diffstat (limited to 'Examples/NGHDL_Examples/decadecounter/nghdl-count/nghdl-count.cir.out')
| -rw-r--r-- | Examples/NGHDL_Examples/decadecounter/nghdl-count/nghdl-count.cir.out | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/Examples/NGHDL_Examples/decadecounter/nghdl-count/nghdl-count.cir.out b/Examples/NGHDL_Examples/decadecounter/nghdl-count/nghdl-count.cir.out new file mode 100644 index 00000000..57e03ec2 --- /dev/null +++ b/Examples/NGHDL_Examples/decadecounter/nghdl-count/nghdl-count.cir.out @@ -0,0 +1,63 @@ +* /home/saurabh/esim-examples/decade_counter/nghdl-count/nghdl-count.cir + +v1 clock gnd pulse(0 5 0 0 0 0.0005 0.001) +v2 rst gnd pulse(0 0 0 0 0 0 0) +* u2 clock plot_v1 +* u3 rst plot_v1 +r10 out1 gnd 1k +* u8 out8 plot_v1 +* u10 out7 plot_v1 +* u11 out6 plot_v1 +* u12 out5 plot_v1 +* u13 out4 plot_v1 +* u14 out3 plot_v1 +* u15 out2 plot_v1 +* u16 out1 plot_v1 +r9 out2 gnd 1k +r8 out3 gnd 1k +r7 out4 gnd 1k +r6 out5 gnd 1k +r5 out6 gnd 1k +r3 out7 gnd 1k +r1 out8 gnd 1k +r2 out9 gnd 1k +r4 out10 gnd 1k +* u7 out9 plot_v1 +* u9 out10 plot_v1 +* u6 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ out1 out2 out3 out4 out5 out6 out7 out8 dac_bridge_8 +* u4 clock rst net-_u1-pad1_ net-_u1-pad2_ adc_bridge_2 +* u5 net-_u1-pad11_ net-_u1-pad12_ out9 out10 dac_bridge_2 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ decadecounter +a1 [net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ ] [out1 out2 out3 out4 out5 out6 out7 out8 ] u6 +a2 [clock rst ] [net-_u1-pad1_ net-_u1-pad2_ ] u4 +a3 [net-_u1-pad11_ net-_u1-pad12_ ] [out9 out10 ] u5 +a4 [net-_u1-pad1_ ] [net-_u1-pad2_ ] [net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ ] u1 +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u4 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: decadecounter, NgSpice Name: decadecounter +.model u1 decadecounter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 instance_id=1 ) +.tran 10e-06 20e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(clock) +plot v(rst) +plot v(out8) +plot v(out7) +plot v(out6) +plot v(out5) +plot v(out4) +plot v(out3) +plot v(out2) +plot v(out1) +plot v(out9) +plot v(out10) +.endc +.end |