common code for Win and Linux, merged py2 changes

19 files changed, 1808 insertions, 0 deletions

diff --git a/Examples/NGHDL_Examples/PWM_Incremental/NPN.lib b/Examples/NGHDL_Examples/PWM_Incremental/NPN.lib
new file mode 100644
index 00000000..6509fe7a
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PNP.lib b/Examples/NGHDL_Examples/PWM_Incremental/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental-cache.lib b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental-cache.lib
new file mode 100644
index 00000000..96aae32d
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental-cache.lib
@@ -0,0 +1,169 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "C" 25 -100 50 H V L CNN
+F2 "" 38 -150 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 110 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# lm_741
+#
+DEF lm_741 X 0 40 Y Y 1 F N
+F0 "X" -200 0 60 H V C CNN
+F1 "lm_741" -100 -250 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N
+X off_null 1 -50 400 200 D 50 38 1 1 I
+X inv 2 -550 150 200 R 50 38 1 1 I
+X non_inv 3 -550 -100 200 R 50 38 1 1 I
+X v_neg 4 -150 -450 200 U 50 38 1 1 I
+X off_null 5 50 350 200 D 50 38 1 1 I
+X out 6 550 0 200 L 50 38 1 1 O
+X v_pos 7 -150 450 200 D 50 38 1 1 I
+X NC 8 150 -300 200 U 50 38 1 1 N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# pwmincrement
+#
+DEF pwmincrement U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "pwmincrement" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2550 2100 3150 1600 0 1 0 N
+X in1 1 2350 1900 200 R 50 50 1 1 I
+X in2 2 2350 1800 200 R 50 50 1 1 I
+X out1 3 3350 1900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir
new file mode 100644
index 00000000..e04c64f0
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir
@@ -0,0 +1,26 @@
+* /home/saurabh/eSim-Workspace/PWM_Incremental/PWM_Incremental.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Nov 14 23:08:06 2019
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v2  Net-_X1-Pad7_ GND 9v		
+U3  D plot_v1		
+X1  ? rc1 pwl_IN Net-_X1-Pad4_ ? D Net-_X1-Pad7_ ? lm_741		
+R1  Q rc1 1k		
+U7  rc1 plot_v1		
+C1  GND rc1 1u		
+U8  Net-_U2-Pad3_ Q dac_bridge_1		
+U9  Q plot_v1		
+U6  clk plot_v1		
+v4  Net-_U4-Pad1_ GND pulse		
+U5  D Net-_U2-Pad2_ adc_bridge_1		
+U4  Net-_U4-Pad1_ clk adc_bridge_1		
+v3  Net-_X1-Pad4_ GND -9v		
+U1  pwl_IN plot_v1		
+v1  pwl_IN GND 3		
+U2  clk Net-_U2-Pad2_ Net-_U2-Pad3_ pwmincrement		
+
+.end
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir.out b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir.out
new file mode 100644
index 00000000..4d222d7b
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.cir.out
@@ -0,0 +1,45 @@
+* /home/saurabh/esim-workspace/pwm_incremental/pwm_incremental.cir
+
+.include lm_741.sub
+v2  net-_x1-pad7_ gnd 9v
+* u3  d plot_v1
+x1 ? rc1 pwl_in net-_x1-pad4_ ? d net-_x1-pad7_ ? lm_741
+r1  q rc1 1k
+* u7  rc1 plot_v1
+c1  gnd rc1 1u
+* u8  net-_u2-pad3_ q dac_bridge_1
+* u9  q plot_v1
+* u6  clk plot_v1
+v4  net-_u4-pad1_ gnd pulse(0 5 10u 10u 20u 0.5m 1m)
+* u5  d net-_u2-pad2_ adc_bridge_1
+* u4  net-_u4-pad1_ clk adc_bridge_1
+v3  net-_x1-pad4_ gnd -9v
+* u1  pwl_in plot_v1
+v1  pwl_in gnd 3
+* u2  clk net-_u2-pad2_ net-_u2-pad3_ pwmincrement
+a1 [net-_u2-pad3_ ] [q ] u8
+a2 [d ] [net-_u2-pad2_ ] u5
+a3 [net-_u4-pad1_ ] [clk ] u4
+a4 [clk ] [net-_u2-pad2_ ] [net-_u2-pad3_ ] u2
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u8 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u4 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: pwmincrement, NgSpice Name: pwmincrement
+.model u2 pwmincrement(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 instance_id=1 stop_time=100e-3 ) 
+.tran 1e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(d)
+plot v(rc1)
+plot v(q)
+plot v(clk)
+plot v(pwl_in)
+.endc
+.end
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.pro b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.pro
new file mode 100644
index 00000000..31e63107
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.pro
@@ -0,0 +1,73 @@
+update=Thu Nov 14 23:00:31 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=switches
+LibName4=relays
+LibName5=motors
+LibName6=transistors
+LibName7=conn
+LibName8=linear
+LibName9=regul
+LibName10=74xx
+LibName11=cmos4000
+LibName12=adc-dac
+LibName13=memory
+LibName14=xilinx
+LibName15=microcontrollers
+LibName16=dsp
+LibName17=microchip
+LibName18=analog_switches
+LibName19=motorola
+LibName20=texas
+LibName21=intel
+LibName22=audio
+LibName23=interface
+LibName24=digital-audio
+LibName25=philips
+LibName26=display
+LibName27=cypress
+LibName28=siliconi
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_User
+LibName38=eSim_Plot
+LibName39=eSim_PSpice
+LibName40=/home/saurabh/eSim_kicad
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.proj b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.proj
new file mode 100644
index 00000000..5bb660af
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.proj
@@ -0,0 +1 @@
+schematicFile PWM_Incremental.sch
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.sch b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.sch
new file mode 100644
index 00000000..dbb48d87
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental.sch
@@ -0,0 +1,435 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:switches
+LIBS:relays
+LIBS:motors
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:eSim_kicad
+LIBS:PWM_Incremental-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
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+Comment4 ""
+$EndDescr
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+F 2 "R1" H 3450 5150 60  0000 C CNN
+F 3 "" H 3750 5150 60  0000 C CNN
+	1    3750 5150
+	0    1    1    0   
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 5DCD900D
+P 2800 4100
+F 0 "U1" H 2800 4600 60  0000 C CNN
+F 1 "plot_v1" H 3000 4450 60  0000 C CNN
+F 2 "" H 2800 4100 60  0000 C CNN
+F 3 "" H 2800 4100 60  0000 C CNN
+	1    2800 4100
+	1    0    0    -1  
+$EndComp
+Text GLabel 2800 3900 3    60   Input ~ 0
+pwl_IN
+$Comp
+L DC v1
+U 1 1 5DCD9113
+P 2050 3900
+F 0 "v1" H 1850 4000 60  0000 C CNN
+F 1 "3" H 1850 3850 60  0000 C CNN
+F 2 "R1" H 1750 3900 60  0000 C CNN
+F 3 "" H 2050 3900 60  0000 C CNN
+	1    2050 3900
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	3700 3200 4300 3200
+Wire Wire Line
+	4300 3200 4300 3700
+Wire Wire Line
+	4300 4600 4300 5150
+Wire Wire Line
+	5000 4150 5150 4150
+Wire Wire Line
+	5400 4000 5400 4600
+Wire Wire Line
+	5550 4300 5400 4300
+Connection ~ 5400 4300
+Connection ~ 2800 3900
+Wire Wire Line
+	2500 3900 3050 3900
+Wire Wire Line
+	3050 3900 3050 4400
+Wire Wire Line
+	2700 3300 2700 3200
+Wire Wire Line
+	2700 3200 2800 3200
+Connection ~ 4300 5150
+Wire Wire Line
+	3150 4250 3900 4250
+Wire Wire Line
+	3550 4000 3900 4000
+Wire Wire Line
+	6550 4450 6850 4450
+Wire Wire Line
+	6850 4450 6850 4650
+Wire Wire Line
+	6250 4600 6250 4450
+Wire Wire Line
+	7050 4500 7050 4200
+Wire Wire Line
+	6850 4500 9300 4500
+Connection ~ 6850 4500
+Wire Wire Line
+	7300 4450 7050 4450
+Wire Wire Line
+	4300 5150 4200 5150
+Wire Wire Line
+	8900 1850 9300 1850
+Wire Wire Line
+	9050 1850 9050 3050
+Connection ~ 9050 1850
+Connection ~ 6100 4600
+Connection ~ 5150 4150
+Wire Wire Line
+	6250 1850 6250 2550
+Connection ~ 6250 2200
+Wire Wire Line
+	9250 2350 9200 2350
+Wire Wire Line
+	9200 2350 9200 1850
+Connection ~ 9200 1850
+Wire Wire Line
+	6500 2500 6250 2500
+Connection ~ 6250 2500
+Wire Wire Line
+	6100 1850 6400 1850
+Connection ~ 6250 1850
+Wire Wire Line
+	6400 1950 6150 1950
+Wire Wire Line
+	6150 1950 6150 2200
+Wire Notes Line
+	1200 5750 4850 5750
+Wire Notes Line
+	1200 5750 1200 2450
+Wire Notes Line
+	1200 2450 4150 2450
+Wire Notes Line
+	4150 2450 4150 3150
+Wire Notes Line
+	4150 3150 4850 3150
+Wire Notes Line
+	4850 3150 4850 5750
+Wire Notes Line
+	5950 3900 5950 5300
+Wire Notes Line
+	5950 5300 8050 5300
+Wire Notes Line
+	8050 5300 8050 3600
+Wire Notes Line
+	8050 3600 5900 3600
+Wire Notes Line
+	5900 3600 5900 3950
+Wire Notes Line
+	5900 3950 5950 3950
+Wire Wire Line
+	3150 4250 3150 4400
+Wire Wire Line
+	3150 4400 3050 4400
+Wire Wire Line
+	6850 4950 6850 5450
+Wire Wire Line
+	2650 3700 3550 3700
+Wire Wire Line
+	3550 3700 3550 4000
+Wire Wire Line
+	2650 3750 2650 3700
+Wire Wire Line
+	5150 2450 5150 4600
+Wire Wire Line
+	2550 6400 9300 6400
+Wire Wire Line
+	2550 6400 2550 3750
+Wire Wire Line
+	9050 3050 6100 3050
+Wire Wire Line
+	4500 1850 4950 1850
+Wire Wire Line
+	4750 2200 5000 2200
+Wire Wire Line
+	4750 2450 4750 2200
+Wire Wire Line
+	5150 2450 4750 2450
+Wire Wire Line
+	4500 1850 4500 2250
+Wire Wire Line
+	5150 4600 5400 4600
+Wire Wire Line
+	6100 3050 6100 4600
+Wire Wire Line
+	6100 4600 6250 4600
+Wire Wire Line
+	2550 3750 2650 3750
+Connection ~ 7050 4450
+Connection ~ 7050 4500
+Wire Wire Line
+	7400 1850 7750 1850
+Wire Wire Line
+	9300 6400 9300 4500
+$Comp
+L pwmincrement U2
+U 1 1 5DCD9189
+P 4050 3750
+F 0 "U2" H 6900 5550 60  0000 C CNN
+F 1 "pwmincrement" H 6900 5750 60  0000 C CNN
+F 2 "" H 6900 5700 60  0000 C CNN
+F 3 "" H 6900 5700 60  0000 C CNN
+	1    4050 3750
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental_Previous_Values.xml b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental_Previous_Values.xml
new file mode 100644
index 00000000..bd749bf9
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/PWM_Incremental_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1m</field2><field3 name="Stop Time">100m</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source><v2 name="Source type">9v</v2><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">10u</field3><field4 name="Rise Time">10u</field4><field5 name="Fall Time">20u</field5><field5 name="Pulse width">0.5m</field5><field5 name="Period">1m</field5></v4><v3 name="Source type">-9v</v3><v1 name="Source type">3</v1></source><model><u8 name="type">dac_bridge<field1 name="Enter value for input load (default=1.0e-12)" /><field2 name="Enter value for out_low (default=0.0)" /><field3 name="Enter value for out_high (default=5.0)" /><field4 name="Enter the Rise Time (default=1.0e-9)" /><field5 name="Enter the Fall Time (default=1.0e-9)" /><field6 name="Enter value for out_undef (default=0.5)" /></u8><u5 name="type">adc_bridge<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter value for in_high (default=2.0)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter value for in_low (default=1.0)" /></u5><u4 name="type">adc_bridge<field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter value for in_low (default=1.0)" /></u4><u2 name="type">pwmincrement<field15 name="Enter Fall Delay (default=1.0e-9)" /><field16 name="Enter Input Load (default=1.0e-12)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Instance ID (Between 0-99)" /><field19 name="Enter the stop time to end the simulation (default=90e-9)">100e-3</field19></u2></model><devicemodel /><subcircuit><x1><field>/home/saurabh/Downloads/eSim-rahulp13-eSim/src/SubcircuitLibrary/lm_741</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/analysis b/Examples/NGHDL_Examples/PWM_Incremental/analysis
new file mode 100644
index 00000000..93ae8d31
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/analysis
@@ -0,0 +1 @@
+.tran 1me-00 100me-00 0e-03
\ No newline at end of file
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741-cache.lib b/Examples/NGHDL_Examples/PWM_Incremental/lm_741-cache.lib
new file mode 100644
index 00000000..04e3fecd
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741-cache.lib
@@ -0,0 +1,119 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20  -80 -30  80 -30 N
+P 2 0 1 20  -80 30  80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  25 25  100 100 N
+P 3 0 1 0  25 -25  100 -100  100 -100 N
+P 3 0 1 20  25 75  25 -75  25 -75 N
+P 5 0 1 0  50 -70  70 -50  90 -90  50 -70  50 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0  25 25  100 100 N
+P 3 0 1 0  25 -25  100 -100  100 -100 N
+P 3 0 1 20  25 75  25 -75  25 -75 N
+P 5 0 1 0  90 -70  70 -90  50 -50  90 -70  90 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir
new file mode 100644
index 00000000..4a5917ea
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir
@@ -0,0 +1,43 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+Q2  Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
+Q6  Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP		
+Q5  Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP		
+Q3  Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN		
+Q4  Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
+Q9  Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
+Q8  Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN		
+Q7  Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN		
+R1  Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k		
+R2  Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k		
+R3  Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k		
+Q12  Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN		
+Q13  Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN		
+R4  Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k		
+R11  Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k		
+Q10  Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
+Q11  Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP		
+Q14  Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN		
+R8  Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k		
+R7  Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 30p		
+Q16  Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN		
+Q15  Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN		
+R5  Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k		
+R6  Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50		
+Q17  Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN		
+Q18  Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN		
+Q20  Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN		
+R9  Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25		
+R10  Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50		
+Q19  Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP		
+U1  Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT		
+
+.end
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir.out b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir.out
new file mode 100644
index 00000000..a00bd86a
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.cir.out
@@ -0,0 +1,46 @@
+* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
+
+.include npn_1.lib
+.include pnp_1.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
+q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
+q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
+q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
+q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
+q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
+r1  net-_q7-pad3_ net-_q12-pad3_ 1k
+r2  net-_q3-pad3_ net-_q12-pad3_ 50k
+r3  net-_q8-pad3_ net-_q12-pad3_ 1k
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
+q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
+r4  net-_q13-pad3_ net-_q12-pad3_ 5k
+r11  net-_q10-pad1_ net-_q12-pad1_ 39k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
+r8  net-_c1-pad1_ net-_q14-pad2_ 4.5k
+r7  net-_q14-pad3_ net-_q14-pad2_ 7.5k
+c1  net-_c1-pad1_ net-_c1-pad2_ 30p
+q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
+q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
+r5  net-_q15-pad2_ net-_q12-pad3_ 50k
+r6  net-_q15-pad3_ net-_q12-pad3_ 50
+q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
+q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
+q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
+r9  net-_q18-pad3_ net-_q20-pad3_ 25
+r10  net-_q20-pad3_ net-_q19-pad3_ 50
+q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
+* u1  net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.pro b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.pro
new file mode 100644
index 00000000..cbe83f35
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.pro
@@ -0,0 +1,45 @@
+update=Fri Jun  7 21:53:51 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sch b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sch
new file mode 100644
index 00000000..b017fd2b
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sch
@@ -0,0 +1,697 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:lm_741-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
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diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sub b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sub
new file mode 100644
index 00000000..fa8d27b1
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741.sub
@@ -0,0 +1,40 @@
+* Subcircuit lm_741
+.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? 
+* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
+.include npn_1.lib
+.include pnp_1.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
+q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
+q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
+q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
+q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
+q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
+r1  net-_q7-pad3_ net-_q12-pad3_ 1k
+r2  net-_q3-pad3_ net-_q12-pad3_ 50k
+r3  net-_q8-pad3_ net-_q12-pad3_ 1k
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
+q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
+r4  net-_q13-pad3_ net-_q12-pad3_ 5k
+r11  net-_q10-pad1_ net-_q12-pad1_ 39k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
+r8  net-_c1-pad1_ net-_q14-pad2_ 4.5k
+r7  net-_q14-pad3_ net-_q14-pad2_ 7.5k
+c1  net-_c1-pad1_ net-_c1-pad2_ 30p
+q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
+q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
+r5  net-_q15-pad2_ net-_q12-pad3_ 50k
+r6  net-_q15-pad3_ net-_q12-pad3_ 50
+q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
+q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
+q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
+r9  net-_q18-pad3_ net-_q20-pad3_ 25
+r10  net-_q20-pad3_ net-_q19-pad3_ 50
+q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
+* Control Statements
+
+.ends lm_741
\ No newline at end of file
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/lm_741_Previous_Values.xml b/Examples/NGHDL_Examples/PWM_Incremental/lm_741_Previous_Values.xml
new file mode 100644
index 00000000..b61322bb
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/lm_741_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/npn_1.lib b/Examples/NGHDL_Examples/PWM_Incremental/npn_1.lib
new file mode 100644
index 00000000..a1818ed8
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/npn_1.lib
@@ -0,0 +1,29 @@
+.model npn_1 NPN(
++ Vtf=1.7 
++ Cjc=0.5p
++ Nc=2 
++ Tr=46.91n 
++ Ne=1.307 
++ Cje=0.5p
++ Isc=0 
++ Xtb=1.5 
++ Rb=500
++ Rc=1 
++ Tf=411.1p 
++ Xti=3 
++ Ikr=0 
++ Bf=125
++ Fc=.5 
++ Ise=14.34f 
++ Br=6.092 
++ Ikf=.2847 
++ Mje=.377 
++ Mjc=.3416 
++ Vaf=74.03 
++ Vjc=.75 
++ Vje=.75 
++ Xtf=3 
++ Itf=.6 
++ Is=14.34f 
++ Eg=1.11 
+)
\ No newline at end of file
diff --git a/Examples/NGHDL_Examples/PWM_Incremental/pnp_1.lib b/Examples/NGHDL_Examples/PWM_Incremental/pnp_1.lib
new file mode 100644
index 00000000..a4ee06da
--- /dev/null
+++ b/Examples/NGHDL_Examples/PWM_Incremental/pnp_1.lib
@@ -0,0 +1,29 @@
+.model pnp_1 PNP(
++ Vtf=1.7 
++ Cjc=1.5p
++ Nc=2 
++ Tr=46.91n 
++ Ne=1.307 
++ Cje=0.3p
++ Isc=0 
++ Xtb=1.5 
++ Rb=250
++ Rc=1 
++ Tf=411.1p 
++ Xti=3 
++ Ikr=0 
++ Bf=25
++ Fc=.5 
++ Ise=14.34f 
++ Br=6.092 
++ Ikf=.2847 
++ Mje=.377 
++ Mjc=.3416 
++ Vaf=74.03 
++ Vjc=.75 
++ Vje=.75 
++ Xtf=3 
++ Itf=.6 
++ Is=14.34f 
++ Eg=1.11 
+)
\ No newline at end of file