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| author | saurabhb17 | 2019-11-27 15:29:09 +0530 |
|---|---|---|
| committer | saurabhb17 | 2019-11-27 16:50:53 +0530 |
| commit | 80bb2f1330465586d17347bcb9a6d1d1135cb3f1 (patch) | |
| tree | b82a518292f5fc32fef72f4cdaa81de2e44f3cde /Examples/NGHDL_Examples/Cmosinverter/inverter.vhdl | |
| parent | 50835cefd437c670752da7e8c857297c926daef3 (diff) | |
| download | eSim-80bb2f1330465586d17347bcb9a6d1d1135cb3f1.tar.gz eSim-80bb2f1330465586d17347bcb9a6d1d1135cb3f1.tar.bz2 eSim-80bb2f1330465586d17347bcb9a6d1d1135cb3f1.zip | |
NGHDL Examples added
Diffstat (limited to 'Examples/NGHDL_Examples/Cmosinverter/inverter.vhdl')
| -rw-r--r-- | Examples/NGHDL_Examples/Cmosinverter/inverter.vhdl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Examples/NGHDL_Examples/Cmosinverter/inverter.vhdl b/Examples/NGHDL_Examples/Cmosinverter/inverter.vhdl new file mode 100644 index 00000000..8a6b638e --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/inverter.vhdl @@ -0,0 +1,12 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity inverter is + port ( i: in std_logic_vector(0 downto 0); + o: out std_logic_vector(0 downto 0)); +end inverter; + +architecture inverter_beh of inverter is +begin + o <= not i; +end inverter_beh; |