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author | saurabhb17 | 2019-11-27 15:29:09 +0530 |
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committer | saurabhb17 | 2019-11-27 16:50:53 +0530 |
commit | 80bb2f1330465586d17347bcb9a6d1d1135cb3f1 (patch) | |
tree | b82a518292f5fc32fef72f4cdaa81de2e44f3cde /Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir | |
parent | 50835cefd437c670752da7e8c857297c926daef3 (diff) | |
download | eSim-80bb2f1330465586d17347bcb9a6d1d1135cb3f1.tar.gz eSim-80bb2f1330465586d17347bcb9a6d1d1135cb3f1.tar.bz2 eSim-80bb2f1330465586d17347bcb9a6d1d1135cb3f1.zip |
NGHDL Examples added
Diffstat (limited to 'Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir')
-rw-r--r-- | Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end |