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| author | saurabhb17 | 2019-11-27 15:29:09 +0530 |
|---|---|---|
| committer | saurabhb17 | 2019-11-27 16:50:53 +0530 |
| commit | 80bb2f1330465586d17347bcb9a6d1d1135cb3f1 (patch) | |
| tree | b82a518292f5fc32fef72f4cdaa81de2e44f3cde /Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir | |
| parent | 50835cefd437c670752da7e8c857297c926daef3 (diff) | |
| download | eSim-80bb2f1330465586d17347bcb9a6d1d1135cb3f1.tar.gz eSim-80bb2f1330465586d17347bcb9a6d1d1135cb3f1.tar.bz2 eSim-80bb2f1330465586d17347bcb9a6d1d1135cb3f1.zip | |
NGHDL Examples added
Diffstat (limited to 'Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir')
| -rw-r--r-- | Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir new file mode 100644 index 00000000..7736c9d0 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir @@ -0,0 +1,26 @@ +* /home/saurabh/eSim-Workspace/Cmosinvertor/Cmosinvertor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Nov 27 14:17:36 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 out1 plot_v1 +X1 out7 out1 INVCMOS +X2 out1 out2 INVCMOS +X3 out2 out3 INVCMOS +U3 out2 plot_v1 +U4 out3 plot_v1 +X4 out3 out4 INVCMOS +U5 out4 plot_v1 +X5 out4 out5 INVCMOS +U6 out5 plot_v1 +X6 out5 out6 INVCMOS +U7 out6 plot_v1 +U8 out7 plot_v1 +U9 out6 Net-_U1-Pad1_ adc_bridge_1 +U10 Net-_U1-Pad2_ out7 dac_bridge_1 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ inverter + +.end |