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| author | saurabhb17 | 2019-12-30 14:25:28 +0530 |
|---|---|---|
| committer | saurabhb17 | 2019-12-30 14:25:28 +0530 |
| commit | b160249024764015260d6091962271d97d19b324 (patch) | |
| tree | d657a8fb0ed7595215e8eeb0df959623c63b58b5 /Examples/Monostable555/lm555n.sub | |
| parent | 0fcd69b197c8c8ee99aec740f0345d6f761fd936 (diff) | |
| download | eSim-b160249024764015260d6091962271d97d19b324.tar.gz eSim-b160249024764015260d6091962271d97d19b324.tar.bz2 eSim-b160249024764015260d6091962271d97d19b324.zip | |
lm555 subcircuit modified
Diffstat (limited to 'Examples/Monostable555/lm555n.sub')
| -rw-r--r-- | Examples/Monostable555/lm555n.sub | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/Examples/Monostable555/lm555n.sub b/Examples/Monostable555/lm555n.sub index beeefc43..b524f5c6 100644 --- a/Examples/Monostable555/lm555n.sub +++ b/Examples/Monostable555/lm555n.sub @@ -1,5 +1,6 @@ * Subcircuit lm555n -.subckt lm555n 22 14 7 6 15 16 3 13 +.subckt lm555n 22 14 7 6 15 16 3 13 +.include npn_1.lib * eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist * Inverter d_inverter * SR Latch d_srlatch @@ -8,7 +9,7 @@ e2 18 0 23 14 10000 * Digital to Analog converter dac8 * Analog to Digital converter adc8 r8 9 2 1500 -q1 3 2 22 qnom +q1 3 2 22 npn_1 r7 18 20 25 r6 17 19 25 e1 17 0 16 15 10000 @@ -33,5 +34,6 @@ a7 [11] [4] u2 a8 [12] [1] u2 a9 [6] [5] u2 .model u2 adc_bridge(in_low=0.8 in_high=2.0 ) +*control statements -.ends lm555n
\ No newline at end of file +.ends lm555n |