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| author | Rahul P | 2020-08-08 19:16:28 +0530 |
|---|---|---|
| committer | GitHub | 2020-08-08 19:16:28 +0530 |
| commit | 8255c72075ab3541e8b6cfa7facb4e016157a905 (patch) | |
| tree | e86226cc6a609e54133b527ad71912996360722b /Examples/Mixed_Signal/Cmosinverter/INVCMOS.cir | |
| parent | 175208c2553bde875968a9bc53176b6039ba9360 (diff) | |
| parent | 7871e58975d75eb2b02928f7a48d29113bebeb2b (diff) | |
| download | eSim-8255c72075ab3541e8b6cfa7facb4e016157a905.tar.gz eSim-8255c72075ab3541e8b6cfa7facb4e016157a905.tar.bz2 eSim-8255c72075ab3541e8b6cfa7facb4e016157a905.zip | |
Merge pull request #156 from rahulp13/master
ported GUI to PyQt5; platform independent paths; launch ngspice through mintty on Win OS
Diffstat (limited to 'Examples/Mixed_Signal/Cmosinverter/INVCMOS.cir')
| -rw-r--r-- | Examples/Mixed_Signal/Cmosinverter/INVCMOS.cir | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Examples/Mixed_Signal/Cmosinverter/INVCMOS.cir b/Examples/Mixed_Signal/Cmosinverter/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/Examples/Mixed_Signal/Cmosinverter/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end |