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author | Rahul P | 2020-08-08 19:16:28 +0530 |
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committer | GitHub | 2020-08-08 19:16:28 +0530 |
commit | 8255c72075ab3541e8b6cfa7facb4e016157a905 (patch) | |
tree | e86226cc6a609e54133b527ad71912996360722b /Examples/Mixed_Signal/Cmosinverter/Cmosinverter.sch | |
parent | 175208c2553bde875968a9bc53176b6039ba9360 (diff) | |
parent | 7871e58975d75eb2b02928f7a48d29113bebeb2b (diff) | |
download | eSim-8255c72075ab3541e8b6cfa7facb4e016157a905.tar.gz eSim-8255c72075ab3541e8b6cfa7facb4e016157a905.tar.bz2 eSim-8255c72075ab3541e8b6cfa7facb4e016157a905.zip |
Merge pull request #156 from rahulp13/master
ported GUI to PyQt5; platform independent paths; launch ngspice through mintty on Win OS
Diffstat (limited to 'Examples/Mixed_Signal/Cmosinverter/Cmosinverter.sch')
-rw-r--r-- | Examples/Mixed_Signal/Cmosinverter/Cmosinverter.sch | 303 |
1 files changed, 303 insertions, 0 deletions
diff --git a/Examples/Mixed_Signal/Cmosinverter/Cmosinverter.sch b/Examples/Mixed_Signal/Cmosinverter/Cmosinverter.sch new file mode 100644 index 00000000..7abedbb2 --- /dev/null +++ b/Examples/Mixed_Signal/Cmosinverter/Cmosinverter.sch @@ -0,0 +1,303 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:Cmosinvertor-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L plot_v1 U2 +U 1 1 5D6266E9 +P 4350 1950 +F 0 "U2" H 4350 2450 60 0000 C CNN +F 1 "plot_v1" H 4550 2300 60 0000 C CNN +F 2 "" H 4350 1950 60 0000 C CNN +F 3 "" H 4350 1950 60 0000 C CNN + 1 4350 1950 + 1 0 0 -1 +$EndComp +Text GLabel 4350 2100 3 60 Input ~ 0 +out1 +$Comp +L INVCMOS X1 +U 1 1 5D626E20 +P 3200 1850 +F 0 "X1" H 3200 1850 60 0000 C CNN +F 1 "INVCMOS" H 2750 2000 60 0000 C CNN +F 2 "" H 3200 1850 60 0001 C CNN +F 3 "" H 3200 1850 60 0001 C CNN + 1 3200 1850 + 1 0 0 -1 +$EndComp +$Comp +L INVCMOS X2 +U 1 1 5D626E52 +P 5400 1850 +F 0 "X2" H 5400 1850 60 0000 C CNN +F 1 "INVCMOS" H 4950 2000 60 0000 C CNN +F 2 "" H 5400 1850 60 0001 C CNN +F 3 "" H 5400 1850 60 0001 C CNN + 1 5400 1850 + 1 0 0 -1 +$EndComp +$Comp +L INVCMOS X3 +U 1 1 5D626EC9 +P 7000 1850 +F 0 "X3" H 7000 1850 60 0000 C CNN +F 1 "INVCMOS" H 6550 2000 60 0000 C CNN +F 2 "" H 7000 1850 60 0001 C CNN +F 3 "" H 7000 1850 60 0001 C CNN + 1 7000 1850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5D626F62 +P 6200 1950 +F 0 "U3" H 6200 2450 60 0000 C CNN +F 1 "plot_v1" H 6400 2300 60 0000 C CNN +F 2 "" H 6200 1950 60 0000 C CNN +F 3 "" H 6200 1950 60 0000 C CNN + 1 6200 1950 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5D626FB9 +P 8000 1950 +F 0 "U4" H 8000 2450 60 0000 C CNN +F 1 "plot_v1" H 8200 2300 60 0000 C CNN +F 2 "" H 8000 1950 60 0000 C CNN +F 3 "" H 8000 1950 60 0000 C CNN + 1 8000 1950 + 1 0 0 -1 +$EndComp +Text GLabel 6200 2150 3 60 Input ~ 0 +out2 +Text GLabel 8000 2150 3 60 Input ~ 0 +out3 +$Comp +L INVCMOS X4 +U 1 1 5D627966 +P 9050 1850 +F 0 "X4" H 9050 1850 60 0000 C CNN +F 1 "INVCMOS" H 8600 2000 60 0000 C CNN +F 2 "" H 9050 1850 60 0001 C CNN +F 3 "" H 9050 1850 60 0001 C CNN + 1 9050 1850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5D627A26 +P 9950 1950 +F 0 "U5" H 9950 2450 60 0000 C CNN +F 1 "plot_v1" H 10150 2300 60 0000 C CNN +F 2 "" H 9950 1950 60 0000 C CNN +F 3 "" H 9950 1950 60 0000 C CNN + 1 9950 1950 + 1 0 0 -1 +$EndComp +$Comp +L INVCMOS X5 +U 1 1 5D628061 +P 8200 3100 +F 0 "X5" H 8200 3100 60 0000 C CNN +F 1 "INVCMOS" H 7750 3250 60 0000 C CNN +F 2 "" H 8200 3100 60 0001 C CNN +F 3 "" H 8200 3100 60 0001 C CNN + 1 8200 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5D628068 +P 9200 3200 +F 0 "U6" H 9200 3700 60 0000 C CNN +F 1 "plot_v1" H 9400 3550 60 0000 C CNN +F 2 "" H 9200 3200 60 0000 C CNN +F 3 "" H 9200 3200 60 0000 C CNN + 1 9200 3200 + 1 0 0 -1 +$EndComp +Text GLabel 9200 3400 3 60 Input ~ 0 +out5 +$Comp +L INVCMOS X6 +U 1 1 5D628071 +P 10250 3100 +F 0 "X6" H 10250 3100 60 0000 C CNN +F 1 "INVCMOS" H 9800 3250 60 0000 C CNN +F 2 "" H 10250 3100 60 0001 C CNN +F 3 "" H 10250 3100 60 0001 C CNN + 1 10250 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 5D628079 +P 11150 3200 +F 0 "U7" H 11150 3700 60 0000 C CNN +F 1 "plot_v1" H 11350 3550 60 0000 C CNN +F 2 "" H 11150 3200 60 0000 C CNN +F 3 "" H 11150 3200 60 0000 C CNN + 1 11150 3200 + 1 0 0 -1 +$EndComp +Text GLabel 11150 3400 3 60 Input ~ 0 +out6 +Text GLabel 9950 2100 3 60 Input ~ 0 +out4 +$Comp +L plot_v1 U8 +U 1 1 5D636DDC +P 14550 4000 +F 0 "U8" H 14550 4500 60 0000 C CNN +F 1 "plot_v1" H 14750 4350 60 0000 C CNN +F 2 "" H 14550 4000 60 0000 C CNN +F 3 "" H 14550 4000 60 0000 C CNN + 1 14550 4000 + 0 -1 -1 0 +$EndComp +Text GLabel 14750 4000 2 60 Input ~ 0 +out7 +$Comp +L adc_bridge_1 U9 +U 1 1 5D67A9F3 +P 12300 3150 +F 0 "U9" H 12300 3150 60 0000 C CNN +F 1 "adc_bridge_1" H 12300 3300 60 0000 C CNN +F 2 "" H 12300 3150 60 0000 C CNN +F 3 "" H 12300 3150 60 0000 C CNN + 1 12300 3150 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U10 +U 1 1 5D67AA64 +P 14400 3000 +F 0 "U10" H 14400 3000 60 0000 C CNN +F 1 "dac_bridge_1" H 14400 3150 60 0000 C CNN +F 2 "" H 14400 3000 60 0000 C CNN +F 3 "" H 14400 3000 60 0000 C CNN + 1 14400 3000 + 0 1 1 0 +$EndComp +Wire Wire Line + 3900 1850 4950 1850 +Connection ~ 2550 1850 +Connection ~ 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14150 2400 +Wire Wire Line + 14150 2400 14450 2400 +$Comp +L inverter U1 +U 1 1 5DDE38F5 +P 10500 5000 +F 0 "U1" H 13350 6800 60 0000 C CNN +F 1 "inverter" H 13350 7000 60 0000 C CNN +F 2 "" H 13350 6950 60 0000 C CNN +F 3 "" H 13350 6950 60 0000 C CNN + 1 10500 5000 + 1 0 0 -1 +$EndComp +$EndSCHEMATC |