Subject: Added eSim Examples

Description: Added eSim Examples

20 files changed, 1493 insertions, 0 deletions

diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier-cache.lib b/Examples/Inverting_Amplifier/Inverting_Amplifier-cache.lib
new file mode 100644
index 00000000..1d012df3
--- /dev/null
+++ b/Examples/Inverting_Amplifier/Inverting_Amplifier-cache.lib
@@ -0,0 +1,82 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 30 V V C CNN
+F3 "" 0 0 30 H V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 60 60 1 1 P
+X ~ 2 0 -150 50 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# UA741
+#
+DEF UA741 X 0 40 Y Y 1 F N
+F0 "X" 150 0 60 H V C CNN
+F1 "UA741" 250 -150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0  0 150  0 -150  350 0  0 150 N
+X + 1 -200 100 200 R 50 50 1 1 I
+X - 2 -200 -100 200 R 50 50 1 1 I
+X ~ 3 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.cir b/Examples/Inverting_Amplifier/Inverting_Amplifier.cir
new file mode 100644
index 00000000..736b20bc
--- /dev/null
+++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.cir
@@ -0,0 +1,14 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 22 15:31:09 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+X1  Net-_R2-Pad1_ In Out UA741		
+R2  Net-_R2-Pad1_ GND 1k		
+R3  GND Out 1k		
+R5  Out In 1k		
+v1  Net-_R1-Pad2_ GND sine		
+R1  In Net-_R1-Pad2_ 1k		
+
+.end
diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.cir.out b/Examples/Inverting_Amplifier/Inverting_Amplifier.cir.out
new file mode 100644
index 00000000..19176cc5
--- /dev/null
+++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.cir.out
@@ -0,0 +1,18 @@
+* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015
+
+.include ua741.sub
+x1 net-_r2-pad1_ in out ua741
+r2  net-_r2-pad1_ gnd 1k
+r3  gnd out 1k
+r5  out in 1k
+v1  net-_r1-pad2_ gnd sine(0 2 50 0 0)
+r1  in net-_r1-pad2_ 1k
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.pro b/Examples/Inverting_Amplifier/Inverting_Amplifier.pro
new file mode 100644
index 00000000..f6b5a5b9
--- /dev/null
+++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.pro
@@ -0,0 +1,69 @@
+update=Mon Jun 22 14:48:33 2015
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
+LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
+LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
+LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
+LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
+LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.proj b/Examples/Inverting_Amplifier/Inverting_Amplifier.proj
new file mode 100644
index 00000000..ea59291b
--- /dev/null
+++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.proj
@@ -0,0 +1 @@
+schematicFile Inverting_Amplifier.sch
diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier.sch b/Examples/Inverting_Amplifier/Inverting_Amplifier.sch
new file mode 100644
index 00000000..33941a0d
--- /dev/null
+++ b/Examples/Inverting_Amplifier/Inverting_Amplifier.sch
@@ -0,0 +1,209 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L UA741 X1
+U 1 1 558820F5
+P 5500 3400
+F 0 "X1" H 5650 3400 60  0000 C CNN
+F 1 "UA741" H 5750 3250 60  0000 C CNN
+F 2 "" H 5500 3400 60  0000 C CNN
+F 3 "" H 5500 3400 60  0000 C CNN
+	1    5500 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R2
+U 1 1 558821D4
+P 5050 3300
+F 0 "R2" V 5130 3300 50  0000 C CNN
+F 1 "1k" V 5050 3300 50  0000 C CNN
+F 2 "" V 4980 3300 30  0000 C CNN
+F 3 "" H 5050 3300 30  0000 C CNN
+	1    5050 3300
+	0    1    1    0   
+$EndComp
+$Comp
+L R R3
+U 1 1 558821F0
+P 6450 3400
+F 0 "R3" V 6530 3400 50  0000 C CNN
+F 1 "1k" V 6450 3400 50  0000 C CNN
+F 2 "" V 6380 3400 30  0000 C CNN
+F 3 "" H 6450 3400 30  0000 C CNN
+	1    6450 3400
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 5588243E
+P 3550 3950
+F 0 "#PWR01" H 3550 3950 30  0001 C CNN
+F 1 "GND" H 3550 3880 30  0001 C CNN
+F 2 "" H 3550 3950 60  0000 C CNN
+F 3 "" H 3550 3950 60  0000 C CNN
+	1    3550 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 558824A7
+P 6800 3450
+F 0 "#PWR02" H 6800 3450 30  0001 C CNN
+F 1 "GND" H 6800 3380 30  0001 C CNN
+F 2 "" H 6800 3450 60  0000 C CNN
+F 3 "" H 6800 3450 60  0000 C CNN
+	1    6800 3450
+	1    0    0    -1  
+$EndComp
+Text GLabel 6200 3250 0    60   Input ~ 0
+Out
+Text GLabel 5250 3650 0    60   Input ~ 0
+In
+$Comp
+L PWR_FLAG #FLG03
+U 1 1 55882796
+P 6750 3300
+F 0 "#FLG03" H 6750 3395 50  0001 C CNN
+F 1 "PWR_FLAG" H 6750 3480 50  0000 C CNN
+F 2 "" H 6750 3300 60  0000 C CNN
+F 3 "" H 6750 3300 60  0000 C CNN
+	1    6750 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L R R5
+U 1 1 558828E5
+P 5800 4050
+F 0 "R5" V 5880 4050 50  0000 C CNN
+F 1 "1k" V 5800 4050 50  0000 C CNN
+F 2 "" V 5730 4050 30  0000 C CNN
+F 3 "" H 5800 4050 30  0000 C CNN
+	1    5800 4050
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR04
+U 1 1 55882C4B
+P 4700 3300
+F 0 "#PWR04" H 4700 3300 30  0001 C CNN
+F 1 "GND" H 4700 3230 30  0001 C CNN
+F 2 "" H 4700 3300 60  0000 C CNN
+F 3 "" H 4700 3300 60  0000 C CNN
+	1    4700 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L sine v1
+U 1 1 55882CA5
+P 4100 3700
+F 0 "v1" H 3900 3800 60  0000 C CNN
+F 1 "sine" H 3900 3650 60  0000 C CNN
+F 2 "R1" H 3800 3700 60  0000 C CNN
+F 3 "" H 4100 3700 60  0000 C CNN
+	1    4100 3700
+	0    1    1    0   
+$EndComp
+$Comp
+L R R1
+U 1 1 55882CF2
+P 4850 3500
+F 0 "R1" V 4930 3500 50  0000 C CNN
+F 1 "1k" V 4850 3500 50  0000 C CNN
+F 2 "" V 4780 3500 30  0000 C CNN
+F 3 "" H 4850 3500 30  0000 C CNN
+	1    4850 3500
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	4550 3500 4550 3700
+Wire Wire Line
+	6050 3400 6300 3400
+Wire Wire Line
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+Wire Wire Line
+	3650 3700 3550 3700
+Wire Wire Line
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+Wire Wire Line
+	5250 3650 5250 3550
+Wire Wire Line
+	5250 3550 5200 3550
+Wire Wire Line
+	5200 3550 5200 3500
+Connection ~ 5200 3500
+Wire Wire Line
+	6200 3250 6200 3400
+Connection ~ 6200 3400
+Wire Wire Line
+	6750 3300 6750 3400
+Connection ~ 6750 3400
+Wire Wire Line
+	5950 4050 6100 4050
+Wire Wire Line
+	6100 4050 6100 3400
+Connection ~ 6100 3400
+Wire Wire Line
+	5100 4050 5650 4050
+Wire Wire Line
+	5100 3500 5100 4050
+Connection ~ 5100 3500
+Wire Wire Line
+	5200 3300 5300 3300
+Wire Wire Line
+	4900 3300 4700 3300
+Wire Wire Line
+	4700 3500 4550 3500
+Wire Wire Line
+	5000 3500 5300 3500
+$EndSCHEMATC
diff --git a/Examples/Inverting_Amplifier/Inverting_Amplifier_Previous_Values.xml b/Examples/Inverting_Amplifier/Inverting_Amplifier_Previous_Values.xml
new file mode 100644
index 00000000..a3159c27
--- /dev/null
+++ b/Examples/Inverting_Amplifier/Inverting_Amplifier_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">10</field1></v1><v2 name="Source type">dc<field1 name="Value">6</field1></v2><v1 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">2</field2><field3 name="Frequency">50</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor">0</field5></v1></source><model /><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/Inverting_Amplifier/analysis b/Examples/Inverting_Amplifier/analysis
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/Examples/Inverting_Amplifier/analysis
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/Examples/Inverting_Amplifier/plot_data_i.txt b/Examples/Inverting_Amplifier/plot_data_i.txt
new file mode 100644
index 00000000..d22ff735
--- /dev/null
+++ b/Examples/Inverting_Amplifier/plot_data_i.txt
@@ -0,0 +1,67 @@
+* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015
+Transient Analysis  Mon Jun 22 15:32:13  2015
+--------------------------------------------------------------------------------
+Index   time            e.x1.ein1#branc e.x1.eout1#bran v1#branch       
+--------------------------------------------------------------------------------
+0	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00	
+1	1.000000e-05	2.386032e-05	1.292478e-05	-6.40261e-06	
+2	2.000000e-05	2.298287e-05	2.547805e-05	-1.26814e-05	
+3	4.000000e-05	2.304574e-05	5.061101e-05	-2.52477e-05	
+4	8.000000e-05	2.297299e-05	1.008670e-04	-5.03757e-05	
+5	1.600000e-04	2.302203e-05	2.013264e-04	-1.00605e-04	
+6	3.200000e-04	2.287019e-05	4.017971e-04	-2.00840e-04	
+7	6.400000e-04	2.261624e-05	7.991932e-04	-3.99538e-04	
+8	1.280000e-03	2.125925e-05	1.565841e-03	-7.82863e-04	
+9	2.560000e-03	1.638914e-05	2.881532e-03	-1.44072e-03	
+10	4.560000e-03	3.396704e-06	3.961965e-03	-1.98096e-03	
+11	6.560000e-03	-1.13261e-05	3.529056e-03	-1.76455e-03	
+12	8.560000e-03	-2.12895e-05	1.748174e-03	-8.74135e-04	
+13	1.056000e-02	-2.35546e-05	-7.00458e-04	3.501680e-04	
+14	1.256000e-02	-1.63887e-05	-2.88153e-03	1.440717e-03	
+15	1.456000e-02	-3.39713e-06	-3.96197e-03	1.980963e-03	
+16	1.656000e-02	1.132653e-05	-3.52906e-03	1.764546e-03	
+17	1.856000e-02	2.128905e-05	-1.74817e-03	8.741351e-04	
+18	2.056000e-02	2.355498e-05	7.004579e-04	-3.50168e-04	
+19	2.256000e-02	1.638829e-05	2.881532e-03	-1.44072e-03	
+20	2.456000e-02	3.397556e-06	3.961965e-03	-1.98096e-03	
+21	2.656000e-02	-1.13270e-05	3.529056e-03	-1.76455e-03	
+22	2.856000e-02	-2.12886e-05	1.748174e-03	-8.74135e-04	
+23	3.056000e-02	-2.35554e-05	-7.00458e-04	3.501680e-04	
+24	3.256000e-02	-1.63879e-05	-2.88153e-03	1.440717e-03	
+25	3.456000e-02	-3.39798e-06	-3.96197e-03	1.980963e-03	
+26	3.656000e-02	1.132739e-05	-3.52906e-03	1.764546e-03	
+27	3.856000e-02	2.128820e-05	-1.74817e-03	8.741351e-04	
+28	4.056000e-02	2.355584e-05	7.004580e-04	-3.50168e-04	
+29	4.256000e-02	1.638744e-05	2.881532e-03	-1.44072e-03	
+30	4.456000e-02	3.398413e-06	3.961965e-03	-1.98096e-03	
+31	4.656000e-02	-1.13278e-05	3.529056e-03	-1.76455e-03	
+32	4.856000e-02	-2.12878e-05	1.748174e-03	-8.74135e-04	
+33	5.056000e-02	-2.35563e-05	-7.00458e-04	3.501680e-04	
+34	5.256000e-02	-1.63870e-05	-2.88153e-03	1.440717e-03	
+35	5.456000e-02	-3.39884e-06	-3.96197e-03	1.980963e-03	
+36	5.656000e-02	1.132825e-05	-3.52906e-03	1.764546e-03	
+37	5.856000e-02	2.128733e-05	-1.74817e-03	8.741351e-04	
+38	6.056000e-02	2.355670e-05	7.004580e-04	-3.50168e-04	
+39	6.256000e-02	1.638657e-05	2.881532e-03	-1.44072e-03	
+40	6.456000e-02	3.399277e-06	3.961965e-03	-1.98096e-03	
+41	6.656000e-02	-1.13287e-05	3.529056e-03	-1.76455e-03	
+42	6.856000e-02	-2.12869e-05	1.748174e-03	-8.74135e-04	
+43	7.056000e-02	-2.35571e-05	-7.00458e-04	3.501680e-04	
+44	7.256000e-02	-1.63861e-05	-2.88153e-03	1.440717e-03	
+45	7.456000e-02	-3.39971e-06	-3.96197e-03	1.980963e-03	
+46	7.656000e-02	1.132912e-05	-3.52906e-03	1.764546e-03	
+47	7.856000e-02	2.128647e-05	-1.74817e-03	8.741351e-04	
+48	8.056000e-02	2.355757e-05	7.004580e-04	-3.50168e-04	
+49	8.256000e-02	1.638570e-05	2.881532e-03	-1.44072e-03	
+50	8.456000e-02	3.400147e-06	3.961965e-03	-1.98096e-03	
+51	8.656000e-02	-1.13296e-05	3.529056e-03	-1.76455e-03	
+52	8.856000e-02	-2.12860e-05	1.748174e-03	-8.74135e-04	
+53	9.056000e-02	-2.35580e-05	-7.00458e-04	3.501680e-04	
+54	9.256000e-02	-1.63853e-05	-2.88153e-03	1.440717e-03	
+
+Index   time            e.x1.ein1#branc e.x1.eout1#bran v1#branch       
+--------------------------------------------------------------------------------
+55	9.456000e-02	-3.40058e-06	-3.96197e-03	1.980963e-03	
+56	9.656000e-02	1.132999e-05	-3.52906e-03	1.764546e-03	
+57	9.856000e-02	2.128559e-05	-1.74817e-03	8.741351e-04	
+58	1.000000e-01	2.318983e-05	3.481451e-07	-1.16010e-07	
diff --git a/Examples/Inverting_Amplifier/plot_data_v.txt b/Examples/Inverting_Amplifier/plot_data_v.txt
new file mode 100644
index 00000000..968de4c5
--- /dev/null
+++ b/Examples/Inverting_Amplifier/plot_data_v.txt
@@ -0,0 +1,203 @@
+* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015
+Transient Analysis  Mon Jun 22 15:32:13  2015
+--------------------------------------------------------------------------------
+Index   time            in              net-_r1-pad2_   net-_r2-pad1_   
+--------------------------------------------------------------------------------
+0	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00	
+1	1.000000e-05	-1.19436e-04	6.283175e-03	-5.96883e-08	
+2	2.000000e-05	-1.15119e-04	1.256629e-02	-5.75307e-08	
+3	4.000000e-05	-1.15578e-04	2.513208e-02	-5.77601e-08	
+4	8.000000e-05	-1.15503e-04	5.026019e-02	-5.77228e-08	
+5	1.600000e-04	-1.16326e-04	1.004886e-01	-5.81342e-08	
+6	3.200000e-04	-1.16720e-04	2.007234e-01	-5.83309e-08	
+7	6.400000e-04	-1.17736e-04	3.994200e-01	-5.88386e-08	
+8	1.280000e-03	-1.15358e-04	7.827473e-01	-5.76502e-08	
+9	2.560000e-03	-9.85643e-05	1.440618e+00	-4.92575e-08	
+10	4.560000e-03	-3.97849e-05	1.980923e+00	-1.98825e-08	
+11	6.560000e-03	3.635683e-05	1.764582e+00	1.816933e-08	
+12	8.560000e-03	9.644407e-05	8.742315e-01	4.819794e-08	
+13	1.056000e-02	1.218619e-04	-3.50046e-01	6.090050e-08	
+14	1.256000e-02	9.856215e-05	-1.44062e+00	4.925645e-08	
+15	1.456000e-02	3.978703e-05	-1.98092e+00	1.988357e-08	
+16	1.656000e-02	-3.63590e-05	-1.76458e+00	-1.81704e-08	
+17	1.856000e-02	-9.64419e-05	-8.74232e-01	-4.81969e-08	
+18	2.056000e-02	-1.21864e-04	3.500461e-01	-6.09016e-08	
+19	2.256000e-02	-9.85600e-05	1.440618e+00	-4.92554e-08	
+20	2.456000e-02	-3.97892e-05	1.980923e+00	-1.98846e-08	
+21	2.656000e-02	3.636109e-05	1.764582e+00	1.817146e-08	
+22	2.856000e-02	9.643981e-05	8.742315e-01	4.819581e-08	
+23	3.056000e-02	1.218662e-04	-3.50046e-01	6.090264e-08	
+24	3.256000e-02	9.855788e-05	-1.44062e+00	4.925431e-08	
+25	3.456000e-02	3.979130e-05	-1.98092e+00	1.988571e-08	
+26	3.656000e-02	-3.63632e-05	-1.76458e+00	-1.81725e-08	
+27	3.856000e-02	-9.64377e-05	-8.74232e-01	-4.81947e-08	
+28	4.056000e-02	-1.21868e-04	3.500461e-01	-6.09037e-08	
+29	4.256000e-02	-9.85557e-05	1.440618e+00	-4.92532e-08	
+30	4.456000e-02	-3.97935e-05	1.980923e+00	-1.98868e-08	
+31	4.656000e-02	3.636538e-05	1.764582e+00	1.817360e-08	
+32	4.856000e-02	9.643551e-05	8.742315e-01	4.819366e-08	
+33	5.056000e-02	1.218705e-04	-3.50046e-01	6.090479e-08	
+34	5.256000e-02	9.855358e-05	-1.44062e+00	4.925216e-08	
+35	5.456000e-02	3.979561e-05	-1.98092e+00	1.988786e-08	
+36	5.656000e-02	-3.63675e-05	-1.76458e+00	-1.81747e-08	
+37	5.856000e-02	-9.64334e-05	-8.74232e-01	-4.81926e-08	
+38	6.056000e-02	-1.21873e-04	3.500461e-01	-6.09059e-08	
+39	6.256000e-02	-9.85514e-05	1.440618e+00	-4.92511e-08	
+40	6.456000e-02	-3.97978e-05	1.980923e+00	-1.98889e-08	
+41	6.656000e-02	3.636971e-05	1.764582e+00	1.817577e-08	
+42	6.856000e-02	9.643118e-05	8.742315e-01	4.819150e-08	
+43	7.056000e-02	1.218748e-04	-3.50046e-01	6.090695e-08	
+44	7.256000e-02	9.854924e-05	-1.44062e+00	4.925000e-08	
+45	7.456000e-02	3.979995e-05	-1.98092e+00	1.989003e-08	
+46	7.656000e-02	-3.63719e-05	-1.76458e+00	-1.81769e-08	
+47	7.856000e-02	-9.64290e-05	-8.74232e-01	-4.81904e-08	
+48	8.056000e-02	-1.21877e-04	3.500461e-01	-6.09080e-08	
+49	8.256000e-02	-9.85471e-05	1.440618e+00	-4.92489e-08	
+50	8.456000e-02	-3.98021e-05	1.980923e+00	-1.98911e-08	
+51	8.656000e-02	3.637406e-05	1.764582e+00	1.817794e-08	
+52	8.856000e-02	9.642682e-05	8.742315e-01	4.818932e-08	
+53	9.056000e-02	1.218792e-04	-3.50046e-01	6.090913e-08	
+54	9.256000e-02	9.854488e-05	-1.44062e+00	4.924782e-08	
+
+Index   time            in              net-_r1-pad2_   net-_r2-pad1_   
+--------------------------------------------------------------------------------
+55	9.456000e-02	3.980431e-05	-1.98092e+00	1.989221e-08	
+56	9.656000e-02	-3.63763e-05	-1.76458e+00	-1.81790e-08	
+57	9.856000e-02	-9.64246e-05	-8.74232e-01	-4.81882e-08	
+58	1.000000e-01	-1.16010e-04	-2.44929e-15	-5.79759e-08	
+
+* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015
+Transient Analysis  Mon Jun 22 15:32:13  2015
+--------------------------------------------------------------------------------
+Index   time            out             x1.1            x1.2            
+--------------------------------------------------------------------------------
+0	0.000000e+00	0.000000e+00	0.000000e+00	0.000000e+00	
+1	1.000000e-05	-6.52211e-03	-7.49147e-03	-7.49147e-03	
+2	2.000000e-05	-1.27966e-02	-1.47074e-02	-1.47074e-02	
+3	4.000000e-05	-2.53633e-02	-2.91591e-02	-2.91591e-02	
+4	8.000000e-05	-5.04913e-02	-5.80563e-02	-5.80563e-02	
+5	1.600000e-04	-1.00721e-01	-1.15821e-01	-1.15821e-01	
+6	3.200000e-04	-2.00957e-01	-2.31092e-01	-2.31092e-01	
+7	6.400000e-04	-3.99655e-01	-4.59595e-01	-4.59595e-01	
+8	1.280000e-03	-7.82978e-01	-9.00416e-01	-9.00416e-01	
+9	2.560000e-03	-1.44082e+00	-1.65693e+00	-1.65693e+00	
+10	4.560000e-03	-1.98100e+00	-2.27815e+00	-2.27815e+00	
+11	6.560000e-03	-1.76451e+00	-2.02919e+00	-2.02919e+00	
+12	8.560000e-03	-8.74039e-01	-1.00515e+00	-1.00515e+00	
+13	1.056000e-02	3.502899e-01	4.028242e-01	4.028242e-01	
+14	1.256000e-02	1.440815e+00	1.656930e+00	1.656930e+00	
+15	1.456000e-02	1.981002e+00	2.278150e+00	2.278150e+00	
+16	1.656000e-02	1.764510e+00	2.029189e+00	2.029189e+00	
+17	1.856000e-02	8.740386e-01	1.005152e+00	1.005152e+00	
+18	2.056000e-02	-3.50290e-01	-4.02824e-01	-4.02824e-01	
+19	2.256000e-02	-1.44082e+00	-1.65693e+00	-1.65693e+00	
+20	2.456000e-02	-1.98100e+00	-2.27815e+00	-2.27815e+00	
+21	2.656000e-02	-1.76451e+00	-2.02919e+00	-2.02919e+00	
+22	2.856000e-02	-8.74039e-01	-1.00515e+00	-1.00515e+00	
+23	3.056000e-02	3.502899e-01	4.028243e-01	4.028243e-01	
+24	3.256000e-02	1.440815e+00	1.656930e+00	1.656930e+00	
+25	3.456000e-02	1.981002e+00	2.278150e+00	2.278150e+00	
+26	3.656000e-02	1.764510e+00	2.029189e+00	2.029189e+00	
+27	3.856000e-02	8.740386e-01	1.005152e+00	1.005152e+00	
+28	4.056000e-02	-3.50290e-01	-4.02824e-01	-4.02824e-01	
+29	4.256000e-02	-1.44082e+00	-1.65693e+00	-1.65693e+00	
+30	4.456000e-02	-1.98100e+00	-2.27815e+00	-2.27815e+00	
+31	4.656000e-02	-1.76451e+00	-2.02919e+00	-2.02919e+00	
+32	4.856000e-02	-8.74039e-01	-1.00515e+00	-1.00515e+00	
+33	5.056000e-02	3.502899e-01	4.028243e-01	4.028243e-01	
+34	5.256000e-02	1.440815e+00	1.656930e+00	1.656930e+00	
+35	5.456000e-02	1.981002e+00	2.278150e+00	2.278150e+00	
+36	5.656000e-02	1.764510e+00	2.029189e+00	2.029189e+00	
+37	5.856000e-02	8.740386e-01	1.005152e+00	1.005152e+00	
+38	6.056000e-02	-3.50290e-01	-4.02824e-01	-4.02824e-01	
+39	6.256000e-02	-1.44082e+00	-1.65693e+00	-1.65693e+00	
+40	6.456000e-02	-1.98100e+00	-2.27815e+00	-2.27815e+00	
+41	6.656000e-02	-1.76451e+00	-2.02919e+00	-2.02919e+00	
+42	6.856000e-02	-8.74039e-01	-1.00515e+00	-1.00515e+00	
+43	7.056000e-02	3.502899e-01	4.028243e-01	4.028243e-01	
+44	7.256000e-02	1.440815e+00	1.656930e+00	1.656930e+00	
+45	7.456000e-02	1.981002e+00	2.278150e+00	2.278150e+00	
+46	7.656000e-02	1.764510e+00	2.029189e+00	2.029189e+00	
+47	7.856000e-02	8.740386e-01	1.005152e+00	1.005152e+00	
+48	8.056000e-02	-3.50290e-01	-4.02824e-01	-4.02824e-01	
+49	8.256000e-02	-1.44082e+00	-1.65693e+00	-1.65693e+00	
+50	8.456000e-02	-1.98100e+00	-2.27815e+00	-2.27815e+00	
+51	8.656000e-02	-1.76451e+00	-2.02919e+00	-2.02919e+00	
+52	8.856000e-02	-8.74039e-01	-1.00515e+00	-1.00515e+00	
+53	9.056000e-02	3.502899e-01	4.028243e-01	4.028243e-01	
+54	9.256000e-02	1.440815e+00	1.656930e+00	1.656930e+00	
+
+Index   time            out             x1.1            x1.2            
+--------------------------------------------------------------------------------
+55	9.456000e-02	1.981002e+00	2.278150e+00	2.278150e+00	
+56	9.656000e-02	1.764510e+00	2.029189e+00	2.029189e+00	
+57	9.856000e-02	8.740386e-01	1.005152e+00	1.005152e+00	
+58	1.000000e-01	-2.32077e-04	-2.58188e-04	-2.58188e-04	
+
+* eeschema netlist version 1.1 (spice format) creation date: mon jun 22 15:31:09 2015
+Transient Analysis  Mon Jun 22 15:32:13  2015
+--------------------------------------------------------------------------------
+Index   time            x1.4            
+--------------------------------------------------------------------------------
+0	0.000000e+00	0.000000e+00	
+1	1.000000e-05	-1.19377e+01	
+2	2.000000e-05	-1.15061e+01	
+3	4.000000e-05	-1.15520e+01	
+4	8.000000e-05	-1.15446e+01	
+5	1.600000e-04	-1.16268e+01	
+6	3.200000e-04	-1.16662e+01	
+7	6.400000e-04	-1.17677e+01	
+8	1.280000e-03	-1.15300e+01	
+9	2.560000e-03	-9.85150e+00	
+10	4.560000e-03	-3.97650e+00	
+11	6.560000e-03	3.633866e+00	
+12	8.560000e-03	9.639588e+00	
+13	1.056000e-02	1.218010e+01	
+14	1.256000e-02	9.851290e+00	
+15	1.456000e-02	3.976714e+00	
+16	1.656000e-02	-3.63408e+00	
+17	1.856000e-02	-9.63937e+00	
+18	2.056000e-02	-1.21803e+01	
+19	2.256000e-02	-9.85108e+00	
+20	2.456000e-02	-3.97693e+00	
+21	2.656000e-02	3.634292e+00	
+22	2.856000e-02	9.639161e+00	
+23	3.056000e-02	1.218053e+01	
+24	3.256000e-02	9.850863e+00	
+25	3.456000e-02	3.977142e+00	
+26	3.656000e-02	-3.63451e+00	
+27	3.856000e-02	-9.63895e+00	
+28	4.056000e-02	-1.21807e+01	
+29	4.256000e-02	-9.85065e+00	
+30	4.456000e-02	-3.97736e+00	
+31	4.656000e-02	3.634721e+00	
+32	4.856000e-02	9.638732e+00	
+33	5.056000e-02	1.218096e+01	
+34	5.256000e-02	9.850432e+00	
+35	5.456000e-02	3.977572e+00	
+36	5.656000e-02	-3.63494e+00	
+37	5.856000e-02	-9.63852e+00	
+38	6.056000e-02	-1.21812e+01	
+39	6.256000e-02	-9.85022e+00	
+40	6.456000e-02	-3.97779e+00	
+41	6.656000e-02	3.635153e+00	
+42	6.856000e-02	9.638299e+00	
+43	7.056000e-02	1.218139e+01	
+44	7.256000e-02	9.849999e+00	
+45	7.456000e-02	3.978006e+00	
+46	7.656000e-02	-3.63537e+00	
+47	7.856000e-02	-9.63808e+00	
+48	8.056000e-02	-1.21816e+01	
+49	8.256000e-02	-9.84978e+00	
+50	8.456000e-02	-3.97822e+00	
+51	8.656000e-02	3.635589e+00	
+52	8.856000e-02	9.637864e+00	
+53	9.056000e-02	1.218183e+01	
+54	9.256000e-02	9.849563e+00	
+
+Index   time            x1.4            
+--------------------------------------------------------------------------------
+55	9.456000e-02	3.978442e+00	
+56	9.656000e-02	-3.63581e+00	
+57	9.856000e-02	-9.63764e+00	
+58	1.000000e-01	-1.15952e+01	
diff --git a/Examples/Inverting_Amplifier/ua741-cache.bak b/Examples/Inverting_Amplifier/ua741-cache.bak
new file mode 100644
index 00000000..eaad34ad
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741-cache.bak
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3  Date: Sunday 21 October 2012 01:22:10 AM IST
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 50 100 50 H V L CNN
+F1 "C" 50 -100 50 H V L CNN
+$FPLIST
+ SM*
+ C?
+ C1-1
+$ENDFPLIST
+DRAW
+P 2 0 1 10  -100 -30  100 -30 N
+P 2 0 1 10  -100 30  100 30 N
+X ~ 1 0 200 170 D 40 40 1 1 P
+X ~ 2 0 -200 170 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 0 -50 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 I
+X ~ 2 250 0 100 L 30 30 2 1 I
+X ~ 3 250 0 100 L 30 30 3 1 I
+X ~ 4 250 0 100 L 30 30 4 1 I
+X ~ 5 250 0 100 L 30 30 5 1 I
+X ~ 6 250 0 100 L 30 30 6 1 I
+X ~ 7 250 0 100 L 30 30 7 1 I
+X ~ 8 250 0 100 L 30 30 8 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 270 30 H I C CNN
+F1 "PWR_FLAG" 0 230 30 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 3 0 1 0  0 0  0 100  0 100 N
+P 5 0 1 0  0 100  -100 150  0 200  100 150  0 100 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+$FPLIST
+ R?
+ SM0603
+ SM0805
+ R?-*
+$ENDFPLIST
+DRAW
+S -40 150 40 -150 0 1 12 N
+X ~ 1 0 250 100 D 60 60 1 1 P
+X ~ 2 0 -250 100 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCVS
+#
+DEF VCVS E 0 40 Y Y 1 F N
+F0 "E" -200 100 50 H V C CNN
+F1 "VCVS" -200 -50 50 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Inverting_Amplifier/ua741-cache.lib b/Examples/Inverting_Amplifier/ua741-cache.lib
new file mode 100644
index 00000000..117989ce
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741-cache.lib
@@ -0,0 +1,111 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# C
+#
+DEF C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C?
+ C_????_*
+ C_????
+ SMD*_c
+ Capacitor*
+$ENDFPLIST
+DRAW
+P 2 0 1 20  -80 -30  80 -30 N
+P 2 0 1 20  -80 30  80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF ~GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0  -50 0  0 -50  50 0  -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 0 -50 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "R" 0 0 50 V V C CNN
+F2 "" -70 0 30 V V C CNN
+F3 "" 0 0 30 H V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 60 60 1 1 P
+X ~ 2 0 -150 50 U 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# VCVS
+#
+DEF VCVS E 0 40 Y Y 1 F N
+F0 "E" -200 100 50 H V C CNN
+F1 "VCVS" -200 -50 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+S -100 100 100 -100 0 1 0 N
+X + 1 -300 50 200 R 35 35 1 1 P
+X - 2 300 50 200 L 35 35 1 1 P
+X +c 3 -50 -200 100 U 35 35 1 1 P
+X -c 4 50 -200 100 U 35 35 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Inverting_Amplifier/ua741.bak b/Examples/Inverting_Amplifier/ua741.bak
new file mode 100644
index 00000000..4e9a8119
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741.bak
@@ -0,0 +1,245 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:analogXSpice
+LIBS:ua741-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "19 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Text Notes 3800 2400 0    60   ~ 0
+Op-Amp
+Text Notes 3750 2850 0    60   ~ 0
+VCCS
+Text Notes 5800 2500 0    60   ~ 0
+out
+Text Notes 2750 3100 0    60   ~ 0
+-
+Text Notes 2700 2600 0    60   ~ 0
++
+$Comp
+L PORT U1
+U 6 1 5082C027
+P 6250 2500
+F 0 "U1" H 6250 2450 30  0000 C CNN
+F 1 "PORT" H 6250 2500 30  0000 C CNN
+F 2 "" H 6250 2500 60  0001 C CNN
+F 3 "" H 6250 2500 60  0001 C CNN
+	6    6250 2500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5082C011
+P 2300 3100
+F 0 "U1" H 2300 3050 30  0000 C CNN
+F 1 "PORT" H 2300 3100 30  0000 C CNN
+F 2 "" H 2300 3100 60  0001 C CNN
+F 3 "" H 2300 3100 60  0001 C CNN
+	2    2300 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5082C00B
+P 2250 2600
+F 0 "U1" H 2250 2550 30  0000 C CNN
+F 1 "PORT" H 2250 2600 30  0000 C CNN
+F 2 "" H 2250 2600 60  0001 C CNN
+F 3 "" H 2250 2600 60  0001 C CNN
+	3    2250 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 508152A0
+P 3450 3200
+F 0 "#FLG01" H 3450 3470 30  0001 C CNN
+F 1 "PWR_FLAG" H 3450 3430 30  0000 C CNN
+F 2 "" H 3450 3200 60  0001 C CNN
+F 3 "" H 3450 3200 60  0001 C CNN
+	1    3450 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L R Rout1
+U 1 1 50813F5B
+P 5600 2500
+F 0 "Rout1" V 5680 2500 50  0000 C CNN
+F 1 "75" V 5600 2500 50  0000 C CNN
+F 2 "" H 5600 2500 60  0001 C CNN
+F 3 "" H 5600 2500 60  0001 C CNN
+	1    5600 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L VCVS Eout1
+U 1 1 50813F0F
+P 5200 2900
+F 0 "Eout1" H 5000 3000 50  0000 C CNN
+F 1 "1" H 5000 2850 50  0000 C CNN
+F 2 "" H 5200 2900 60  0001 C CNN
+F 3 "" H 5200 2900 60  0001 C CNN
+	1    5200 2900
+	0    1    1    0   
+$EndComp
+$Comp
+L C Cbw1
+U 1 1 50813EE0
+P 4550 2900
+F 0 "Cbw1" H 4600 3000 50  0000 L CNN
+F 1 "31.85e-9" H 4600 2800 50  0000 L CNN
+F 2 "" H 4550 2900 60  0001 C CNN
+F 3 "" H 4550 2900 60  0001 C CNN
+	1    4550 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L R Rbw1
+U 1 1 50813EAB
+P 4150 2500
+F 0 "Rbw1" V 4230 2500 50  0000 C CNN
+F 1 "0.5e6" V 4150 2500 50  0000 C CNN
+F 2 "" H 4150 2500 60  0001 C CNN
+F 3 "" H 4150 2500 60  0001 C CNN
+	1    4150 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 50813E0D
+P 3700 3400
+F 0 "#PWR02" H 3700 3400 30  0001 C CNN
+F 1 "GND" H 3700 3330 30  0001 C CNN
+F 2 "" H 3700 3400 60  0001 C CNN
+F 3 "" H 3700 3400 60  0001 C CNN
+	1    3700 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L VCVS Ein1
+U 1 1 50813D7C
+P 3650 2850
+F 0 "Ein1" H 3450 2950 50  0000 C CNN
+F 1 "100e3" H 3450 2800 50  0000 C CNN
+F 2 "" H 3650 2850 60  0001 C CNN
+F 3 "" H 3650 2850 60  0001 C CNN
+	1    3650 2850
+	0    1    1    0   
+$EndComp
+$Comp
+L R Rin1
+U 1 1 50813C57
+P 3000 2850
+F 0 "Rin1" V 3080 2850 50  0000 C CNN
+F 1 "2e6" V 3000 2850 50  0000 C CNN
+F 2 "" H 3000 2850 60  0001 C CNN
+F 3 "" H 3000 2850 60  0001 C CNN
+	1    3000 2850
+	1    0    0    -1  
+$EndComp
+Connection ~ 3700 3200
+Wire Wire Line
+	3450 3200 3700 3200
+Connection ~ 5000 3300
+Wire Wire Line
+	3700 3300 5250 3300
+Wire Wire Line
+	5250 3300 5250 3200
+Connection ~ 4550 3300
+Wire Wire Line
+	5000 3300 5000 2950
+Connection ~ 3700 3300
+Wire Wire Line
+	4550 3050 4550 3300
+Wire Wire Line
+	3700 2500 4000 2500
+Wire Wire Line
+	3700 2500 3700 2550
+Wire Wire Line
+	3450 2900 3300 2900
+Wire Wire Line
+	3300 2900 3300 3200
+Wire Wire Line
+	3300 3200 2950 3200
+Connection ~ 2950 3100
+Wire Wire Line
+	2950 3200 2950 3100
+Wire Wire Line
+	3000 2600 2500 2600
+Wire Wire Line
+	2550 3100 3000 3100
+Wire Wire Line
+	2950 2600 2950 2500
+Connection ~ 2950 2600
+Wire Wire Line
+	2950 2500 3300 2500
+Wire Wire Line
+	3300 2500 3300 2800
+Wire Wire Line
+	3300 2800 3450 2800
+Wire Wire Line
+	3700 3150 3700 3400
+Wire Wire Line
+	4550 2500 4550 2750
+Wire Wire Line
+	4300 2500 5000 2500
+Wire Wire Line
+	5000 2500 5000 2850
+Connection ~ 4550 2500
+Wire Wire Line
+	5250 2600 5250 2500
+Wire Wire Line
+	5250 2500 5450 2500
+Wire Wire Line
+	5750 2500 6000 2500
+Wire Wire Line
+	3000 3100 3000 3000
+Wire Wire Line
+	3000 2700 3000 2600
+$EndSCHEMATC
diff --git a/Examples/Inverting_Amplifier/ua741.cir b/Examples/Inverting_Amplifier/ua741.cir
new file mode 100644
index 00000000..de797429
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741.cir
@@ -0,0 +1,15 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Monday 17 December 2012 11:16:58 AM IST
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U1  6 7 3 PORT		
+Rout1  3 2 75		
+Eout1  2 0 1 0 1		
+Cbw1  1 0 31.85e-9		
+Rbw1  1 4 0.5e6		
+Ein1  4 0 7 6 100e3		
+Rin1  7 6 2e6		
+
+.end
diff --git a/Examples/Inverting_Amplifier/ua741.cir.ckt b/Examples/Inverting_Amplifier/ua741.cir.ckt
new file mode 100644
index 00000000..3661a9a2
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741.cir.ckt
@@ -0,0 +1,9 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
+
+u1  6 7 3 port
+rout1  3 2 75
+eout1  2 0 1 0 1
+cbw1  1 0 31.85e-9
+rbw1  1 4 0.5e6
+ein1  4 0 7 6 100e3
+rin1  7 6 2e6
diff --git a/Examples/Inverting_Amplifier/ua741.cir.out b/Examples/Inverting_Amplifier/ua741.cir.out
new file mode 100644
index 00000000..72e68514
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741.cir.out
@@ -0,0 +1,18 @@
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
+
+* u1  6 7 3 port
+rout1  3 2 75
+eout1  2 0 1 0 1
+cbw1  1 0 31.85e-9
+rbw1  1 4 0.5e6
+ein1  4 0 7 6 100e3
+rin1  7 6 2e6
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Inverting_Amplifier/ua741.pro b/Examples/Inverting_Amplifier/ua741.pro
new file mode 100644
index 00000000..5dbb81a5
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741.pro
@@ -0,0 +1,72 @@
+update=Monday 17 December 2012 06:14:06 PM IST
+last_client=eeschema
+[eeschema]
+version=1
+LibDir=/home/yogesh/FreeEDA/library
+NetFmt=1
+HPGLSpd=20
+HPGLDm=15
+HPGLNum=1
+offX_A4=0
+offY_A4=0
+offX_A3=0
+offY_A3=0
+offX_A2=0
+offY_A2=0
+offX_A1=0
+offY_A1=0
+offX_A0=0
+offY_A0=0
+offX_A=0
+offY_A=0
+offX_B=0
+offY_B=0
+offX_C=0
+offY_C=0
+offX_D=0
+offY_D=0
+offX_E=0
+offY_E=0
+RptD_X=0
+RptD_Y=100
+RptLab=1
+LabSize=60
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=analogSpice
+LibName32=converterSpice
+LibName33=digitalSpice
+LibName34=linearSpice
+LibName35=measurementSpice
+LibName36=portSpice
+LibName37=sourcesSpice
+LibName38=analogXSpice
diff --git a/Examples/Inverting_Amplifier/ua741.sch b/Examples/Inverting_Amplifier/ua741.sch
new file mode 100644
index 00000000..4e9a8119
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741.sch
@@ -0,0 +1,245 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:analogXSpice
+LIBS:ua741-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "19 dec 2012"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Text Notes 3800 2400 0    60   ~ 0
+Op-Amp
+Text Notes 3750 2850 0    60   ~ 0
+VCCS
+Text Notes 5800 2500 0    60   ~ 0
+out
+Text Notes 2750 3100 0    60   ~ 0
+-
+Text Notes 2700 2600 0    60   ~ 0
++
+$Comp
+L PORT U1
+U 6 1 5082C027
+P 6250 2500
+F 0 "U1" H 6250 2450 30  0000 C CNN
+F 1 "PORT" H 6250 2500 30  0000 C CNN
+F 2 "" H 6250 2500 60  0001 C CNN
+F 3 "" H 6250 2500 60  0001 C CNN
+	6    6250 2500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5082C011
+P 2300 3100
+F 0 "U1" H 2300 3050 30  0000 C CNN
+F 1 "PORT" H 2300 3100 30  0000 C CNN
+F 2 "" H 2300 3100 60  0001 C CNN
+F 3 "" H 2300 3100 60  0001 C CNN
+	2    2300 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5082C00B
+P 2250 2600
+F 0 "U1" H 2250 2550 30  0000 C CNN
+F 1 "PORT" H 2250 2600 30  0000 C CNN
+F 2 "" H 2250 2600 60  0001 C CNN
+F 3 "" H 2250 2600 60  0001 C CNN
+	3    2250 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 508152A0
+P 3450 3200
+F 0 "#FLG01" H 3450 3470 30  0001 C CNN
+F 1 "PWR_FLAG" H 3450 3430 30  0000 C CNN
+F 2 "" H 3450 3200 60  0001 C CNN
+F 3 "" H 3450 3200 60  0001 C CNN
+	1    3450 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L R Rout1
+U 1 1 50813F5B
+P 5600 2500
+F 0 "Rout1" V 5680 2500 50  0000 C CNN
+F 1 "75" V 5600 2500 50  0000 C CNN
+F 2 "" H 5600 2500 60  0001 C CNN
+F 3 "" H 5600 2500 60  0001 C CNN
+	1    5600 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L VCVS Eout1
+U 1 1 50813F0F
+P 5200 2900
+F 0 "Eout1" H 5000 3000 50  0000 C CNN
+F 1 "1" H 5000 2850 50  0000 C CNN
+F 2 "" H 5200 2900 60  0001 C CNN
+F 3 "" H 5200 2900 60  0001 C CNN
+	1    5200 2900
+	0    1    1    0   
+$EndComp
+$Comp
+L C Cbw1
+U 1 1 50813EE0
+P 4550 2900
+F 0 "Cbw1" H 4600 3000 50  0000 L CNN
+F 1 "31.85e-9" H 4600 2800 50  0000 L CNN
+F 2 "" H 4550 2900 60  0001 C CNN
+F 3 "" H 4550 2900 60  0001 C CNN
+	1    4550 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L R Rbw1
+U 1 1 50813EAB
+P 4150 2500
+F 0 "Rbw1" V 4230 2500 50  0000 C CNN
+F 1 "0.5e6" V 4150 2500 50  0000 C CNN
+F 2 "" H 4150 2500 60  0001 C CNN
+F 3 "" H 4150 2500 60  0001 C CNN
+	1    4150 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 50813E0D
+P 3700 3400
+F 0 "#PWR02" H 3700 3400 30  0001 C CNN
+F 1 "GND" H 3700 3330 30  0001 C CNN
+F 2 "" H 3700 3400 60  0001 C CNN
+F 3 "" H 3700 3400 60  0001 C CNN
+	1    3700 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L VCVS Ein1
+U 1 1 50813D7C
+P 3650 2850
+F 0 "Ein1" H 3450 2950 50  0000 C CNN
+F 1 "100e3" H 3450 2800 50  0000 C CNN
+F 2 "" H 3650 2850 60  0001 C CNN
+F 3 "" H 3650 2850 60  0001 C CNN
+	1    3650 2850
+	0    1    1    0   
+$EndComp
+$Comp
+L R Rin1
+U 1 1 50813C57
+P 3000 2850
+F 0 "Rin1" V 3080 2850 50  0000 C CNN
+F 1 "2e6" V 3000 2850 50  0000 C CNN
+F 2 "" H 3000 2850 60  0001 C CNN
+F 3 "" H 3000 2850 60  0001 C CNN
+	1    3000 2850
+	1    0    0    -1  
+$EndComp
+Connection ~ 3700 3200
+Wire Wire Line
+	3450 3200 3700 3200
+Connection ~ 5000 3300
+Wire Wire Line
+	3700 3300 5250 3300
+Wire Wire Line
+	5250 3300 5250 3200
+Connection ~ 4550 3300
+Wire Wire Line
+	5000 3300 5000 2950
+Connection ~ 3700 3300
+Wire Wire Line
+	4550 3050 4550 3300
+Wire Wire Line
+	3700 2500 4000 2500
+Wire Wire Line
+	3700 2500 3700 2550
+Wire Wire Line
+	3450 2900 3300 2900
+Wire Wire Line
+	3300 2900 3300 3200
+Wire Wire Line
+	3300 3200 2950 3200
+Connection ~ 2950 3100
+Wire Wire Line
+	2950 3200 2950 3100
+Wire Wire Line
+	3000 2600 2500 2600
+Wire Wire Line
+	2550 3100 3000 3100
+Wire Wire Line
+	2950 2600 2950 2500
+Connection ~ 2950 2600
+Wire Wire Line
+	2950 2500 3300 2500
+Wire Wire Line
+	3300 2500 3300 2800
+Wire Wire Line
+	3300 2800 3450 2800
+Wire Wire Line
+	3700 3150 3700 3400
+Wire Wire Line
+	4550 2500 4550 2750
+Wire Wire Line
+	4300 2500 5000 2500
+Wire Wire Line
+	5000 2500 5000 2850
+Connection ~ 4550 2500
+Wire Wire Line
+	5250 2600 5250 2500
+Wire Wire Line
+	5250 2500 5450 2500
+Wire Wire Line
+	5750 2500 6000 2500
+Wire Wire Line
+	3000 3100 3000 3000
+Wire Wire Line
+	3000 2700 3000 2600
+$EndSCHEMATC
diff --git a/Examples/Inverting_Amplifier/ua741.sub b/Examples/Inverting_Amplifier/ua741.sub
new file mode 100644
index 00000000..ad26c001
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741.sub
@@ -0,0 +1,12 @@
+* Subcircuit ua741
+.subckt ua741 6 7 3 
+* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:16:58 am ist
+rout1  3 2 75
+eout1  2 0 1 0 1
+cbw1  1 0 31.85e-9
+rbw1  1 4 0.5e6
+ein1  4 0 7 6 100e3
+rin1  7 6 2e6
+* Control Statements
+
+.ends ua741
\ No newline at end of file
diff --git a/Examples/Inverting_Amplifier/ua741_Previous_Values.xml b/Examples/Inverting_Amplifier/ua741_Previous_Values.xml
new file mode 100644
index 00000000..9c7bb530
--- /dev/null
+++ b/Examples/Inverting_Amplifier/ua741_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file