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authorSunil Shetye2019-03-11 12:11:24 +0530
committerSunil Shetye2019-07-01 17:41:27 +0530
commit5e116a4676854289fabeb6cce57f3d01ae8f5709 (patch)
tree317985a949497440e3bb98ac07ab0e2a0d5a9a1c /Examples/Integrator/scr.sub~
parente9064e423b586c2a31926fb5a1e582e8d1f626f8 (diff)
downloadeSim-5e116a4676854289fabeb6cce57f3d01ae8f5709.tar.gz
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remove temporary files
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-* Subcircuit scr
-.subckt scr 3 7 1
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-.include PowerDiode.lib
-* f2
-d1 5 2 PowerDiode
-c1 3 9 10u
-* f1
-v1 8 4 dc 0
-v2 6 5 dc 0
-* u1 9 1 6 aswitch
-r1 7 8 50
-r2 3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 [1 6 ] u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
-* Control Statements
-
-.ends scr \ No newline at end of file