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authorSunil Shetye2019-07-01 18:12:34 +0530
committerGitHub2019-07-01 18:12:34 +0530
commit29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (patch)
tree6d3b2a1ba2c92ba6bfb898f534576a2331cf9f9d /Examples/HalfwaveRectifier_SCR
parent6b410587b3101af7c6378c8e816e7d357beb1929 (diff)
parentaec27ddec95f30c155ad356da24eb7e3ce2247cd (diff)
downloadeSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.gz
eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.bz2
eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.zip
Merge pull request #114 from sunilshetye/masterfixes
Master fixes
Diffstat (limited to 'Examples/HalfwaveRectifier_SCR')
-rwxr-xr-xExamples/HalfwaveRectifier_SCR/D.lib20
-rw-r--r--Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR-cache.lib134
-rw-r--r--Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR.bak201
-rw-r--r--Examples/HalfwaveRectifier_SCR/PowerDiode.lib21
-rw-r--r--Examples/HalfwaveRectifier_SCR/scr.bak243
-rw-r--r--Examples/HalfwaveRectifier_SCR/scr.cir.ckt19
-rw-r--r--Examples/HalfwaveRectifier_SCR/scr.cir.out~29
-rw-r--r--Examples/HalfwaveRectifier_SCR/scr.sub~23
8 files changed, 1 insertions, 689 deletions
diff --git a/Examples/HalfwaveRectifier_SCR/D.lib b/Examples/HalfwaveRectifier_SCR/D.lib
deleted file mode 100755
index ef18bb50..00000000
--- a/Examples/HalfwaveRectifier_SCR/D.lib
+++ /dev/null
@@ -1,20 +0,0 @@
-.MODEL D1N750 D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
-+ Tbv1=-21.277u
-+ Bv=8.1
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=880.5E-18
-+ Xti=3
-+ Ibvl=1.9556m
-) \ No newline at end of file
diff --git a/Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR-cache.lib b/Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR-cache.lib
deleted file mode 100644
index 89d2a843..00000000
--- a/Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR-cache.lib
+++ /dev/null
@@ -1,134 +0,0 @@
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diff --git a/Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR.bak b/Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR.bak
deleted file mode 100644
index c3bb45a5..00000000
--- a/Examples/HalfwaveRectifier_SCR/HalfwaveRectifier_SCR.bak
+++ /dev/null
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diff --git a/Examples/HalfwaveRectifier_SCR/PowerDiode.lib b/Examples/HalfwaveRectifier_SCR/PowerDiode.lib
index a2f61dce..d6fb6469 100644
--- a/Examples/HalfwaveRectifier_SCR/PowerDiode.lib
+++ b/Examples/HalfwaveRectifier_SCR/PowerDiode.lib
@@ -1,20 +1 @@
-.MODEL PowerDiode D(
-+ Vj=.75
-+ Nbvl=14.976
-+ Cjo=175p
-+ Rs=.25
-+ Isr=1.859n
-+ Eg=1.11
-+ M=.5516
-+ Nbv=1.6989
-+ N=1
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-+ bv=1800
-+ Fc=.5
-+ Ikf=0
-+ Nr=2
-+ Ibv=20.245m
-+ Is=2.2E-15
-+ Xti=3
-+ Ibvl=1.9556m
-) \ No newline at end of file
+.MODEL PowerDiode D( Vj=.75 Nbvl=14.976 Cjo=175p Rs=.25 Isr=1.859n Eg=1.11 M=.5516 Nbv=1.6989 N=1 Tbv1=-21.277u bv=1800 Fc=.5 Ikf=0 Nr=2 Ibv=20.245m Is=2.2E-15 Xti=3 Ibvl=1.9556m )
diff --git a/Examples/HalfwaveRectifier_SCR/scr.bak b/Examples/HalfwaveRectifier_SCR/scr.bak
deleted file mode 100644
index 58b985d9..00000000
--- a/Examples/HalfwaveRectifier_SCR/scr.bak
+++ /dev/null
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diff --git a/Examples/HalfwaveRectifier_SCR/scr.cir.ckt b/Examples/HalfwaveRectifier_SCR/scr.cir.ckt
deleted file mode 100644
index b0e218fd..00000000
--- a/Examples/HalfwaveRectifier_SCR/scr.cir.ckt
+++ /dev/null
@@ -1,19 +0,0 @@
-* eeschema netlist version 1.1 (spice format) creation date: 08/21/14 11:07:22
-.include diode.lib
-
-u2 5 8 1 port
-* f2
-* Analog Switch analogswitch
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diff --git a/Examples/HalfwaveRectifier_SCR/scr.cir.out~ b/Examples/HalfwaveRectifier_SCR/scr.cir.out~
deleted file mode 100644
index d600f25d..00000000
--- a/Examples/HalfwaveRectifier_SCR/scr.cir.out~
+++ /dev/null
@@ -1,29 +0,0 @@
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-
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-
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-run
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-print alli > plot_data_i.txt
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-.end
diff --git a/Examples/HalfwaveRectifier_SCR/scr.sub~ b/Examples/HalfwaveRectifier_SCR/scr.sub~
deleted file mode 100644
index 0fdddbf4..00000000
--- a/Examples/HalfwaveRectifier_SCR/scr.sub~
+++ /dev/null
@@ -1,23 +0,0 @@
-* Subcircuit scr
-.subckt scr 3 7 1
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-.include PowerDiode.lib
-* f2
-d1 5 2 PowerDiode
-c1 3 9 10u
-* f1
-v1 8 4 dc 0
-v2 6 5 dc 0
-* u1 9 1 6 aswitch
-r1 7 8 50
-r2 3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 [1 6 ] u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
-* Control Statements
-
-.ends scr \ No newline at end of file