common code for Win and Linux, merged py2 changes

10 files changed, 606 insertions, 0 deletions

diff --git a/Examples/Half_Adder/Half_Adder-cache.lib b/Examples/Half_Adder/Half_Adder-cache.lib
new file mode 100644
index 00000000..92d3bca5
--- /dev/null
+++ b/Examples/Half_Adder/Half_Adder-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND-RESCUE-Half_Adder
+#
+DEF ~GND-RESCUE-Half_Adder #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 0 30 H I C CNN
+F1 "GND-RESCUE-Half_Adder" 0 -70 30 H I C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N
+X GND 1 0 0 0 U 30 30 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# R-RESCUE-Half_Adder
+#
+DEF R-RESCUE-Half_Adder R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "R-RESCUE-Half_Adder" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_adder
+#
+DEF half_adder X 0 40 Y Y 1 F N
+F0 "X" 900 500 60 H V C CNN
+F1 "half_adder" 900 400 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 500 800 1250 0 0 1 0 N
+X IN1 1 300 700 200 R 50 50 1 1 I
+X IN2 2 300 100 200 R 50 50 1 1 I
+X SUM 3 1450 700 200 L 50 50 1 1 O
+X COUT 4 1450 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Half_Adder/Half_Adder-rescue.lib b/Examples/Half_Adder/Half_Adder-rescue.lib
new file mode 100644
index 00000000..3d16d4cb
--- /dev/null
+++ b/Examples/Half_Adder/Half_Adder-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# R-RESCUE-Half_Adder
+#
+DEF R-RESCUE-Half_Adder R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "R-RESCUE-Half_Adder" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Half_Adder/Half_Adder.cir b/Examples/Half_Adder/Half_Adder.cir
new file mode 100644
index 00000000..4658c5cb
--- /dev/null
+++ b/Examples/Half_Adder/Half_Adder.cir
@@ -0,0 +1,21 @@
+* /home/fossee/UpdatedExamples/Half_Adder/Half_Adder.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar  3 21:35:33 2016
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad1_ Net-_U2-Pad2_ half_adder		
+U1  IN1 IN2 Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2		
+U2  Net-_U2-Pad1_ Net-_U2-Pad2_ sum cout dac_bridge_2		
+v1  IN1 GND DC		
+v2  IN2 GND DC		
+R1  sum GND 1k		
+R2  cout GND 1k		
+U3  IN1 plot_v1		
+U4  IN2 plot_v1		
+U5  sum plot_v1		
+U6  cout plot_v1		
+
+.end
diff --git a/Examples/Half_Adder/Half_Adder.cir.out b/Examples/Half_Adder/Half_Adder.cir.out
new file mode 100644
index 00000000..96066fff
--- /dev/null
+++ b/Examples/Half_Adder/Half_Adder.cir.out
@@ -0,0 +1,33 @@
+* /home/fossee/updatedexamples/half_adder/half_adder.cir
+
+.include half_adder.sub
+x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder
+* u1  in1 in2 net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
+* u2  net-_u2-pad1_ net-_u2-pad2_ sum cout dac_bridge_2
+v1 in1 gnd  dc 5
+v2 in2 gnd  dc 0
+r1  sum gnd 1k
+r2  cout gnd 1k
+* u3  in1 plot_v1
+* u4  in2 plot_v1
+* u5  sum plot_v1
+* u6  cout plot_v1
+a1 [in1 in2 ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) 
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(in1)
+plot v(in2)
+plot v(sum)
+plot v(cout)
+.endc
+.end
diff --git a/Examples/Half_Adder/Half_Adder.pro b/Examples/Half_Adder/Half_Adder.pro
new file mode 100644
index 00000000..5316e430
--- /dev/null
+++ b/Examples/Half_Adder/Half_Adder.pro
@@ -0,0 +1,74 @@
+update=Wed Jul 10 18:10:53 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=Half_Adder-rescue
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
+LibName11=power
+LibName12=device
+LibName13=transistors
+LibName14=conn
+LibName15=linear
+LibName16=regul
+LibName17=74xx
+LibName18=cmos4000
+LibName19=adc-dac
+LibName20=memory
+LibName21=xilinx
+LibName22=special
+LibName23=microcontrollers
+LibName24=dsp
+LibName25=microchip
+LibName26=analog_switches
+LibName27=motorola
+LibName28=texas
+LibName29=intel
+LibName30=audio
+LibName31=interface
+LibName32=digital-audio
+LibName33=philips
+LibName34=display
+LibName35=cypress
+LibName36=siliconi
+LibName37=opto
+LibName38=atmel
+LibName39=contrib
+LibName40=valves
+LibName41=eSim_Power
diff --git a/Examples/Half_Adder/Half_Adder.proj b/Examples/Half_Adder/Half_Adder.proj
new file mode 100644
index 00000000..cc4f1c32
--- /dev/null
+++ b/Examples/Half_Adder/Half_Adder.proj
@@ -0,0 +1 @@
+schematicFile Half_Adder.sch
diff --git a/Examples/Half_Adder/Half_Adder.sch b/Examples/Half_Adder/Half_Adder.sch
new file mode 100644
index 00000000..97cb4b04
--- /dev/null
+++ b/Examples/Half_Adder/Half_Adder.sch
@@ -0,0 +1,313 @@
+EESchema Schematic File Version 2
+LIBS:Half_Adder-rescue
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Power
+LIBS:Half_Adder-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L half_adder X1
+U 1 1 558A91C8
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+F 0 "X1" H 5900 4400 60  0000 C CNN
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+F 2 "" H 5000 3900 60  0000 C CNN
+F 3 "" H 5000 3900 60  0000 C CNN
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+	1    0    0    -1  
+$EndComp
+$Comp
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+F 3 "" H 6950 3450 60  0000 C CNN
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+$EndComp
+$Comp
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+F 3 "" H 2850 3850 60  0000 C CNN
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+Text GLabel 7600 3750 0    60   Input ~ 0
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+Text GLabel 4050 3150 2    60   Input ~ 0
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+Text GLabel 4100 3750 2    60   Input ~ 0
+IN2
+$Comp
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+F 3 "" V 7850 3400 30  0000 C CNN
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+$EndComp
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diff --git a/Examples/Half_Adder/Half_Adder_Previous_Values.xml b/Examples/Half_Adder/Half_Adder_Previous_Values.xml
new file mode 100644
index 00000000..ca482668
--- /dev/null
+++ b/Examples/Half_Adder/Half_Adder_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u2 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /><subcircuit><x1><field>/home/fossee/esim-updated/eSim/src/SubcircuitLibrary/half_adder</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/Half_Adder/analysis b/Examples/Half_Adder/analysis
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/Examples/Half_Adder/analysis
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03
\ No newline at end of file
diff --git a/Examples/Half_Adder/half_adder.sub b/Examples/Half_Adder/half_adder.sub
new file mode 100644
index 00000000..e9f92223
--- /dev/null
+++ b/Examples/Half_Adder/half_adder.sub
@@ -0,0 +1,14 @@
+* Subcircuit half_adder
+.subckt half_adder 1 4 3 2 
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+* u2  1 4 3 d_xor
+* u3  1 4 2 d_and
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends half_adder
\ No newline at end of file