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authorSunil Shetye2019-03-11 15:57:40 +0530
committerSunil Shetye2019-07-01 17:43:18 +0530
commitef380a4a6a2ff4c90bde90c41296e94f5db70389 (patch)
tree13acc3811724d347e87f8667f6c8a4f7ebb2c212 /Examples/Half_Adder/Half_Adder.cir.out
parent5e116a4676854289fabeb6cce57f3d01ae8f5709 (diff)
downloadeSim-ef380a4a6a2ff4c90bde90c41296e94f5db70389.tar.gz
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Half adder subcircuit filename conflict in Windows
Replaced Half_Adder example with renamed HalfAdder to avoid Windows case-only filename difference conflict with subcircuit half_adder. Based on contribution by https://github.com/MaxOLydian/eSim
Diffstat (limited to 'Examples/Half_Adder/Half_Adder.cir.out')
-rw-r--r--Examples/Half_Adder/Half_Adder.cir.out33
1 files changed, 0 insertions, 33 deletions
diff --git a/Examples/Half_Adder/Half_Adder.cir.out b/Examples/Half_Adder/Half_Adder.cir.out
deleted file mode 100644
index 96066fff..00000000
--- a/Examples/Half_Adder/Half_Adder.cir.out
+++ /dev/null
@@ -1,33 +0,0 @@
-* /home/fossee/updatedexamples/half_adder/half_adder.cir
-
-.include half_adder.sub
-x1 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad1_ net-_u2-pad2_ half_adder
-* u1 in1 in2 net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
-* u2 net-_u2-pad1_ net-_u2-pad2_ sum cout dac_bridge_2
-v1 in1 gnd dc 5
-v2 in2 gnd dc 0
-r1 sum gnd 1k
-r2 cout gnd 1k
-* u3 in1 plot_v1
-* u4 in2 plot_v1
-* u5 sum plot_v1
-* u6 cout plot_v1
-a1 [in1 in2 ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
-a2 [net-_u2-pad1_ net-_u2-pad2_ ] [sum cout ] u2
-* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
-.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
-* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
-.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-plot v(in1)
-plot v(in2)
-plot v(sum)
-plot v(cout)
-.endc
-.end