summaryrefslogtreecommitdiff
path: root/Examples/HalfAdder/half_adder.sub
diff options
context:
space:
mode:
authorSunil Shetye2019-07-01 18:12:34 +0530
committerGitHub2019-07-01 18:12:34 +0530
commit29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (patch)
tree6d3b2a1ba2c92ba6bfb898f534576a2331cf9f9d /Examples/HalfAdder/half_adder.sub
parent6b410587b3101af7c6378c8e816e7d357beb1929 (diff)
parentaec27ddec95f30c155ad356da24eb7e3ce2247cd (diff)
downloadeSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.gz
eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.bz2
eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.zip
Merge pull request #114 from sunilshetye/masterfixes
Master fixes
Diffstat (limited to 'Examples/HalfAdder/half_adder.sub')
-rw-r--r--Examples/HalfAdder/half_adder.sub14
1 files changed, 14 insertions, 0 deletions
diff --git a/Examples/HalfAdder/half_adder.sub b/Examples/HalfAdder/half_adder.sub
new file mode 100644
index 00000000..e9f92223
--- /dev/null
+++ b/Examples/HalfAdder/half_adder.sub
@@ -0,0 +1,14 @@
+* Subcircuit half_adder
+.subckt half_adder 1 4 3 2
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+* u2 1 4 3 d_xor
+* u3 1 4 2 d_and
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends half_adder \ No newline at end of file