diff options
| author | Sunil Shetye | 2019-03-11 15:57:40 +0530 |
|---|---|---|
| committer | Sunil Shetye | 2019-07-01 17:43:18 +0530 |
| commit | ef380a4a6a2ff4c90bde90c41296e94f5db70389 (patch) | |
| tree | 13acc3811724d347e87f8667f6c8a4f7ebb2c212 /Examples/HalfAdder/half_adder.cir.out | |
| parent | 5e116a4676854289fabeb6cce57f3d01ae8f5709 (diff) | |
| download | eSim-ef380a4a6a2ff4c90bde90c41296e94f5db70389.tar.gz eSim-ef380a4a6a2ff4c90bde90c41296e94f5db70389.tar.bz2 eSim-ef380a4a6a2ff4c90bde90c41296e94f5db70389.zip | |
Half adder subcircuit filename conflict in Windows
Replaced Half_Adder example with renamed HalfAdder to avoid Windows
case-only filename difference conflict with subcircuit half_adder.
Based on contribution by https://github.com/MaxOLydian/eSim
Diffstat (limited to 'Examples/HalfAdder/half_adder.cir.out')
| -rw-r--r-- | Examples/HalfAdder/half_adder.cir.out | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/Examples/HalfAdder/half_adder.cir.out b/Examples/HalfAdder/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/Examples/HalfAdder/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |