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authorSunil Shetye2019-07-01 18:12:34 +0530
committerGitHub2019-07-01 18:12:34 +0530
commit29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (patch)
tree6d3b2a1ba2c92ba6bfb898f534576a2331cf9f9d /Examples/FullwaveRectifier_SCR/scr.sub~
parent6b410587b3101af7c6378c8e816e7d357beb1929 (diff)
parentaec27ddec95f30c155ad356da24eb7e3ce2247cd (diff)
downloadeSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.gz
eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.bz2
eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.zip
Merge pull request #114 from sunilshetye/masterfixes
Master fixes
Diffstat (limited to 'Examples/FullwaveRectifier_SCR/scr.sub~')
-rw-r--r--Examples/FullwaveRectifier_SCR/scr.sub~23
1 files changed, 0 insertions, 23 deletions
diff --git a/Examples/FullwaveRectifier_SCR/scr.sub~ b/Examples/FullwaveRectifier_SCR/scr.sub~
deleted file mode 100644
index 0fdddbf4..00000000
--- a/Examples/FullwaveRectifier_SCR/scr.sub~
+++ /dev/null
@@ -1,23 +0,0 @@
-* Subcircuit scr
-.subckt scr 3 7 1
-* /opt/esim/src/subcircuitlibrary/scr/scr.cir
-.include PowerDiode.lib
-* f2
-d1 5 2 PowerDiode
-c1 3 9 10u
-* f1
-v1 8 4 dc 0
-v2 6 5 dc 0
-* u1 9 1 6 aswitch
-r1 7 8 50
-r2 3 9 1
-Vf2 2 3 0
-f2 3 9 Vf2 100
-Vf1 4 3 0
-f1 3 9 Vf1 10
-a1 9 [1 6 ] u1
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
-* Control Statements
-
-.ends scr \ No newline at end of file