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| author | Fahim | 2016-03-03 23:00:00 +0530 |
|---|---|---|
| committer | Fahim | 2016-03-03 23:00:00 +0530 |
| commit | 7e4774656997c34eae3ab09b37c8f82b5b046d48 (patch) | |
| tree | fe72483af0c1feba7f97d5b9290f647f50840fc1 /Examples/FullwaveRectifier_SCR/scr.sub~ | |
| parent | 823d892cbafccc47287ffebd01316754e7efad56 (diff) | |
| download | eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.gz eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.bz2 eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.zip | |
Remove unwanted example
Diffstat (limited to 'Examples/FullwaveRectifier_SCR/scr.sub~')
| -rw-r--r-- | Examples/FullwaveRectifier_SCR/scr.sub~ | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/Examples/FullwaveRectifier_SCR/scr.sub~ b/Examples/FullwaveRectifier_SCR/scr.sub~ new file mode 100644 index 00000000..0fdddbf4 --- /dev/null +++ b/Examples/FullwaveRectifier_SCR/scr.sub~ @@ -0,0 +1,23 @@ +* Subcircuit scr +.subckt scr 3 7 1 +* /opt/esim/src/subcircuitlibrary/scr/scr.cir +.include PowerDiode.lib +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 [1 6 ] u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +* Control Statements + +.ends scr
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