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authorFahim2016-03-03 23:00:00 +0530
committerFahim2016-03-03 23:00:00 +0530
commit7e4774656997c34eae3ab09b37c8f82b5b046d48 (patch)
treefe72483af0c1feba7f97d5b9290f647f50840fc1 /Examples/FullwaveRectifier_SCR/scr.cir
parent823d892cbafccc47287ffebd01316754e7efad56 (diff)
downloadeSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.gz
eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.tar.bz2
eSim-7e4774656997c34eae3ab09b37c8f82b5b046d48.zip
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+* /opt/eSim/src/SubcircuitLibrary/scr/scr.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:47:20 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 3 7 1 PORT
+F2 3 9 2 3 100
+D1 5 2 D
+C1 3 9 10u
+F1 3 9 4 3 10
+v1 8 4 dc
+v2 6 5 dc
+U1 9 1 6 aswitch
+R1 7 8 50
+R2 3 9 1
+
+.end