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| author | Fahim | 2015-08-19 15:49:33 +0530 |
|---|---|---|
| committer | Fahim | 2015-08-19 15:49:33 +0530 |
| commit | 5e81c99de1606d01c5d07fbe35005ad5a4298c7f (patch) | |
| tree | f380242a8f6f4133a2eca5fc5efbf4a49be811ed /Examples/Full_Adder/half_adder.cir.out | |
| parent | 0a10771024b1b82b69b23aa770a664b8653f985e (diff) | |
| download | eSim-5e81c99de1606d01c5d07fbe35005ad5a4298c7f.tar.gz eSim-5e81c99de1606d01c5d07fbe35005ad5a4298c7f.tar.bz2 eSim-5e81c99de1606d01c5d07fbe35005ad5a4298c7f.zip | |
Modified Example
Diffstat (limited to 'Examples/Full_Adder/half_adder.cir.out')
| -rw-r--r-- | Examples/Full_Adder/half_adder.cir.out | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/Examples/Full_Adder/half_adder.cir.out b/Examples/Full_Adder/half_adder.cir.out deleted file mode 100644 index b1b6b1e7..00000000 --- a/Examples/Full_Adder/half_adder.cir.out +++ /dev/null @@ -1,20 +0,0 @@ -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 - -* u2 1 4 3 d_xor -* u3 1 4 2 d_and -* u1 1 4 3 2 port -a1 [1 4 ] 3 u2 -a2 [1 4 ] 2 u3 -* Schematic Name: d_xor, NgSpice Name: d_xor -.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.ac lin 0 0Hz 0Hz - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end |