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| author | fahim | 2015-08-05 13:52:57 +0530 |
|---|---|---|
| committer | fahim | 2015-08-05 13:52:57 +0530 |
| commit | df569f79a7ee495291324e07d99af990104e3db2 (patch) | |
| tree | a005c682aa78b58b7dd5bb693c415eff9c04d04b /Examples/Full_Adder/full_adder.sub | |
| parent | c4971ed867af4a970a3cd1c23825adee5073372e (diff) | |
| download | eSim-df569f79a7ee495291324e07d99af990104e3db2.tar.gz eSim-df569f79a7ee495291324e07d99af990104e3db2.tar.bz2 eSim-df569f79a7ee495291324e07d99af990104e3db2.zip | |
Subject: Added eSim Examples
Description: Added eSim Examples
Diffstat (limited to 'Examples/Full_Adder/full_adder.sub')
| -rw-r--r-- | Examples/Full_Adder/full_adder.sub | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/Examples/Full_Adder/full_adder.sub b/Examples/Full_Adder/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/Examples/Full_Adder/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
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