diff options
| author | Fahim | 2015-08-19 15:49:33 +0530 |
|---|---|---|
| committer | Fahim | 2015-08-19 15:49:33 +0530 |
| commit | 5e81c99de1606d01c5d07fbe35005ad5a4298c7f (patch) | |
| tree | f380242a8f6f4133a2eca5fc5efbf4a49be811ed /Examples/Full_Adder/full_adder.sub | |
| parent | 0a10771024b1b82b69b23aa770a664b8653f985e (diff) | |
| download | eSim-5e81c99de1606d01c5d07fbe35005ad5a4298c7f.tar.gz eSim-5e81c99de1606d01c5d07fbe35005ad5a4298c7f.tar.bz2 eSim-5e81c99de1606d01c5d07fbe35005ad5a4298c7f.zip | |
Modified Example
Diffstat (limited to 'Examples/Full_Adder/full_adder.sub')
| -rw-r--r-- | Examples/Full_Adder/full_adder.sub | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/Examples/Full_Adder/full_adder.sub b/Examples/Full_Adder/full_adder.sub deleted file mode 100644 index 5f261f78..00000000 --- a/Examples/Full_Adder/full_adder.sub +++ /dev/null @@ -1,13 +0,0 @@ -* Subcircuit full_adder -.subckt full_adder 8 7 5 4 1 -* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 -.include half_adder.sub -x1 8 7 6 2 half_adder -x2 5 6 4 3 half_adder -* u2 3 2 1 d_or -a1 [3 2 ] 1 u2 -* Schematic Name: d_or, NgSpice Name: d_or -.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends full_adder
\ No newline at end of file |