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authorSunil Shetye2019-03-11 12:11:24 +0530
committerSunil Shetye2019-07-01 17:41:27 +0530
commit5e116a4676854289fabeb6cce57f3d01ae8f5709 (patch)
tree317985a949497440e3bb98ac07ab0e2a0d5a9a1c /Examples/Diac_Triac/triac.cir.ckt
parente9064e423b586c2a31926fb5a1e582e8d1f626f8 (diff)
downloadeSim-5e116a4676854289fabeb6cce57f3d01ae8f5709.tar.gz
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-* eeschema netlist version 1.1 (spice format) creation date: 09/20/14 11:23:24
-.include diode.lib
-
-u3 7 4 5 port
-* f3
-d2 3 2 diode
-v3 2 1 dc 0
-* Analog Switch analogswitch
-d1 11 7 diode
-* f2
-v2 8 10 dc 0
-* Analog Switch analogswitch
-c1 7 9 10u
-r1 7 9 1
-* f1
-v1 5 6 dc 0
-Vf3 3 7 0
-f3 7 9 Vf3 10
-Vf2 10 11 0
-f2 7 9 Vf2 10
-Vf1 6 7 0
-f1 7 9 Vf1 100
-a1 9 (1 4) u2
-.model u2 aswitch(cntl_on=-1 cntl_off=-0.1 r_on=0.0125 r_off=1000000)
-a2 9 (4 8) u1
-.model u1 aswitch(cntl_on=1 cntl_off=0.1 r_on=0.0125 r_off=1000000)