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authorSunil Shetye2019-07-01 18:12:34 +0530
committerGitHub2019-07-01 18:12:34 +0530
commit29dc2de214a60216e62d80dfa3e5cbd998c2d6ee (patch)
tree6d3b2a1ba2c92ba6bfb898f534576a2331cf9f9d /Examples/Diac_Triac/diac.sub~
parent6b410587b3101af7c6378c8e816e7d357beb1929 (diff)
parentaec27ddec95f30c155ad356da24eb7e3ce2247cd (diff)
downloadeSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.gz
eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.tar.bz2
eSim-29dc2de214a60216e62d80dfa3e5cbd998c2d6ee.zip
Merge pull request #114 from sunilshetye/masterfixes
Master fixes
Diffstat (limited to 'Examples/Diac_Triac/diac.sub~')
-rw-r--r--Examples/Diac_Triac/diac.sub~18
1 files changed, 0 insertions, 18 deletions
diff --git a/Examples/Diac_Triac/diac.sub~ b/Examples/Diac_Triac/diac.sub~
deleted file mode 100644
index 43c2d279..00000000
--- a/Examples/Diac_Triac/diac.sub~
+++ /dev/null
@@ -1,18 +0,0 @@
-* Subcircuit diac
-.subckt diac 1 2
-* /opt/esim/src/subcircuitlibrary/diac/diac.cir
-* u1 1 1 2 aswitch
-* u2 1 1 2 aswitch
-a1 1 [1 2 ] u1
-a2 1 [1 2 ] u2
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 )
-* Schematic Name: aswitch, NgSpice Name: aswitch
-.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 )
-* Control Statements
-
-.ends diac \ No newline at end of file