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| author | Sunil Shetye | 2019-03-11 12:11:24 +0530 |
|---|---|---|
| committer | Sunil Shetye | 2019-07-01 17:41:27 +0530 |
| commit | 5e116a4676854289fabeb6cce57f3d01ae8f5709 (patch) | |
| tree | 317985a949497440e3bb98ac07ab0e2a0d5a9a1c /Examples/Diac_Triac/diac.cir.out~ | |
| parent | e9064e423b586c2a31926fb5a1e582e8d1f626f8 (diff) | |
| download | eSim-5e116a4676854289fabeb6cce57f3d01ae8f5709.tar.gz eSim-5e116a4676854289fabeb6cce57f3d01ae8f5709.tar.bz2 eSim-5e116a4676854289fabeb6cce57f3d01ae8f5709.zip | |
remove temporary files
Diffstat (limited to 'Examples/Diac_Triac/diac.cir.out~')
| -rw-r--r-- | Examples/Diac_Triac/diac.cir.out~ | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/Examples/Diac_Triac/diac.cir.out~ b/Examples/Diac_Triac/diac.cir.out~ deleted file mode 100644 index 89cc8142..00000000 --- a/Examples/Diac_Triac/diac.cir.out~ +++ /dev/null @@ -1,24 +0,0 @@ -* /opt/esim/src/subcircuitlibrary/diac/diac.cir - -* u3 1 2 port -* u1 1 1 2 aswitch -* u2 1 1 2 aswitch -a1 1 [1 2 ] u1 -a2 1 [1 2 ] u2 -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) -* Schematic Name: aswitch, NgSpice Name: aswitch -.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end |