Merge pull request #152 from saurabhb17/master

Subcircuit for CMOS based NAND gate and its supporting example

17 files changed, 871 insertions, 0 deletions

diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND-cache.lib b/Examples/CMOS_NAND_Gate/CMOS_NAND-cache.lib
new file mode 100644
index 00000000..99c6453a
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND-cache.lib
@@ -0,0 +1,130 @@
+EESchema-LIBRARY Version 2.3

+#encoding utf-8

+#

+# DC

+#

+DEF DC v 0 40 Y Y 1 F N

+F0 "v" -200 100 60 H V C CNN

+F1 "DC" -200 -50 60 H V C CNN

+F2 "R1" -300 0 60 H V C CNN

+F3 "" 0 0 60 H V C CNN

+$FPLIST

+ 1_pin

+$ENDFPLIST

+DRAW

+C 0 0 150 0 1 0 N

+X + 1 0 450 300 D 50 50 1 1 w

+X - 2 0 -450 300 U 50 50 1 1 w

+ENDDRAW

+ENDDEF

+#

+# GND

+#

+DEF GND #PWR 0 0 Y Y 1 F P

+F0 "#PWR" 0 -250 50 H I C CNN

+F1 "GND" 0 -150 50 H V C CNN

+F2 "" 0 0 50 H I C CNN

+F3 "" 0 0 50 H I C CNN

+DRAW

+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N

+X GND 1 0 0 0 D 50 50 1 1 W N

+ENDDRAW

+ENDDEF

+#

+# PORT

+#

+DEF PORT U 0 40 Y Y 26 F N

+F0 "U" 50 100 30 H V C CNN

+F1 "PORT" 0 0 30 H V C CNN

+F2 "" 0 0 60 H V C CNN

+F3 "" 0 0 60 H V C CNN

+DRAW

+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0

+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50

+S -100 50 100 -50 0 1 0 N

+X ~ 1 250 0 100 L 30 30 1 1 B

+X ~ 2 250 0 100 L 30 30 2 1 B

+X ~ 3 250 0 100 L 30 30 3 1 B

+X ~ 4 250 0 100 L 30 30 4 1 B

+X ~ 5 250 0 100 L 30 30 5 1 B

+X ~ 6 250 0 100 L 30 30 6 1 B

+X ~ 7 250 0 100 L 30 30 7 1 B

+X ~ 8 250 0 100 L 30 30 8 1 B

+X ~ 9 250 0 100 L 30 30 9 1 B

+X ~ 10 250 0 100 L 30 30 10 1 B

+X ~ 11 250 0 100 L 30 30 11 1 B

+X ~ 12 250 0 100 L 30 30 12 1 B

+X ~ 13 250 0 100 L 30 30 13 1 B

+X ~ 14 250 0 100 L 30 30 14 1 B

+X ~ 15 250 0 100 L 30 30 15 1 B

+X ~ 16 250 0 100 L 30 30 16 1 B

+X ~ 17 250 0 100 L 30 30 17 1 B

+X ~ 18 250 0 100 L 30 30 18 1 B

+X ~ 19 250 0 100 L 30 30 19 1 B

+X ~ 20 250 0 100 L 30 30 20 1 B

+X ~ 21 250 0 100 L 30 30 21 1 B

+X ~ 22 250 0 100 L 30 30 22 1 B

+X ~ 23 250 0 100 L 30 30 23 1 B

+X ~ 24 250 0 100 L 30 30 24 1 B

+X ~ 25 250 0 100 L 30 30 25 1 B

+X ~ 26 250 0 100 L 30 30 26 1 B

+ENDDRAW

+ENDDEF

+#

+# eSim_MOS_N

+#

+DEF eSim_MOS_N M 0 0 Y N 1 F N

+F0 "M" 0 -150 50 H V R CNN

+F1 "eSim_MOS_N" 100 -50 50 H V R CNN

+F2 "" 300 -300 29 H V C CNN

+F3 "" 100 -200 60 H V C CNN

+ALIAS mosfet_n

+DRAW

+C 150 -200 111 0 1 10 N

+P 2 0 1 10 130 -290 130 -250 N

+P 2 0 1 0 130 -270 200 -270 N

+P 2 0 1 10 130 -220 130 -180 N

+P 2 0 1 0 130 -200 200 -200 N

+P 2 0 1 10 130 -150 130 -110 N

+P 2 0 1 0 130 -130 200 -130 N

+P 2 0 1 0 200 -300 200 -270 N

+P 2 0 1 0 200 -130 200 -100 N

+P 3 0 1 10 110 -275 110 -125 110 -125 N

+P 3 0 1 0 200 -200 300 -200 300 -250 N

+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F

+X D 1 200 0 100 D 50 50 1 1 P

+X G 2 -100 -200 210 R 50 50 1 1 P

+X S 3 200 -400 100 U 50 50 1 1 P

+X B 4 300 -350 98 U 47 47 1 1 P

+ENDDRAW

+ENDDEF

+#

+# eSim_MOS_P

+#

+DEF eSim_MOS_P M 0 0 Y N 1 F N

+F0 "M" -50 50 50 H V R CNN

+F1 "eSim_MOS_P" 50 150 50 H V R CNN

+F2 "" 250 100 29 H V C CNN

+F3 "" 50 0 60 H V C CNN

+ALIAS mosfet_p

+DRAW

+C 100 0 111 0 1 10 N

+P 2 0 1 0 80 -70 150 -70 N

+P 2 0 1 10 80 -50 80 -90 N

+P 2 0 1 0 80 0 150 0 N

+P 2 0 1 10 80 20 80 -20 N

+P 2 0 1 0 80 70 150 70 N

+P 2 0 1 10 80 90 80 50 N

+P 2 0 1 0 150 -70 150 -100 N

+P 2 0 1 0 150 100 150 70 N

+P 3 0 1 10 60 75 60 -75 60 -75 N

+P 3 0 1 0 150 0 250 0 250 -50 N

+P 4 0 1 0 140 0 100 -15 100 15 140 0 F

+X D 1 150 200 100 D 50 50 1 1 P

+X G 2 -150 0 210 R 50 50 1 1 P

+X S 3 150 -200 100 U 50 50 1 1 P

+X B 4 250 -150 100 U 50 50 1 1 P

+ENDDRAW

+ENDDEF

+#

+#End Library

diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND.cir b/Examples/CMOS_NAND_Gate/CMOS_NAND.cir
new file mode 100644
index 00000000..92015d1f
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND.cir
@@ -0,0 +1,16 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND\CMOS_NAND.cir

+

+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/23/20 20:21:59

+

+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N

+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

+

+* Sheet Name: /

+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P		

+M4  Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P		

+M2  Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M2-Pad3_ GND eSim_MOS_N		

+M3  Net-_M2-Pad3_ Net-_M3-Pad2_ GND GND eSim_MOS_N		

+U1  Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ PORT		

+v1  Net-_M1-Pad1_ GND DC		

+

+.end

diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND.cir.out b/Examples/CMOS_NAND_Gate/CMOS_NAND.cir.out
new file mode 100644
index 00000000..d1cde907
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND.cir.out
@@ -0,0 +1,19 @@
+* c:\fossee\esim\library\subcircuitlibrary\cmos_nand\cmos_nand.cir

+

+.include NMOS-180nm.lib

+.include PMOS-180nm.lib

+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1

+m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1

+m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ gnd CMOSN W=1u L=0.5u M=1

+m3 net-_m2-pad3_ net-_m3-pad2_ gnd gnd CMOSN W=1u L=0.5u M=1

+* u1  net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ port

+v1 net-_m1-pad1_ gnd  dc 5

+.tran 0e-00 0e-00 0e-00

+

+* Control Statements 

+.control

+run

+print allv > plot_data_v.txt

+print alli > plot_data_i.txt

+.endc

+.end

diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND.pro b/Examples/CMOS_NAND_Gate/CMOS_NAND.pro
new file mode 100644
index 00000000..f63b751e
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND.pro
@@ -0,0 +1,69 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND.sch b/Examples/CMOS_NAND_Gate/CMOS_NAND.sch
new file mode 100644
index 00000000..5e2f6b80
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND.sch
@@ -0,0 +1,254 @@
+EESchema Schematic File Version 2

+LIBS:adc-dac

+LIBS:memory

+LIBS:xilinx

+LIBS:microcontrollers

+LIBS:dsp

+LIBS:microchip

+LIBS:analog_switches

+LIBS:motorola

+LIBS:texas

+LIBS:intel

+LIBS:audio

+LIBS:interface

+LIBS:digital-audio

+LIBS:philips

+LIBS:display

+LIBS:cypress

+LIBS:siliconi

+LIBS:opto

+LIBS:atmel

+LIBS:contrib

+LIBS:power

+LIBS:eSim_Plot

+LIBS:transistors

+LIBS:conn

+LIBS:eSim_User

+LIBS:regul

+LIBS:74xx

+LIBS:cmos4000

+LIBS:eSim_Analog

+LIBS:eSim_Devices

+LIBS:eSim_Digital

+LIBS:eSim_Hybrid

+LIBS:eSim_Miscellaneous

+LIBS:eSim_Power

+LIBS:eSim_Sources

+LIBS:eSim_Subckt

+LIBS:CMOS_NAND-cache

+EELAYER 25 0

+EELAYER END

+$Descr A4 11693 8268

+encoding utf-8

+Sheet 1 1

+Title ""

+Date ""

+Rev ""

+Comp ""

+Comment1 ""

+Comment2 ""

+Comment3 ""

+Comment4 ""

+$EndDescr

+$Comp

+L eSim_MOS_P M1

+U 1 1 5EA19849

+P 5150 2100

+F 0 "M1" H 5100 2150 50  0000 R CNN

+F 1 "eSim_MOS_P" H 5200 2250 50  0000 R CNN

+F 2 "" H 5400 2200 29  0000 C CNN

+F 3 "" H 5200 2100 60  0000 C CNN

+	1    5150 2100

+	1    0    0    -1  

+$EndComp

+$Comp

+L eSim_MOS_P M4

+U 1 1 5EA1984A

+P 5950 2050

+F 0 "M4" H 5900 2100 50  0000 R CNN

+F 1 "eSim_MOS_P" H 6000 2200 50  0000 R CNN

+F 2 "" H 6200 2150 29  0000 C CNN

+F 3 "" H 6000 2050 60  0000 C CNN

+	1    5950 2050

+	-1   0    0    -1  

+$EndComp

+$Comp

+L eSim_MOS_N M2

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+F 0 "M2" H 5350 2650 50  0000 R CNN

+F 1 "eSim_MOS_N" H 5450 2750 50  0000 R CNN

+F 2 "" H 5650 2500 29  0000 C CNN

+F 3 "" H 5450 2600 60  0000 C CNN

+	1    5350 2800

+	1    0    0    -1  

+$EndComp

+$Comp

+L eSim_MOS_N M3

+U 1 1 5EA1984C

+P 5350 3450

+F 0 "M3" H 5350 3300 50  0000 R CNN

+F 1 "eSim_MOS_N" H 5450 3400 50  0000 R CNN

+F 2 "" H 5650 3150 29  0000 C CNN

+F 3 "" H 5450 3250 60  0000 C CNN

+	1    5350 3450

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+$EndComp

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+Wire Wire Line

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+Wire Wire Line

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+Connection ~ 5550 2550

+Wire Wire Line

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+Wire Wire Line

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+Wire Wire Line

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+Wire Wire Line

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+Connection ~ 5450 1800

+Connection ~ 5600 1800

+Wire Wire Line

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+Wire Wire Line

+	7400 1650 5600 1650

+Wire Wire Line

+	7400 4200 7400 3150

+Wire Wire Line

+	5650 4200 7400 4200

+Wire Wire Line

+	4650 3650 5250 3650

+Connection ~ 5650 4200

+Wire Wire Line

+	3950 2400 4650 2400

+Wire Wire Line

+	4650 2400 4650 3000

+Wire Wire Line

+	4650 3000 5250 3000

+Wire Wire Line

+	4950 2100 5000 2100

+Connection ~ 4950 3650

+Wire Wire Line

+	6400 2050 6400 4850

+Wire Wire Line

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+Connection ~ 6050 4200

+Connection ~ 5550 2750

+Wire Wire Line

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+Connection ~ 4950 3000

+Wire Wire Line

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+Wire Wire Line

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+Wire Wire Line

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+Wire Wire Line

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+$Comp

+L PORT U1

+U 1 1 5EA19AC9

+P 3600 2150

+F 0 "U1" H 3650 2250 30  0000 C CNN

+F 1 "PORT" H 3600 2150 30  0000 C CNN

+F 2 "" H 3600 2150 60  0000 C CNN

+F 3 "" H 3600 2150 60  0000 C CNN

+	1    3600 2150

+	1    0    0    -1  

+$EndComp

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+U 2 1 5EA19B16

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+F 2 "" H 4150 3350 60  0000 C CNN

+F 3 "" H 4150 3350 60  0000 C CNN

+	2    4150 3350

+	1    0    0    -1  

+$EndComp

+$Comp

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+U 3 1 5EA19B5B

+P 6250 3000

+F 0 "U1" H 6300 3100 30  0000 C CNN

+F 1 "PORT" H 6250 3000 30  0000 C CNN

+F 2 "" H 6250 3000 60  0000 C CNN

+F 3 "" H 6250 3000 60  0000 C CNN

+	3    6250 3000

+	-1   0    0    1   

+$EndComp

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+Text Notes 7800 2100 0    60   ~ 0

+vcc

+Text Notes 7850 3300 0    60   ~ 0

+gnd

+Text Notes 3250 2150 0    60   ~ 0

+in1\n

+Text Notes 3800 3400 0    60   ~ 0

+in2

+Text Notes 6150 2850 0    60   ~ 0

+out\n

+Wire Wire Line

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+Connection ~ 5650 4100

+$Comp

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+F 1 "DC" H 7350 2650 60  0000 C CNN

+F 2 "R1" H 7250 2700 60  0000 C CNN

+F 3 "" H 7550 2700 60  0000 C CNN

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+$EndComp

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+$Comp

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+F 2 "" H 6750 4300 50  0001 C CNN

+F 3 "" H 6750 4300 50  0001 C CNN

+	1    6750 4300

+	1    0    0    -1  

+$EndComp

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diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND.sub b/Examples/CMOS_NAND_Gate/CMOS_NAND.sub
new file mode 100644
index 00000000..6d2efb0b
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND.sub
@@ -0,0 +1,13 @@
+* Subcircuit CMOS_NAND

+.subckt CMOS_NAND net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ 

+* c:\fossee\esim\library\subcircuitlibrary\cmos_nand\cmos_nand.cir

+.include NMOS-180nm.lib

+.include PMOS-180nm.lib

+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1

+m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad1_ CMOSP W=2.5u L=0.5u M=1

+m2 net-_m1-pad3_ net-_m1-pad2_ net-_m2-pad3_ gnd CMOSN W=1u L=0.5u M=1

+m3 net-_m2-pad3_ net-_m3-pad2_ gnd gnd CMOSN W=1u L=0.5u M=1

+v1 net-_m1-pad1_ gnd  dc 5

+* Control Statements

+

+.ends CMOS_NAND
\ No newline at end of file
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate-cache.lib b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate-cache.lib
new file mode 100644
index 00000000..cb3a7cc3
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate-cache.lib
@@ -0,0 +1,71 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_NAND
+#
+DEF CMOS_NAND X 0 40 Y Y 1 F N
+F0 "X" -100 -150 60 H V C CNN
+F1 "CMOS_NAND" 0 -50 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -350 300 300 300 N
+P 3 0 1 0 -350 300 -350 -400 300 -400 N
+X in1 1 -550 250 200 R 50 50 1 1 I
+X in2 2 -550 -300 200 R 50 50 1 1 I
+X out 3 800 0 279 L 79 79 1 1 I
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir
new file mode 100644
index 00000000..2b7a6c0f
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir
@@ -0,0 +1,16 @@
+* /home/saurabh/eSim-Workspace/CMOS_NAND_Gate/CMOS_NAND_Gate.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Apr 24 09:28:35 2020
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v1  inputA GND pulse		
+v2  inputB GND pulse		
+U2  inputB plot_v1		
+U1  inputA plot_v1		
+U3  out plot_v1		
+X1  inputA inputB out CMOS_NAND		
+
+.end
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir.out b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir.out
new file mode 100644
index 00000000..28714b07
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir.out
@@ -0,0 +1,21 @@
+* /home/saurabh/esim-workspace/cmos_nand_gate/cmos_nand_gate.cir
+
+.include CMOS_NAND.sub
+v1  inputa gnd pulse(0 5 0 0 0 17m 33m)
+v2  inputb gnd pulse(0 5 0 0 0 10m 20m)
+* u2  inputb plot_v1
+* u1  inputa plot_v1
+* u3  out plot_v1
+x1 inputa inputb out CMOS_NAND
+.tran 0.1e-03 100e-03 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(inputb)
+plot v(inputa)
+plot v(out)
+.endc
+.end
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.pro b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.pro
new file mode 100644
index 00000000..f63b751e
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.pro
@@ -0,0 +1,69 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.proj b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.proj
new file mode 100644
index 00000000..02f0a5a8
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.proj
@@ -0,0 +1 @@
+schematicFile CMOS_NAND_Gate.sch
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.sch b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.sch
new file mode 100644
index 00000000..39a1f343
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.sch
@@ -0,0 +1,165 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:CMOS_NAND_Gate-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pulse v1
+U 1 1 5EA263FE
+P 6350 2700
+F 0 "v1" H 6150 2800 60  0000 C CNN
+F 1 "pulse" H 6150 2650 60  0000 C CNN
+F 2 "R1" H 6050 2700 60  0000 C CNN
+F 3 "" H 6350 2700 60  0000 C CNN
+	1    6350 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L pulse v2
+U 1 1 5EA263FF
+P 6800 3950
+F 0 "v2" H 6600 4050 60  0000 C CNN
+F 1 "pulse" H 6600 3900 60  0000 C CNN
+F 2 "R1" H 6500 3950 60  0000 C CNN
+F 3 "" H 6800 3950 60  0000 C CNN
+	1    6800 3950
+	1    0    0    -1  
+$EndComp
+Text GLabel 6100 2250 0    60   Input ~ 0
+inputA
+Text GLabel 6750 3350 0    60   Input ~ 0
+inputB
+$Comp
+L plot_v1 U2
+U 1 1 5EA26400
+P 6800 3550
+F 0 "U2" H 6800 4050 60  0000 C CNN
+F 1 "plot_v1" H 7000 3900 60  0000 C CNN
+F 2 "" H 6800 3550 60  0000 C CNN
+F 3 "" H 6800 3550 60  0000 C CNN
+	1    6800 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 5EA26401
+P 6350 2450
+F 0 "U1" H 6350 2950 60  0000 C CNN
+F 1 "plot_v1" H 6550 2800 60  0000 C CNN
+F 2 "" H 6350 2450 60  0000 C CNN
+F 3 "" H 6350 2450 60  0000 C CNN
+	1    6350 2450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6800 3500 7400 3500
+Wire Wire Line
+	6350 3150 6350 4400
+Connection ~ 6800 4400
+Wire Wire Line
+	6100 2250 6800 2250
+Wire Wire Line
+	6800 2250 6800 2850
+Wire Wire Line
+	6800 2850 7400 2850
+Connection ~ 6350 2250
+Wire Wire Line
+	6750 3350 6800 3350
+Wire Wire Line
+	6800 3350 6800 3500
+$Comp
+L plot_v1 U3
+U 1 1 5EA26402
+P 8900 3200
+F 0 "U3" H 8900 3700 60  0000 C CNN
+F 1 "plot_v1" H 9100 3550 60  0000 C CNN
+F 2 "" H 8900 3200 60  0000 C CNN
+F 3 "" H 8900 3200 60  0000 C CNN
+	1    8900 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7400 2850 7400 2900
+Wire Wire Line
+	7400 3500 7400 3450
+Connection ~ 8050 4400
+$Comp
+L GND #PWR1
+U 1 1 5EA26403
+P 8050 4550
+F 0 "#PWR1" H 8050 4300 50  0001 C CNN
+F 1 "GND" H 8050 4400 50  0000 C CNN
+F 2 "" H 8050 4550 50  0001 C CNN
+F 3 "" H 8050 4550 50  0001 C CNN
+	1    8050 4550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8900 3000 8900 3150
+Wire Wire Line
+	8900 3150 8750 3150
+Text GLabel 8900 3150 3    60   Input ~ 0
+out
+$Comp
+L CMOS_NAND X1
+U 1 1 5EA26404
+P 7950 3150
+F 0 "X1" H 7850 3000 60  0000 C CNN
+F 1 "CMOS_NAND" H 7950 3100 60  0000 C CNN
+F 2 "" H 7950 3150 60  0001 C CNN
+F 3 "" H 7950 3150 60  0001 C CNN
+	1    7950 3150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8050 4400 8050 4550
+Wire Wire Line
+	6350 4400 8050 4400
+$EndSCHEMATC
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate_Previous_Values.xml b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate_Previous_Values.xml
new file mode 100644
index 00000000..101b4146
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.1</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0</field4><field5 name="Fall Time">0</field5><field5 name="Pulse width">17m</field5><field5 name="Period">33m</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0</field4><field5 name="Fall Time">0</field5><field5 name="Pulse width">10m</field5><field5 name="Period">20m</field5></v2></source><model /><devicemodel /><subcircuit><x1><field>/home/saurabh/Desktop/eSim/library/SubcircuitLibrary/CMOS_NAND</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND_Previous_Values.xml b/Examples/CMOS_NAND_Gate/CMOS_NAND_Previous_Values.xml
new file mode 100644
index 00000000..e3478d8c
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/CMOS_NAND_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">5</field1></v1></source><model /><devicemodel><m2><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field>1u</field><field>0.5u</field><field /></m2><m4><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field>2.5u</field><field>0.5u</field><field /></m4><m3><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field>1u</field><field>0.5u</field><field /></m3><m1><field>C:/FOSSEE/eSim/library/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field>2.5u</field><field>0.5u</field><field /></m1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/CMOS_NAND_Gate/NMOS-180nm.lib b/Examples/CMOS_NAND_Gate/NMOS-180nm.lib
new file mode 100644
index 00000000..51e9b119
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/Examples/CMOS_NAND_Gate/PMOS-180nm.lib b/Examples/CMOS_NAND_Gate/PMOS-180nm.lib
new file mode 100644
index 00000000..032b5b95
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/Examples/CMOS_NAND_Gate/analysis b/Examples/CMOS_NAND_Gate/analysis
new file mode 100644
index 00000000..402d01b4
--- /dev/null
+++ b/Examples/CMOS_NAND_Gate/analysis
@@ -0,0 +1 @@
+.tran 0.1e-03 100e-03 0e-00
\ No newline at end of file