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| author | Saurabh Bansode | 2020-04-24 11:51:22 +0530 |
|---|---|---|
| committer | GitHub | 2020-04-24 11:51:22 +0530 |
| commit | a35d497b81023950a6e675536f9cd4bf895983c2 (patch) | |
| tree | 2329f74685827e8e88aae6c4dad1caee797fecbd /Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir | |
| parent | b8097333ca26b380180de0de18a987e0db292927 (diff) | |
| parent | e279dc2d5fa948fc3e9491d0d36dd42f88a8ecad (diff) | |
| download | eSim-a35d497b81023950a6e675536f9cd4bf895983c2.tar.gz eSim-a35d497b81023950a6e675536f9cd4bf895983c2.tar.bz2 eSim-a35d497b81023950a6e675536f9cd4bf895983c2.zip | |
Merge pull request #152 from saurabhb17/master
Subcircuit for CMOS based NAND gate and its supporting example
Diffstat (limited to 'Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir')
| -rw-r--r-- | Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir new file mode 100644 index 00000000..2b7a6c0f --- /dev/null +++ b/Examples/CMOS_NAND_Gate/CMOS_NAND_Gate.cir @@ -0,0 +1,16 @@ +* /home/saurabh/eSim-Workspace/CMOS_NAND_Gate/CMOS_NAND_Gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Apr 24 09:28:35 2020 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +v1 inputA GND pulse +v2 inputB GND pulse +U2 inputB plot_v1 +U1 inputA plot_v1 +U3 out plot_v1 +X1 inputA inputB out CMOS_NAND + +.end |