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authorsaurabhb172020-04-24 11:46:43 +0530
committersaurabhb172020-04-24 11:46:43 +0530
commite279dc2d5fa948fc3e9491d0d36dd42f88a8ecad (patch)
tree2329f74685827e8e88aae6c4dad1caee797fecbd /Examples/CMOS_NAND_Gate/CMOS_NAND.cir
parent239241418842098bbf0f2de67447a96aa96082b0 (diff)
downloadeSim-e279dc2d5fa948fc3e9491d0d36dd42f88a8ecad.tar.gz
eSim-e279dc2d5fa948fc3e9491d0d36dd42f88a8ecad.tar.bz2
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Subcircuit for CMOS based NAND gate and its supporting example
Diffstat (limited to 'Examples/CMOS_NAND_Gate/CMOS_NAND.cir')
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diff --git a/Examples/CMOS_NAND_Gate/CMOS_NAND.cir b/Examples/CMOS_NAND_Gate/CMOS_NAND.cir
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+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_NAND\CMOS_NAND.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 04/23/20 20:21:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P
+M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad1_ eSim_MOS_P
+M2 Net-_M1-Pad3_ Net-_M1-Pad2_ Net-_M2-Pad3_ GND eSim_MOS_N
+M3 Net-_M2-Pad3_ Net-_M3-Pad2_ GND GND eSim_MOS_N
+U1 Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ PORT
+v1 Net-_M1-Pad1_ GND DC
+
+.end