diff options
| author | saurabhb17 | 2020-03-18 20:22:53 +0530 |
|---|---|---|
| committer | GitHub | 2020-03-18 20:22:53 +0530 |
| commit | d3395f5bd22cdd99c7bfa41e5efaf3abf9690bf0 (patch) | |
| tree | affe4c16134e0ca17f6678707a602e06970beade /Examples/Analysis_Of_Digital_IC | |
| parent | d536a4002d05233971a08bbae1907ed9e24e3000 (diff) | |
| parent | 7d7964e7c677244e0fd9fd048a116f62553016ce (diff) | |
| download | eSim-d3395f5bd22cdd99c7bfa41e5efaf3abf9690bf0.tar.gz eSim-d3395f5bd22cdd99c7bfa41e5efaf3abf9690bf0.tar.bz2 eSim-d3395f5bd22cdd99c7bfa41e5efaf3abf9690bf0.zip | |
Merge pull request #140 from saurabhb17/master
Changes in .pro across Examples and Subcircuits
Diffstat (limited to 'Examples/Analysis_Of_Digital_IC')
103 files changed, 133 insertions, 6629 deletions
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib index 6eee1a53..616ce603 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib @@ -27,19 +27,11 @@ X Vdd 14 500 300 200 L 50 50 1 1 I ENDDRAW ENDDEF # -<<<<<<< HEAD -# DC -# -DEF DC v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC" -200 -50 60 H V C CNN -======= # DC-RESCUE-3_Input_NAND_Characteristics # DEF DC-RESCUE-3_Input_NAND_Characteristics v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN F1 "DC-RESCUE-3_Input_NAND_Characteristics" -200 -50 60 H V C CNN ->>>>>>> fellowship2019-python3 F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro index 4d64f7c3..09ee34fe 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro @@ -1,51 +1,4 @@ -<<<<<<< HEAD -update=06/01/19 15:31:12
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../eSim/kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
-======= -update=Wed Mar 11 12:47:11 2020 +update=Wed Mar 18 18:12:01 2020 version=1 last_client=eeschema [general] @@ -90,4 +43,3 @@ LibName9=eSim_Power LibName10=eSim_User LibName11=eSim_Sources LibName12=eSim_Subckt ->>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch index fe74ae2d..cb48a83a 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch @@ -1,8 +1,5 @@ EESchema Schematic File Version 2 -<<<<<<< HEAD -======= LIBS:3_Input_NAND_Characteristics-rescue ->>>>>>> fellowship2019-python3 LIBS:power LIBS:eSim_Analog LIBS:eSim_Devices @@ -11,16 +8,9 @@ LIBS:eSim_Hybrid LIBS:eSim_Miscellaneous LIBS:eSim_Plot LIBS:eSim_Power -<<<<<<< HEAD -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -======= LIBS:eSim_User LIBS:eSim_Sources LIBS:eSim_Subckt ->>>>>>> fellowship2019-python3 LIBS:3_Input_NAND_Characteristics-cache EELAYER 25 0 EELAYER END @@ -92,11 +82,7 @@ F 3 "" H 6800 5750 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -<<<<<<< HEAD -L DC v1 -======= L DC-RESCUE-3_Input_NAND_Characteristics v1 ->>>>>>> fellowship2019-python3 U 1 1 5CF24F1F P 1700 2350 F 0 "v1" H 1500 2450 60 0000 C CNN @@ -107,11 +93,7 @@ F 3 "" H 1700 2350 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v2 -======= L DC-RESCUE-3_Input_NAND_Characteristics v2 ->>>>>>> fellowship2019-python3 U 1 1 5CF24F90 P 1700 2900 F 0 "v2" H 1500 3000 60 0000 C CNN @@ -122,11 +104,7 @@ F 3 "" H 1700 2900 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v3 -======= L DC-RESCUE-3_Input_NAND_Characteristics v3 ->>>>>>> fellowship2019-python3 U 1 1 5CF24FC7 P 1700 3450 F 0 "v3" H 1500 3550 60 0000 C CNN @@ -137,11 +115,7 @@ F 3 "" H 1700 3450 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v4 -======= L DC-RESCUE-3_Input_NAND_Characteristics v4 ->>>>>>> fellowship2019-python3 U 1 1 5CF25001 P 1750 4000 F 0 "v4" H 1550 4100 60 0000 C CNN @@ -152,11 +126,7 @@ F 3 "" H 1750 4000 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v5 -======= L DC-RESCUE-3_Input_NAND_Characteristics v5 ->>>>>>> fellowship2019-python3 U 1 1 5CF25044 P 1750 4550 F 0 "v5" H 1550 4650 60 0000 C CNN @@ -167,11 +137,7 @@ F 3 "" H 1750 4550 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v6 -======= L DC-RESCUE-3_Input_NAND_Characteristics v6 ->>>>>>> fellowship2019-python3 U 1 1 5CF25082 P 1750 5050 F 0 "v6" H 1550 5150 60 0000 C CNN @@ -278,11 +244,7 @@ Wire Wire Line Wire Wire Line 5950 5900 6200 5900 $Comp -<<<<<<< HEAD -L DC v7 -======= L DC-RESCUE-3_Input_NAND_Characteristics v7 ->>>>>>> fellowship2019-python3 U 1 1 5CF25804 P 9250 3250 F 0 "v7" H 9050 3350 60 0000 C CNN @@ -293,11 +255,7 @@ F 3 "" H 9250 3250 60 0000 C CNN 0 -1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v8 -======= L DC-RESCUE-3_Input_NAND_Characteristics v8 ->>>>>>> fellowship2019-python3 U 1 1 5CF2580A P 9250 3800 F 0 "v8" H 9050 3900 60 0000 C CNN @@ -308,11 +266,7 @@ F 3 "" H 9250 3800 60 0000 C CNN 0 -1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v9 -======= L DC-RESCUE-3_Input_NAND_Characteristics v9 ->>>>>>> fellowship2019-python3 U 1 1 5CF25810 P 9250 4300 F 0 "v9" H 9050 4400 60 0000 C CNN diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~HEAD b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib index 0a3ccf7f..0a3ccf7f 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~HEAD +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~fellowship2019-python3 deleted file mode 100644 index af058641..00000000 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~fellowship2019-python3 +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~HEAD b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir index 15f8954d..15f8954d 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~HEAD +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~HEAD b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out index e3c96645..e3c96645 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~HEAD +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~fellowship2019-python3 deleted file mode 100644 index d7cf79a0..00000000 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~fellowship2019-python3 +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~fellowship2019-python3 deleted file mode 100644 index ba296cf0..00000000 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~fellowship2019-python3 +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro index 94cd9bd4..c5f4a39f 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~fellowship2019-python3 +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro @@ -1,4 +1,4 @@ -update=05/31/19 16:37:06 +update=Wed Mar 18 19:43:53 2020 version=1 last_client=eeschema [general] diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro~fellowship2019-python3 deleted file mode 100644 index 2c9ac554..00000000 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro~fellowship2019-python3 +++ /dev/null @@ -1,58 +0,0 @@ -update=03/26/19 18:40:23 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=texas -LibName3=intel -LibName4=audio -LibName5=interface -LibName6=digital-audio -LibName7=philips -LibName8=display -LibName9=cypress -LibName10=siliconi -LibName11=opto -LibName12=atmel -LibName13=contrib -LibName14=valves -LibName15=eSim_Analog -LibName16=eSim_Devices -LibName17=eSim_Digital -LibName18=eSim_Hybrid -LibName19=eSim_Miscellaneous -LibName20=eSim_Plot -LibName21=eSim_Power -LibName22=eSim_PSpice -LibName23=eSim_Sources -LibName24=eSim_Subckt -LibName25=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~HEAD b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch index c853bf49..c853bf49 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~HEAD +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~fellowship2019-python3 deleted file mode 100644 index 86be0215..00000000 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~fellowship2019-python3 +++ /dev/null @@ -1,121 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~HEAD b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub index b949ae4f..b949ae4f 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~HEAD +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~fellowship2019-python3 deleted file mode 100644 index 3d9120bb..00000000 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~fellowship2019-python3 +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml~HEAD b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml index abc5faaa..abc5faaa 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml~HEAD +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/analysis b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis index 660a46cc..660a46cc 100644 --- a/Examples/Analysis_Of_Digital_IC/4028_test/analysis +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_i.txt b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_i.txt index 4112f610..1b24c22f 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_i.txt +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_i.txt @@ -1,5 +1,5 @@ * c:\users\malli\esim-workspace\4023_test\4023_test.cir - Transient Analysis Fri Jan 31 12:34:52 2020 + Transient Analysis Wed Mar 18 19:44:14 2020 -------------------------------------------------------------------------------- Index time a4#branch_1_0 a4#branch_1_1 a4#branch_1_2 -------------------------------------------------------------------------------- @@ -67,7 +67,7 @@ Index time a4#branch_1_0 a4#branch_1_1 a4#branch_1_2 58 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 * c:\users\malli\esim-workspace\4023_test\4023_test.cir - Transient Analysis Fri Jan 31 12:34:52 2020 + Transient Analysis Wed Mar 18 19:44:14 2020 -------------------------------------------------------------------------------- Index time v1#branch v2#branch v3#branch -------------------------------------------------------------------------------- @@ -135,7 +135,7 @@ Index time v1#branch v2#branch v3#branch 58 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 * c:\users\malli\esim-workspace\4023_test\4023_test.cir - Transient Analysis Fri Jan 31 12:34:52 2020 + Transient Analysis Wed Mar 18 19:44:14 2020 -------------------------------------------------------------------------------- Index time v4#branch v5#branch v6#branch -------------------------------------------------------------------------------- @@ -203,7 +203,7 @@ Index time v4#branch v5#branch v6#branch 58 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 * c:\users\malli\esim-workspace\4023_test\4023_test.cir - Transient Analysis Fri Jan 31 12:34:52 2020 + Transient Analysis Wed Mar 18 19:44:14 2020 -------------------------------------------------------------------------------- Index time v7#branch v8#branch v9#branch -------------------------------------------------------------------------------- diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_v.txt b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_v.txt index 09e3e5bb..109a3ed3 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_v.txt +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_v.txt @@ -1,5 +1,5 @@ * c:\users\malli\esim-workspace\4023_test\4023_test.cir - Transient Analysis Fri Jan 31 12:34:52 2020 + Transient Analysis Wed Mar 18 19:44:14 2020 -------------------------------------------------------------------------------- Index time a1 a2 a3 -------------------------------------------------------------------------------- @@ -67,7 +67,7 @@ Index time a1 a2 a3 58 1.000000e-01 0.000000e+00 5.000000e+00 5.000000e+00 * c:\users\malli\esim-workspace\4023_test\4023_test.cir - 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-======= EESchema Schematic File Version 2 LIBS:4012_test-rescue LIBS:power @@ -1002,4 +499,3 @@ Wire Wire Line 4800 1850 4800 2050 Connection ~ 4800 2050 $EndSCHEMATC ->>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4012_test/analysis index 660a46cc..660a46cc 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis~fellowship2019-python3 +++ b/Examples/Analysis_Of_Digital_IC/4012_test/analysis diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/analysis~HEAD b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~HEAD deleted file mode 100644 index 660a46cc..00000000 --- a/Examples/Analysis_Of_Digital_IC/4012_test/analysis~HEAD +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/analysis~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~fellowship2019-python3 deleted file mode 100644 index 660a46cc..00000000 --- a/Examples/Analysis_Of_Digital_IC/4012_test/analysis~fellowship2019-python3 +++ /dev/null @@ -1 +0,0 @@ -.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib index 0a3ccf7f..0a3ccf7f 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3 deleted file mode 100644 index af058641..00000000 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3 +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir index 15f8954d..15f8954d 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out index e3c96645..e3c96645 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3 deleted file mode 100644 index d7cf79a0..00000000 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3 +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3 deleted file mode 100644 index ba296cf0..00000000 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3 +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - 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-[cvpcb]
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-[eeschema/libraries]
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-LibName2=eSim_Devices
-LibName3=eSim_Digital
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-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
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diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3 deleted file mode 100644 index 2c9ac554..00000000 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3 +++ /dev/null @@ -1,58 +0,0 @@ -update=03/26/19 18:40:23 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=texas -LibName3=intel -LibName4=audio -LibName5=interface -LibName6=digital-audio -LibName7=philips -LibName8=display -LibName9=cypress -LibName10=siliconi -LibName11=opto -LibName12=atmel -LibName13=contrib -LibName14=valves -LibName15=eSim_Analog -LibName16=eSim_Devices -LibName17=eSim_Digital -LibName18=eSim_Hybrid -LibName19=eSim_Miscellaneous -LibName20=eSim_Plot -LibName21=eSim_Power -LibName22=eSim_PSpice -LibName23=eSim_Sources -LibName24=eSim_Subckt -LibName25=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~HEAD b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch index c853bf49..c853bf49 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3 deleted file mode 100644 index 86be0215..00000000 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3 +++ /dev/null @@ -1,121 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 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-.ends 3_and
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml index abc5faaa..abc5faaa 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml~fellowship2019-python3 +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3 deleted file mode 100644 index abc5faaa..00000000 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3 +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib index 9fb7bb13..4ef5b7f4 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib @@ -1,127 +1,3 @@ -<<<<<<< HEAD -EESchema-LIBRARY Version 2.3
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-======= EESchema-LIBRARY Version 2.3 #encoding utf-8 # @@ -244,4 +120,3 @@ ENDDRAW ENDDEF # #End Library ->>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro index ec355936..d2059e07 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro @@ -1,51 +1,4 @@ -<<<<<<< HEAD -update=06/01/19 15:31:12
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-$Comp
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-Text GLabel 8300 3500 0 60 Input ~ 0
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-$EndSCHEMATC
-======= EESchema Schematic File Version 2 LIBS:4023_test-rescue LIBS:power @@ -1151,4 +574,3 @@ Wire Wire Line 3050 5150 3050 5000 Connection ~ 3050 5000 $EndSCHEMATC ->>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028-cache.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028-cache.lib deleted file mode 100644 index 4ba19fb8..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028-cache.lib +++ /dev/null @@ -1,94 +0,0 @@ -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_and
-#
-DEF d_and U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_and" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
-A 150 49 100 6 900 0 1 0 N 250 50 150 150
-P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
-X IN1 1 -450 100 200 R 50 50 1 1 I
-X IN2 2 -450 0 200 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# d_inverter
-#
-DEF d_inverter U 0 40 Y Y 1 F N
-F0 "U" 0 -100 60 H V C CNN
-F1 "d_inverter" 0 150 60 H V C CNN
-F2 "" 50 -50 60 H V C CNN
-F3 "" 50 -50 60 H V C CNN
-DRAW
-P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
-X ~ 1 -300 0 200 R 50 50 1 1 I
-X ~ 2 300 0 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-# d_nor
-#
-DEF d_nor U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_nor" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O I
-ENDDRAW
-ENDDEF
-#
-#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir deleted file mode 100644 index c13da65d..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir +++ /dev/null @@ -1,32 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U9 Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor
-U10 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
-U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor
-U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor
-U6 Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor
-U7 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor
-U8 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor
-U2 Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter
-U3 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter
-U4 Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter
-U5 Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter
-U15 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and
-U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and
-U17 Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and
-U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and
-U19 Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and
-U20 Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and
-U21 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and
-U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and
-U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT
-U22 Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and
-
-.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir.out b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir.out deleted file mode 100644 index 93e14b93..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir.out +++ /dev/null @@ -1,96 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
-
-* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
-* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
-* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
-* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
-* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
-* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
-* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
-* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter
-* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter
-* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter
-* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter
-* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
-* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
-* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
-* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
-* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
-* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
-* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
-* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
-* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
-* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
-a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
-a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
-a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
-a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
-a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
-a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
-a8 net-_u1-pad10_ net-_u11-pad1_ u2
-a9 net-_u1-pad13_ net-_u10-pad2_ u3
-a10 net-_u1-pad12_ net-_u4-pad2_ u4
-a11 net-_u1-pad11_ net-_u5-pad2_ u5
-a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
-a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
-a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
-a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
-a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
-a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
-a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
-a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
-a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
-a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.sch b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sch deleted file mode 100644 index a487c693..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028.sch +++ /dev/null @@ -1,628 +0,0 @@ -EESchema Schematic File Version 2
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- 12 1200 4150
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-F 3 "" H 8000 1800 60 0000 C CNN
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-F 3 "" H 8000 2300 60 0000 C CNN
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-F 3 "" H 8000 2750 60 0000 C CNN
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Connection ~ 5900 5550
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-F 1 "PORT" H 7950 5750 30 0000 C CNN
-F 2 "" H 7950 5750 60 0000 C CNN
-F 3 "" H 7950 5750 60 0000 C CNN
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-F 1 "PORT" H 9550 4800 30 0000 C CNN
-F 2 "" H 9550 4800 60 0000 C CNN
-F 3 "" H 9550 4800 60 0000 C CNN
- 8 9550 4800
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-L PORT U1
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-F 1 "PORT" H 9550 5250 30 0000 C CNN
-F 2 "" H 9550 5250 60 0000 C CNN
-F 3 "" H 9550 5250 60 0000 C CNN
- 16 9550 5250
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diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.sub b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sub deleted file mode 100644 index 5f9f3cf8..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028.sub +++ /dev/null @@ -1,90 +0,0 @@ -* Subcircuit 4028
-.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ?
-* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
-* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
-* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
-* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
-* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
-* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
-* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
-* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
-* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter
-* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter
-* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter
-* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter
-* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
-* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
-* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
-* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
-* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
-* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
-* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
-* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
-* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
-* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
-a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
-a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
-a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
-a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
-a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
-a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
-a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
-a8 net-_u1-pad10_ net-_u11-pad1_ u2
-a9 net-_u1-pad13_ net-_u10-pad2_ u3
-a10 net-_u1-pad12_ net-_u4-pad2_ u4
-a11 net-_u1-pad11_ net-_u5-pad2_ u5
-a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
-a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
-a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
-a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
-a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
-a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
-a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
-a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
-a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
-a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_nor, NgSpice Name: d_nor
-.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
-.ends 4028
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4028_test/4028_Previous_Values.xml deleted file mode 100644 index 189fb200..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib deleted file mode 100644 index cd34331d..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib +++ /dev/null @@ -1,307 +0,0 @@ -<<<<<<< HEAD -EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 4028
-#
-DEF 4028 X 0 40 Y Y 1 F N
-F0 "X" 0 -100 60 H V C CNN
-F1 "4028" 0 50 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -300 450 300 -450 0 1 0 N
-X Q4 1 -500 350 200 R 50 50 1 1 O
-X Q2 2 -500 250 200 R 50 50 1 1 O
-X Q0 3 -500 150 200 R 50 50 1 1 O
-X Q7 4 -500 50 200 R 50 50 1 1 O
-X Q9 5 -500 -50 200 R 50 50 1 1 O
-X Q5 6 -500 -150 200 R 50 50 1 1 O
-X Q6 7 -500 -250 200 R 50 50 1 1 O
-X Vss 8 -500 -350 200 R 50 50 1 1 I
-X Q8 9 500 -350 200 L 50 50 1 1 O
-X A0 10 500 -250 200 L 50 50 1 1 I
-X A3 11 500 -150 200 L 50 50 1 1 I
-X A2 12 500 -50 200 L 50 50 1 1 I
-X A1 13 500 50 200 L 50 50 1 1 I
-X Q1 14 500 150 200 L 50 50 1 1 O
-X Q3 15 500 250 200 L 50 50 1 1 O
-X Vdd 16 500 350 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# DC
-#
-DEF DC v 0 40 Y Y 1 F N
-F0 "v" -200 100 60 H V C CNN
-F1 "DC" -200 -50 60 H V C CNN
-F2 "R1" -300 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-$FPLIST
- 1_pin
-$ENDFPLIST
-DRAW
-C 0 0 150 0 1 0 N
-X + 1 0 450 300 D 50 50 1 1 P
-X - 2 0 -450 300 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# PWR_FLAG
-#
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 95 50 H I C CNN
-F1 "PWR_FLAG" 0 180 50 H V C CNN
-F2 "" 0 0 50 H V C CNN
-F3 "" 0 0 50 H V C CNN
-DRAW
-X pwr 1 0 0 0 U 20 20 0 0 w
-P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
-ENDDRAW
-ENDDEF
-#
-# adc_bridge_4
-#
-DEF adc_bridge_4 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "adc_bridge_4" 0 300 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -350 350 350 -200 0 1 0 N
-X IN1 1 -550 200 200 R 50 50 1 1 I
-X IN2 2 -550 100 200 R 50 50 1 1 I
-X IN3 3 -550 0 200 R 50 50 1 1 I
-X IN4 4 -550 -100 200 R 50 50 1 1 I
-X OUT1 5 550 200 200 L 50 50 1 1 O
-X OUT2 6 550 100 200 L 50 50 1 1 O
-X OUT3 7 550 0 200 L 50 50 1 1 O
-X OUT4 8 550 -100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# dac_bridge_2
-#
-DEF dac_bridge_2 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "dac_bridge_2" 50 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -250 200 350 -100 0 1 0 N
-X IN1 1 -450 50 200 R 50 50 1 1 I
-X IN2 2 -450 -50 200 R 50 50 1 1 I
-X OUT1 3 550 50 200 L 50 50 1 1 O
-X OUT4 4 550 -50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# dac_bridge_8
-#
-DEF dac_bridge_8 U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "dac_bridge_8" 0 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -400 200 350 -700 0 1 0 N
-X IN1 1 -600 50 200 R 50 50 1 1 I
-X IN2 2 -600 -50 200 R 50 50 1 1 I
-X IN3 3 -600 -150 200 R 50 50 1 1 I
-X IN4 4 -600 -250 200 R 50 50 1 1 I
-X IN5 5 -600 -350 200 R 50 50 1 1 I
-X IN6 6 -600 -450 200 R 50 50 1 1 I
-X IN7 7 -600 -550 200 R 50 50 1 1 I
-X IN8 8 -600 -650 200 R 50 50 1 1 I
-X OUT1 9 550 50 200 L 50 50 1 1 O
-X OUT2 10 550 -50 200 L 50 50 1 1 O
-X OUT3 11 550 -150 200 L 50 50 1 1 O
-X OUT4 12 550 -250 200 L 50 50 1 1 O
-X OUT5 13 550 -350 200 L 50 50 1 1 O
-X OUT6 14 550 -450 200 L 50 50 1 1 O
-X OUT7 15 550 -550 200 L 50 50 1 1 O
-X OUT8 16 550 -650 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# eSim_GND
-#
-DEF eSim_GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "eSim_GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# plot_v1
-#
-DEF plot_v1 U 0 40 Y Y 1 F N
-F0 "U" 0 500 60 H V C CNN
-F1 "plot_v1" 200 350 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 0 500 100 0 1 0 N
-X ~ ~ 0 200 200 U 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
-======= -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 4028 -# -DEF 4028 X 0 40 Y Y 1 F N -F0 "X" 0 -100 60 H V C CNN -F1 "4028" 0 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -300 450 300 -450 0 1 0 N -X Q4 1 -500 350 200 R 50 50 1 1 O -X Q2 2 -500 250 200 R 50 50 1 1 O -X Q0 3 -500 150 200 R 50 50 1 1 O -X Q7 4 -500 50 200 R 50 50 1 1 O -X Q9 5 -500 -50 200 R 50 50 1 1 O -X Q5 6 -500 -150 200 R 50 50 1 1 O -X Q6 7 -500 -250 200 R 50 50 1 1 O -X Vss 8 -500 -350 200 R 50 50 1 1 I -X Q8 9 500 -350 200 L 50 50 1 1 O -X A0 10 500 -250 200 L 50 50 1 1 I -X A3 11 500 -150 200 L 50 50 1 1 I -X A2 12 500 -50 200 L 50 50 1 1 I -X A1 13 500 50 200 L 50 50 1 1 I -X Q1 14 500 150 200 L 50 50 1 1 O -X Q3 15 500 250 200 L 50 50 1 1 O -X Vdd 16 500 350 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# DC-RESCUE-4028_test -# -DEF DC-RESCUE-4028_test v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC-RESCUE-4028_test" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -# PWR_FLAG -# -DEF PWR_FLAG #FLG 0 0 N N 1 F P -F0 "#FLG" 0 75 50 H I C CNN -F1 "PWR_FLAG" 0 150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -X pwr 1 0 0 0 U 50 50 0 0 w -P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N -ENDDRAW -ENDDEF -# -# adc_bridge_4 -# -DEF adc_bridge_4 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "adc_bridge_4" 0 300 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -350 350 350 -200 0 1 0 N -X IN1 1 -550 200 200 R 50 50 1 1 I -X IN2 2 -550 100 200 R 50 50 1 1 I -X IN3 3 -550 0 200 R 50 50 1 1 I -X IN4 4 -550 -100 200 R 50 50 1 1 I -X OUT1 5 550 200 200 L 50 50 1 1 O -X OUT2 6 550 100 200 L 50 50 1 1 O -X OUT3 7 550 0 200 L 50 50 1 1 O -X OUT4 8 550 -100 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# dac_bridge_2 -# -DEF dac_bridge_2 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "dac_bridge_2" 50 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -250 200 350 -100 0 1 0 N -X IN1 1 -450 50 200 R 50 50 1 1 I -X IN2 2 -450 -50 200 R 50 50 1 1 I -X OUT1 3 550 50 200 L 50 50 1 1 O -X OUT4 4 550 -50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# dac_bridge_8 -# -DEF dac_bridge_8 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "dac_bridge_8" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -400 200 350 -700 0 1 0 N -X IN1 1 -600 50 200 R 50 50 1 1 I -X IN2 2 -600 -50 200 R 50 50 1 1 I -X IN3 3 -600 -150 200 R 50 50 1 1 I -X IN4 4 -600 -250 200 R 50 50 1 1 I -X IN5 5 -600 -350 200 R 50 50 1 1 I -X IN6 6 -600 -450 200 R 50 50 1 1 I -X IN7 7 -600 -550 200 R 50 50 1 1 I -X IN8 8 -600 -650 200 R 50 50 1 1 I -X OUT1 9 550 50 200 L 50 50 1 1 O -X OUT2 10 550 -50 200 L 50 50 1 1 O -X OUT3 11 550 -150 200 L 50 50 1 1 O -X OUT4 12 550 -250 200 L 50 50 1 1 O -X OUT5 13 550 -350 200 L 50 50 1 1 O -X OUT6 14 550 -450 200 L 50 50 1 1 O -X OUT7 15 550 -550 200 L 50 50 1 1 O -X OUT8 16 550 -650 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# eSim_GND -# -DEF eSim_GND #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -250 50 H I C CNN -F1 "eSim_GND" 0 -150 50 H V C CNN -F2 "" 0 0 50 H I C CNN -F3 "" 0 0 50 H I C CNN -DRAW -P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N -X GND 1 0 0 0 D 50 50 1 1 W N -ENDDRAW -ENDDEF -# -# plot_v1 -# -DEF plot_v1 U 0 40 Y Y 1 F N -F0 "U" 0 500 60 H V C CNN -F1 "plot_v1" 200 350 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -C 0 500 100 0 1 0 N -X ~ ~ 0 200 200 U 50 50 1 1 I -ENDDRAW -ENDDEF -# -#End Library ->>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-rescue.lib deleted file mode 100644 index 214f1f4c..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-rescue.lib +++ /dev/null @@ -1,21 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# DC-RESCUE-4028_test -# -DEF DC-RESCUE-4028_test v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC-RESCUE-4028_test" -200 -50 60 H V C CNN -F2 "R1" -300 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -$FPLIST - 1_pin -$ENDFPLIST -DRAW -C 0 0 150 0 1 0 N -X + 1 0 450 300 D 50 50 1 1 P -X - 2 0 -450 300 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir deleted file mode 100644 index 66fe8e03..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir +++ /dev/null @@ -1,32 +0,0 @@ -* C:\Users\malli\eSim-Workspace\4028_test\4028_test.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 16:27:32
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U11-Pad5_ Net-_U11-Pad3_ Net-_U11-Pad1_ Net-_U11-Pad8_ Net-_U12-Pad2_ Net-_U11-Pad6_ Net-_U11-Pad7_ ? Net-_U12-Pad1_ Net-_U13-Pad5_ Net-_U13-Pad8_ Net-_U13-Pad7_ Net-_U13-Pad6_ Net-_U11-Pad2_ Net-_U11-Pad4_ ? 4028
-U13 a0 a1 a2 a3 Net-_U13-Pad5_ Net-_U13-Pad6_ Net-_U13-Pad7_ Net-_U13-Pad8_ adc_bridge_4
-U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ q0 q1 q2 q3 q4 q5 q6 q7 dac_bridge_8
-U12 Net-_U12-Pad1_ Net-_U12-Pad2_ q8 q9 dac_bridge_2
-v2 a1 GND DC
-v1 a0 GND DC
-v3 a2 GND DC
-v4 a3 GND DC
-U2 q1 plot_v1
-U3 q2 plot_v1
-U4 q3 plot_v1
-U5 q4 plot_v1
-U6 q5 plot_v1
-U7 q6 plot_v1
-U8 q7 plot_v1
-U9 q8 plot_v1
-U10 q9 plot_v1
-U1 q0 plot_v1
-U16 a1 plot_v1
-U15 a0 plot_v1
-U14 a3 plot_v1
-U17 a2 plot_v1
-
-.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out deleted file mode 100644 index 30ea7914..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out +++ /dev/null @@ -1,57 +0,0 @@ -* c:\users\malli\esim-workspace\4028_test\4028_test.cir
-
-.include 4028.sub
-x1 net-_u11-pad5_ net-_u11-pad3_ net-_u11-pad1_ net-_u11-pad8_ net-_u12-pad2_ net-_u11-pad6_ net-_u11-pad7_ ? net-_u12-pad1_ net-_u13-pad5_ net-_u13-pad8_ net-_u13-pad7_ net-_u13-pad6_ net-_u11-pad2_ net-_u11-pad4_ ? 4028
-* u13 a0 a1 a2 a3 net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ adc_bridge_4
-* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ q0 q1 q2 q3 q4 q5 q6 q7 dac_bridge_8
-* u12 net-_u12-pad1_ net-_u12-pad2_ q8 q9 dac_bridge_2
-v2 a1 gnd dc 0
-v1 a0 gnd dc 5
-v3 a2 gnd dc 5
-v4 a3 gnd dc 0
-* u2 q1 plot_v1
-* u3 q2 plot_v1
-* u4 q3 plot_v1
-* u5 q4 plot_v1
-* u6 q5 plot_v1
-* u7 q6 plot_v1
-* u8 q7 plot_v1
-* u9 q8 plot_v1
-* u10 q9 plot_v1
-* u1 q0 plot_v1
-* u16 a1 plot_v1
-* u15 a0 plot_v1
-* u14 a3 plot_v1
-* u17 a2 plot_v1
-a1 [a0 a1 a2 a3 ] [net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ ] u13
-a2 [net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ ] [q0 q1 q2 q3 q4 q5 q6 q7 ] u11
-a3 [net-_u12-pad1_ net-_u12-pad2_ ] [q8 q9 ] u12
-* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
-.model u13 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
-* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
-.model u11 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
-* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
-.model u12 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
-.tran 10e-03 100e-03 0e-03
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-plot v(q1)
-plot v(q2)
-plot v(q3)
-plot v(q4)
-plot v(q5)
-plot v(q6)
-plot v(q7)
-plot v(q8)
-plot v(q9)
-plot v(q0)
-plot v(a1)
-plot v(a0)
-plot v(a3)
-plot v(a2)
-.endc
-.end
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-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
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-[eeschema]
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-[eeschema/libraries]
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-LibName2=eSim_Analog
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-LibName4=eSim_Digital
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-======= -update=Wed Mar 11 12:51:14 2020 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir=../../eSim/kicadSchematicLibrary -[eeschema/libraries] -LibName1=4028_test-rescue -LibName2=power -LibName3=eSim_Analog -LibName4=eSim_Devices -LibName5=eSim_Digital -LibName6=eSim_Hybrid -LibName7=eSim_Miscellaneous -LibName8=eSim_Plot -LibName9=eSim_Power -LibName10=eSim_Sources -LibName11=eSim_Subckt -LibName12=eSim_User ->>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.proj b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.proj deleted file mode 100644 index fa2ce0cd..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.proj +++ /dev/null @@ -1 +0,0 @@ -schematicFile 4028_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch deleted file mode 100644 index ba22945c..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch +++ /dev/null @@ -1,1107 +0,0 @@ -<<<<<<< HEAD -EESchema Schematic File Version 2
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-======= -EESchema Schematic File Version 2 -LIBS:4028_test-rescue -LIBS:power -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -LIBS:4028_test-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 4028 X1 -U 1 1 5CF25569 -P 5600 4300 -F 0 "X1" H 5600 4200 60 0000 C CNN -F 1 "4028" H 5600 4350 60 0000 C CNN -F 2 "" H 5600 4300 60 0000 C CNN -F 3 "" H 5600 4300 60 0000 C CNN - 1 5600 4300 - 1 0 0 -1 -$EndComp -$Comp -L adc_bridge_4 U13 -U 1 1 5CF25781 -P 7300 4350 -F 0 "U13" H 7300 4350 60 0000 C CNN -F 1 "adc_bridge_4" H 7300 4650 60 0000 C CNN -F 2 "" H 7300 4350 60 0000 C CNN -F 3 "" H 7300 4350 60 0000 C CNN - 1 7300 4350 - -1 0 0 -1 -$EndComp -$Comp -L dac_bridge_8 U11 -U 1 1 5CF257F0 -P 3750 3950 -F 0 "U11" H 3750 3950 60 0000 C CNN -F 1 "dac_bridge_8" H 3750 4100 60 0000 C CNN -F 2 "" H 3750 3950 60 0000 C CNN -F 3 "" H 3750 3950 60 0000 C CNN - 1 3750 3950 - -1 0 0 -1 -$EndComp -$Comp -L dac_bridge_2 U12 -U 1 1 5CF258CD -P 3800 5050 -F 0 "U12" H 3800 5050 60 0000 C CNN -F 1 "dac_bridge_2" H 3850 5200 60 0000 C CNN -F 2 "" H 3800 5050 60 0000 C CNN -F 3 "" H 3800 5050 60 0000 C CNN - 1 3800 5050 - -1 0 0 -1 -$EndComp -$Comp -L DC-RESCUE-4028_test v2 -U 1 1 5CF25946 -P 9400 3950 -F 0 "v2" H 9200 4050 60 0000 C CNN -F 1 "DC" H 9200 3900 60 0000 C CNN -F 2 "R1" H 9100 3950 60 0000 C CNN -F 3 "" H 9400 3950 60 0000 C CNN - 1 9400 3950 - 0 -1 -1 0 -$EndComp -$Comp -L DC-RESCUE-4028_test v1 -U 1 1 5CF259A4 -P 9400 3400 -F 0 "v1" H 9200 3500 60 0000 C CNN -F 1 "DC" H 9200 3350 60 0000 C CNN -F 2 "R1" H 9100 3400 60 0000 C CNN -F 3 "" H 9400 3400 60 0000 C CNN - 1 9400 3400 - 0 -1 -1 0 -$EndComp -$Comp -L DC-RESCUE-4028_test v3 -U 1 1 5CF259F8 -P 9400 4500 -F 0 "v3" H 9200 4600 60 0000 C CNN -F 1 "DC" H 9200 4450 60 0000 C CNN -F 2 "R1" H 9100 4500 60 0000 C CNN -F 3 "" H 9400 4500 60 0000 C CNN - 1 9400 4500 - 0 -1 -1 0 -$EndComp -$Comp -L DC-RESCUE-4028_test v4 -U 1 1 5CF25A37 -P 9450 5000 -F 0 "v4" H 9250 5100 60 0000 C CNN -F 1 "DC" H 9250 4950 60 0000 C CNN -F 2 "R1" H 9150 5000 60 0000 C CNN -F 3 "" H 9450 5000 60 0000 C CNN - 1 9450 5000 - 0 -1 -1 0 -$EndComp -$Comp -L eSim_GND #PWR01 -U 1 1 5CF25C11 -P 10200 4450 -F 0 "#PWR01" H 10200 4200 50 0001 C CNN -F 1 "eSim_GND" H 10200 4300 50 0000 C CNN -F 2 "" H 10200 4450 50 0001 C CNN -F 3 "" H 10200 4450 50 0001 C CNN - 1 10200 4450 - 1 0 0 -1 -$EndComp -$Comp -L PWR_FLAG #FLG02 -U 1 1 5CF25C75 -P 10200 4100 -F 0 "#FLG02" H 10200 4195 50 0001 C CNN -F 1 "PWR_FLAG" H 10200 4280 50 0000 C CNN -F 2 "" H 10200 4100 50 0000 C CNN -F 3 "" H 10200 4100 50 0000 C CNN - 1 10200 4100 - 1 0 0 -1 -$EndComp -Wire Wire Line - 8950 3400 8500 3400 -Wire Wire Line - 8500 3400 8500 4150 -Wire Wire Line - 8500 4150 7850 4150 -Wire Wire Line - 8600 4250 7850 4250 -Wire Wire Line - 8600 3050 8600 4250 -Wire Wire Line - 8600 3950 8950 3950 -Wire Wire Line - 8950 4500 8500 4500 -Wire Wire Line - 8500 4500 8500 4350 -Wire Wire Line - 8500 4350 7850 4350 -Wire Wire Line - 7850 4450 8200 4450 -Wire Wire Line - 8200 4450 8200 5000 -Wire Wire Line - 8200 5000 9000 5000 -Wire Wire Line - 9900 3400 9900 5000 -Wire Wire Line - 9900 3400 9850 3400 -Wire Wire Line - 9850 3950 9900 3950 -Connection ~ 9900 3950 -Wire Wire Line - 9850 4500 9900 4500 -Connection ~ 9900 4500 -Wire Wire Line - 9900 4200 10200 4200 -Wire Wire Line - 10200 4100 10200 4450 -Connection ~ 9900 4200 -Connection ~ 10200 4200 -Wire Wire Line - 5100 4150 4750 4150 -Wire Wire Line - 4750 4150 4750 3900 -Wire Wire Line - 4750 3900 4350 3900 -Wire Wire Line - 6100 4150 6200 4150 -Wire Wire Line - 6200 4150 6200 3700 -Wire Wire Line - 6200 3700 4400 3700 -Wire Wire Line - 4400 3700 4400 4000 -Wire Wire Line - 4400 4000 4350 4000 -Wire Wire Line - 4350 4050 5100 4050 -Wire Wire Line - 4350 4050 4350 4100 -Wire Wire Line - 6100 4050 6250 4050 -Wire Wire Line - 6250 4050 6250 3650 -Wire Wire Line - 6250 3650 4450 3650 -Wire Wire Line - 4450 3650 4450 4200 -Wire Wire Line - 4450 4200 4350 4200 -Wire Wire Line - 5100 3950 4500 3950 -Wire Wire Line - 4500 3950 4500 4300 -Wire Wire Line - 4500 4300 4350 4300 -Wire Wire Line - 5100 4450 4500 4450 -Wire Wire Line - 4500 4450 4500 4400 -Wire Wire Line - 4500 4400 4350 4400 -Wire Wire Line - 5100 4550 4450 4550 -Wire Wire Line - 4450 4550 4450 4500 -Wire Wire Line - 4450 4500 4350 4500 -Wire Wire Line - 4550 4250 5100 4250 -Wire Wire Line - 4550 4250 4550 4600 -Wire Wire Line - 4550 4600 4350 4600 -Wire Wire Line - 6100 4650 6150 4650 -Wire Wire Line - 6150 4650 6150 5000 -Wire Wire Line - 6150 5000 4250 5000 -Wire Wire Line - 4250 5100 4650 5100 -Wire Wire Line - 4650 5100 4650 4350 -Wire Wire Line - 4650 4350 5100 4350 -Wire Wire Line - 6100 4550 6350 4550 -Wire Wire Line - 6350 4550 6350 4150 -Wire Wire Line - 6350 4150 6750 4150 -Wire Wire Line - 6100 4250 6750 4250 -Wire Wire Line - 6100 4350 6750 4350 -Wire Wire Line - 6750 4450 6100 4450 -$Comp -L plot_v1 U2 -U 1 1 5CF261D1 -P 1700 2550 -F 0 "U2" H 1700 3050 60 0000 C CNN -F 1 "plot_v1" H 1900 2900 60 0000 C CNN -F 2 "" H 1700 2550 60 0000 C CNN -F 3 "" H 1700 2550 60 0000 C CNN - 1 1700 2550 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U3 -U 1 1 5CF262A9 -P 1700 3050 -F 0 "U3" H 1700 3550 60 0000 C CNN -F 1 "plot_v1" H 1900 3400 60 0000 C CNN -F 2 "" H 1700 3050 60 0000 C CNN -F 3 "" H 1700 3050 60 0000 C CNN - 1 1700 3050 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U4 -U 1 1 5CF262EF -P 1700 3450 -F 0 "U4" H 1700 3950 60 0000 C CNN -F 1 "plot_v1" H 1900 3800 60 0000 C CNN -F 2 "" H 1700 3450 60 0000 C CNN -F 3 "" H 1700 3450 60 0000 C CNN - 1 1700 3450 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U5 -U 1 1 5CF2632C -P 1700 3850 -F 0 "U5" H 1700 4350 60 0000 C CNN -F 1 "plot_v1" H 1900 4200 60 0000 C CNN -F 2 "" H 1700 3850 60 0000 C CNN -F 3 "" H 1700 3850 60 0000 C CNN - 1 1700 3850 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U6 -U 1 1 5CF26370 -P 1700 4250 -F 0 "U6" H 1700 4750 60 0000 C CNN -F 1 "plot_v1" H 1900 4600 60 0000 C CNN -F 2 "" H 1700 4250 60 0000 C CNN -F 3 "" H 1700 4250 60 0000 C CNN - 1 1700 4250 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U7 -U 1 1 5CF263B7 -P 1700 4650 -F 0 "U7" H 1700 5150 60 0000 C CNN -F 1 "plot_v1" H 1900 5000 60 0000 C CNN -F 2 "" H 1700 4650 60 0000 C CNN -F 3 "" H 1700 4650 60 0000 C CNN - 1 1700 4650 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U8 -U 1 1 5CF263FD -P 1700 5050 -F 0 "U8" H 1700 5550 60 0000 C CNN -F 1 "plot_v1" H 1900 5400 60 0000 C CNN -F 2 "" H 1700 5050 60 0000 C CNN -F 3 "" H 1700 5050 60 0000 C CNN - 1 1700 5050 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U9 -U 1 1 5CF26446 -P 1700 5500 -F 0 "U9" H 1700 6000 60 0000 C CNN -F 1 "plot_v1" H 1900 5850 60 0000 C CNN -F 2 "" H 1700 5500 60 0000 C CNN -F 3 "" H 1700 5500 60 0000 C CNN - 1 1700 5500 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U10 -U 1 1 5CF2649A -P 1700 5900 -F 0 "U10" H 1700 6400 60 0000 C CNN -F 1 "plot_v1" H 1900 6250 60 0000 C CNN -F 2 "" H 1700 5900 60 0000 C CNN -F 3 "" H 1700 5900 60 0000 C CNN - 1 1700 5900 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U1 -U 1 1 5CF26545 -P 1700 2100 -F 0 "U1" H 1700 2600 60 0000 C CNN -F 1 "plot_v1" H 1900 2450 60 0000 C CNN -F 2 "" H 1700 2100 60 0000 C CNN -F 3 "" H 1700 2100 60 0000 C CNN - 1 1700 2100 - 0 -1 -1 0 -$EndComp -Wire Wire Line - 3200 3900 2900 3900 -Wire Wire Line - 2900 3900 2900 2100 -Wire Wire Line - 2900 2100 1500 2100 -Wire Wire Line - 1500 2550 2850 2550 -Wire Wire Line - 2850 2550 2850 4000 -Wire Wire Line - 2850 4000 3200 4000 -Wire Wire Line - 3200 4100 2700 4100 -Wire Wire Line - 2700 4100 2700 3050 -Wire Wire Line - 2700 3050 1500 3050 -Wire Wire Line - 1500 3450 2650 3450 -Wire Wire Line - 2650 3450 2650 4200 -Wire Wire Line - 2650 4200 3200 4200 -Wire Wire Line - 3200 4300 2600 4300 -Wire Wire Line - 2600 4300 2600 3850 -Wire Wire Line - 2600 3850 1500 3850 -Wire Wire Line - 1500 4250 2550 4250 -Wire Wire Line - 2550 4250 2550 4400 -Wire Wire Line - 2550 4400 3200 4400 -Wire Wire Line - 2450 4500 3200 4500 -Wire Wire Line - 2450 4500 2450 4650 -Wire Wire Line - 2450 4650 1500 4650 -Wire Wire Line - 1500 5050 2600 5050 -Wire Wire Line - 2600 5050 2600 4600 -Wire Wire Line - 2600 4600 3200 4600 -Wire Wire Line - 3250 5000 2650 5000 -Wire Wire Line - 2650 5000 2650 5500 -Wire Wire Line - 2650 5500 1500 5500 -Wire Wire Line - 3250 5100 2700 5100 -Wire Wire Line - 2700 5100 2700 5900 -Wire Wire Line - 2700 5900 1500 5900 -$Comp -L plot_v1 U16 -U 1 1 5CF26B3C -P 8600 3250 -F 0 "U16" H 8600 3750 60 0000 C CNN -F 1 "plot_v1" H 8800 3600 60 0000 C CNN -F 2 "" H 8600 3250 60 0000 C CNN -F 3 "" H 8600 3250 60 0000 C CNN - 1 8600 3250 - 1 0 0 -1 -$EndComp -$Comp -L plot_v1 U15 -U 1 1 5CF26C0A -P 8250 3750 -F 0 "U15" H 8250 4250 60 0000 C CNN -F 1 "plot_v1" H 8450 4100 60 0000 C CNN -F 2 "" H 8250 3750 60 0000 C CNN -F 3 "" H 8250 3750 60 0000 C CNN - 1 8250 3750 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U14 -U 1 1 5CF26C90 -P 8150 4900 -F 0 "U14" H 8150 5400 60 0000 C CNN -F 1 "plot_v1" H 8350 5250 60 0000 C CNN -F 2 "" H 8150 4900 60 0000 C CNN -F 3 "" H 8150 4900 60 0000 C CNN - 1 8150 4900 - 0 -1 -1 0 -$EndComp -$Comp -L plot_v1 U17 -U 1 1 5CF26D07 -P 8750 5150 -F 0 "U17" H 8750 5650 60 0000 C CNN -F 1 "plot_v1" H 8950 5500 60 0000 C CNN -F 2 "" H 8750 5150 60 0000 C CNN -F 3 "" H 8750 5150 60 0000 C CNN - 1 8750 5150 - -1 0 0 1 -$EndComp -Wire Wire Line - 8750 5350 8750 4500 -Connection ~ 8750 4500 -Wire Wire Line - 7950 4900 8200 4900 -Connection ~ 8200 4900 -Wire Wire Line - 8050 3750 8500 3750 -Connection ~ 8500 3750 -Connection ~ 8600 3950 -Text GLabel 8450 3250 0 60 Input ~ 0 -a1 -Text GLabel 8250 3850 3 60 Input ~ 0 -a0 -Text GLabel 8600 4750 0 60 Input ~ 0 -a2 -Text GLabel 8050 5050 3 60 Input ~ 0 -a3 -Wire Wire Line - 8050 5050 8050 4900 -Connection ~ 8050 4900 -Wire Wire Line - 8600 4750 8750 4750 -Connection ~ 8750 4750 -Wire Wire Line - 8250 3850 8250 3750 -Connection ~ 8250 3750 -Wire Wire Line - 8450 3250 8600 3250 -Connection ~ 8600 3250 -NoConn ~ 6100 3950 -NoConn ~ 5100 4650 -Text GLabel 2000 1950 1 60 Output ~ 0 -q0 -Text GLabel 2000 2450 1 60 Output ~ 0 -q1 -Text GLabel 1900 2900 1 60 Output ~ 0 -q2 -Text GLabel 1850 3350 1 60 Output ~ 0 -q3 -Text GLabel 1850 3750 1 60 Output ~ 0 -q4 -Text GLabel 1850 4150 1 60 Output ~ 0 -q5 -Text GLabel 1800 4550 1 60 Output ~ 0 -q6 -Text GLabel 1800 4950 1 60 Output ~ 0 -q7 -Text GLabel 1800 5400 1 60 Output ~ 0 -q8 -Text GLabel 1800 5800 1 60 Output ~ 0 -q9 -Wire Wire Line - 1800 5800 1800 5900 -Connection ~ 1800 5900 -Wire Wire Line - 1800 5400 1800 5500 -Connection ~ 1800 5500 -Wire Wire Line - 1800 4950 1800 5050 -Connection ~ 1800 5050 -Wire Wire Line - 1800 4550 1800 4650 -Connection ~ 1800 4650 -Wire Wire Line - 1850 4150 1850 4250 -Connection ~ 1850 4250 -Wire Wire Line - 1850 3750 1850 3850 -Connection ~ 1850 3850 -Wire Wire Line - 1850 3350 1850 3450 -Connection ~ 1850 3450 -Wire Wire Line - 1900 2900 1900 3050 -Connection ~ 1900 3050 -Wire Wire Line - 2000 2450 2000 2550 -Connection ~ 2000 2550 -Wire Wire Line - 2000 1950 2000 2100 -Connection ~ 2000 2100 -$EndSCHEMATC ->>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test_Previous_Values.xml deleted file mode 100644 index 4156779d..00000000 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4></source><model><u13 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u13><u11 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u11><u12 name="type">dac_bridge<field11 name="Enter value for input load (default=1.0e-12)" /><field12 name="Enter value for out_low (default=0.0)" /><field13 name="Enter value for out_high (default=5.0)" /><field14 name="Enter the Rise Time (default=1.0e-9)" /><field15 name="Enter the Fall Time (default=1.0e-9)" /><field16 name="Enter value for out_undef (default=0.5)" /></u12></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4028</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib index 0a3ccf7f..0a3ccf7f 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~fellowship2019-python3 deleted file mode 100644 index af058641..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~fellowship2019-python3 +++ /dev/null @@ -1,61 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# d_and -# -DEF d_and U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "d_and" 50 100 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 -A 150 49 100 6 900 0 1 0 N 250 50 150 150 -P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N -X IN1 1 -450 100 200 R 50 50 1 1 I -X IN2 2 -450 0 200 R 50 50 1 1 I -X OUT 3 450 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir index 15f8954d..15f8954d 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out index e3c96645..e3c96645 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~fellowship2019-python3 deleted file mode 100644 index d7cf79a0..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~fellowship2019-python3 +++ /dev/null @@ -1,20 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir - -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3 deleted file mode 100644 index ba296cf0..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3 +++ /dev/null @@ -1,13 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and -U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT - -.end diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.pro b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro index 6f7acdde..dfb28cee 100644 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028.pro +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro @@ -1,43 +1,43 @@ -update=05/31/19 15:43:40
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_Sources
-LibName9=eSim_Subckt
-LibName10=eSim_User
+update=Wed Mar 18 19:41:37 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~HEAD deleted file mode 100644 index 0fdf4d25..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~HEAD +++ /dev/null @@ -1,44 +0,0 @@ -update=05/31/19 15:26:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=eSim_Analog
-LibName2=eSim_Devices
-LibName3=eSim_Digital
-LibName4=eSim_Hybrid
-LibName5=eSim_Miscellaneous
-LibName6=eSim_Plot
-LibName7=eSim_Power
-LibName8=eSim_PSpice
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~fellowship2019-python3 deleted file mode 100644 index 2c9ac554..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~fellowship2019-python3 +++ /dev/null @@ -1,58 +0,0 @@ -update=03/26/19 18:40:23 -version=1 -last_client=eeschema -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=texas -LibName3=intel -LibName4=audio -LibName5=interface -LibName6=digital-audio -LibName7=philips -LibName8=display -LibName9=cypress -LibName10=siliconi -LibName11=opto -LibName12=atmel -LibName13=contrib -LibName14=valves -LibName15=eSim_Analog -LibName16=eSim_Devices -LibName17=eSim_Digital -LibName18=eSim_Hybrid -LibName19=eSim_Miscellaneous -LibName20=eSim_Plot -LibName21=eSim_Power -LibName22=eSim_PSpice -LibName23=eSim_Sources -LibName24=eSim_Subckt -LibName25=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch index c853bf49..c853bf49 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~fellowship2019-python3 deleted file mode 100644 index 86be0215..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~fellowship2019-python3 +++ /dev/null @@ -1,121 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:power -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_PSpice -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L d_and U2 -U 1 1 5C9A24D8 -P 4250 2700 -F 0 "U2" H 4250 2700 60 0000 C CNN -F 1 "d_and" H 4300 2800 60 0000 C CNN -F 2 "" H 4250 2700 60 0000 C CNN -F 3 "" H 4250 2700 60 0000 C CNN - 1 4250 2700 - 1 0 0 -1 -$EndComp -$Comp -L d_and U3 -U 1 1 5C9A2538 -P 5150 2900 -F 0 "U3" H 5150 2900 60 0000 C CNN -F 1 "d_and" H 5200 3000 60 0000 C CNN -F 2 "" H 5150 2900 60 0000 C CNN -F 3 "" H 5150 2900 60 0000 C CNN - 1 5150 2900 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5C9A259A -P 3050 2600 -F 0 "U1" H 3100 2700 30 0000 C CNN -F 1 "PORT" H 3050 2600 30 0000 C CNN -F 2 "" H 3050 2600 60 0000 C CNN -F 3 "" H 3050 2600 60 0000 C CNN - 1 3050 2600 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5C9A25D9 -P 3050 2800 -F 0 "U1" H 3100 2900 30 0000 C CNN -F 1 "PORT" H 3050 2800 30 0000 C CNN -F 2 "" H 3050 2800 60 0000 C CNN -F 3 "" H 3050 2800 60 0000 C CNN - 2 3050 2800 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5C9A260A -P 3050 3100 -F 0 "U1" H 3100 3200 30 0000 C CNN -F 1 "PORT" H 3050 3100 30 0000 C CNN -F 2 "" H 3050 3100 60 0000 C CNN -F 3 "" H 3050 3100 60 0000 C CNN - 3 3050 3100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5C9A2637 -P 6900 2850 -F 0 "U1" H 6950 2950 30 0000 C CNN -F 1 "PORT" H 6900 2850 30 0000 C CNN -F 2 "" H 6900 2850 60 0000 C CNN -F 3 "" H 6900 2850 60 0000 C CNN - 4 6900 2850 - -1 0 0 1 -$EndComp -Wire Wire Line - 4700 2650 4700 2800 -Wire Wire Line - 5600 2850 6650 2850 -Wire Wire Line - 3800 2600 3300 2600 -Wire Wire Line - 3800 2700 3300 2700 -Wire Wire Line - 3300 2700 3300 2800 -Wire Wire Line - 3300 3100 4700 3100 -Wire Wire Line - 4700 3100 4700 2900 -$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub index b949ae4f..b949ae4f 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~fellowship2019-python3 deleted file mode 100644 index 3d9120bb..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~fellowship2019-python3 +++ /dev/null @@ -1,14 +0,0 @@ -* Subcircuit 3_and -.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ -* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir -* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and -* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and -a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 -a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 -* Schematic Name: d_and, NgSpice Name: d_and -.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Schematic Name: d_and, NgSpice Name: d_and -.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) -* Control Statements - -.ends 3_and
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml index abc5faaa..abc5faaa 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~HEAD deleted file mode 100644 index abc5faaa..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~HEAD +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~fellowship2019-python3 deleted file mode 100644 index abc5faaa..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~fellowship2019-python3 +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib index e316d596..e316d596 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~fellowship2019-python3 deleted file mode 100644 index 4ee605a2..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~fellowship2019-python3 +++ /dev/null @@ -1,62 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# 3_and -# -DEF 3_and X 0 40 Y Y 1 F N -F0 "X" 100 -50 60 H V C CNN -F1 "3_and" 150 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 -P 2 0 1 0 -150 200 200 200 N -P 3 0 1 0 -150 200 -150 -100 200 -100 N -X in1 1 -350 150 200 R 50 50 1 1 I -X in2 2 -350 50 200 R 50 50 1 1 I -X in3 3 -350 -50 200 R 50 50 1 1 I -X out 4 500 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir index 7afe79fe..7afe79fe 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out index d22d0923..d22d0923 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~fellowship2019-python3 deleted file mode 100644 index b25337cd..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~fellowship2019-python3 +++ /dev/null @@ -1,16 +0,0 @@ -* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir - -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port -x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and -x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~fellowship2019-python3 deleted file mode 100644 index e159f055..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~fellowship2019-python3 +++ /dev/null @@ -1,14 +0,0 @@ -* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT -X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and -X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and - -.end diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro index 7ed8e96e..7ed8e96e 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch index ff6d873a..ff6d873a 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~fellowship2019-python3 deleted file mode 100644 index 045208e6..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~fellowship2019-python3 +++ /dev/null @@ -1,263 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Plot -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_User -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L 3_and X1 -U 1 1 5CF10AEA -P 4550 2650 -F 0 "X1" H 4650 2600 60 0000 C CNN -F 1 "3_and" H 4700 2800 60 0000 C CNN -F 2 "" H 4550 2650 60 0000 C CNN -F 3 "" H 4550 2650 60 0000 C CNN - 1 4550 2650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 5CF10B72 -P 3100 2200 -F 0 "U1" H 3150 2300 30 0000 C CNN -F 1 "PORT" H 3100 2200 30 0000 C CNN -F 2 "" H 3100 2200 60 0000 C CNN -F 3 "" H 3100 2200 60 0000 C CNN - 1 3100 2200 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 5CF10BC9 -P 3100 2500 -F 0 "U1" H 3150 2600 30 0000 C CNN -F 1 "PORT" H 3100 2500 30 0000 C CNN -F 2 "" H 3100 2500 60 0000 C CNN -F 3 "" H 3100 2500 60 0000 C CNN - 2 3100 2500 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 8 1 5CF10BEA -P 3100 2850 -F 0 "U1" H 3150 2950 30 0000 C CNN -F 1 "PORT" H 3100 2850 30 0000 C CNN -F 2 "" H 3100 2850 60 0000 C CNN -F 3 "" H 3100 2850 60 0000 C CNN - 8 3100 2850 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 9 1 5CF10C10 -P 6200 2600 -F 0 "U1" H 6250 2700 30 0000 C CNN -F 1 "PORT" H 6200 2600 30 0000 C CNN -F 2 "" H 6200 2600 60 0000 C CNN -F 3 "" H 6200 2600 60 0000 C CNN - 9 6200 2600 - -1 0 0 1 -$EndComp -Wire Wire Line - 5950 2600 5050 2600 -Wire Wire Line - 4200 2500 4200 2200 -Wire Wire Line - 4200 2200 3350 2200 -Wire Wire Line - 3350 2500 3850 2500 -Wire Wire Line - 3850 2500 3850 2600 -Wire Wire Line - 3850 2600 4200 2600 -Wire Wire Line - 4200 2700 4200 2850 -Wire Wire Line - 4200 2850 3350 2850 -$Comp -L 3_and X3 -U 1 1 5CF10DE5 -P 4600 4100 -F 0 "X3" H 4700 4050 60 0000 C CNN -F 1 "3_and" H 4750 4250 60 0000 C CNN -F 2 "" H 4600 4100 60 0000 C CNN -F 3 "" H 4600 4100 60 0000 C CNN - 1 4600 4100 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 3 1 5CF10DEB -P 3150 3650 -F 0 "U1" H 3200 3750 30 0000 C CNN -F 1 "PORT" H 3150 3650 30 0000 C CNN -F 2 "" H 3150 3650 60 0000 C CNN -F 3 "" H 3150 3650 60 0000 C CNN - 3 3150 3650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 4 1 5CF10DF1 -P 3150 3950 -F 0 "U1" H 3200 4050 30 0000 C CNN -F 1 "PORT" H 3150 3950 30 0000 C CNN -F 2 "" H 3150 3950 60 0000 C CNN -F 3 "" H 3150 3950 60 0000 C CNN - 4 3150 3950 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 5 1 5CF10DF7 -P 3150 4300 -F 0 "U1" H 3200 4400 30 0000 C CNN -F 1 "PORT" H 3150 4300 30 0000 C CNN -F 2 "" H 3150 4300 60 0000 C CNN -F 3 "" H 3150 4300 60 0000 C CNN - 5 3150 4300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 6 1 5CF10DFD -P 6250 4050 -F 0 "U1" H 6300 4150 30 0000 C CNN -F 1 "PORT" H 6250 4050 30 0000 C CNN -F 2 "" H 6250 4050 60 0000 C CNN -F 3 "" H 6250 4050 60 0000 C CNN - 6 6250 4050 - -1 0 0 1 -$EndComp -Wire Wire Line - 6000 4050 5100 4050 -Wire Wire Line - 4250 3950 4250 3650 -Wire Wire Line - 4250 3650 3400 3650 -Wire Wire Line - 3400 3950 3900 3950 -Wire Wire Line - 3900 3950 3900 4050 -Wire Wire Line - 3900 4050 4250 4050 -Wire Wire Line - 4250 4150 4250 4300 -Wire Wire Line - 4250 4300 3400 4300 -$Comp -L 3_and X2 -U 1 1 5CF10E9C -P 4550 5450 -F 0 "X2" H 4650 5400 60 0000 C CNN -F 1 "3_and" H 4700 5600 60 0000 C CNN -F 2 "" H 4550 5450 60 0000 C CNN -F 3 "" H 4550 5450 60 0000 C CNN - 1 4550 5450 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 11 1 5CF10EA2 -P 3100 5000 -F 0 "U1" H 3150 5100 30 0000 C CNN -F 1 "PORT" H 3100 5000 30 0000 C CNN -F 2 "" H 3100 5000 60 0000 C CNN -F 3 "" H 3100 5000 60 0000 C CNN - 11 3100 5000 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 12 1 5CF10EA8 -P 3100 5300 -F 0 "U1" H 3150 5400 30 0000 C CNN -F 1 "PORT" H 3100 5300 30 0000 C CNN -F 2 "" H 3100 5300 60 0000 C CNN -F 3 "" H 3100 5300 60 0000 C CNN - 12 3100 5300 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 13 1 5CF10EAE -P 3100 5650 -F 0 "U1" H 3150 5750 30 0000 C CNN -F 1 "PORT" H 3100 5650 30 0000 C CNN -F 2 "" H 3100 5650 60 0000 C CNN -F 3 "" H 3100 5650 60 0000 C CNN - 13 3100 5650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 10 1 5CF10EB4 -P 6200 5400 -F 0 "U1" H 6250 5500 30 0000 C CNN -F 1 "PORT" H 6200 5400 30 0000 C CNN -F 2 "" H 6200 5400 60 0000 C CNN -F 3 "" H 6200 5400 60 0000 C CNN - 10 6200 5400 - -1 0 0 1 -$EndComp -Wire Wire Line - 5950 5400 5050 5400 -Wire Wire Line - 4200 5300 4200 5000 -Wire Wire Line - 4200 5000 3350 5000 -Wire Wire Line - 3350 5300 3850 5300 -Wire Wire Line - 3850 5300 3850 5400 -Wire Wire Line - 3850 5400 4200 5400 -Wire Wire Line - 4200 5500 4200 5650 -Wire Wire Line - 4200 5650 3350 5650 -$Comp -L PORT U1 -U 7 1 5CF11A2A -P 7500 4100 -F 0 "U1" H 7550 4200 30 0000 C CNN -F 1 "PORT" H 7500 4100 30 0000 C CNN -F 2 "" H 7500 4100 60 0000 C CNN -F 3 "" H 7500 4100 60 0000 C CNN - 7 7500 4100 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 14 1 5CF11A8A -P 7550 4600 -F 0 "U1" H 7600 4700 30 0000 C CNN -F 1 "PORT" H 7550 4600 30 0000 C CNN -F 2 "" H 7550 4600 60 0000 C CNN -F 3 "" H 7550 4600 60 0000 C CNN - 14 7550 4600 - -1 0 0 1 -$EndComp -NoConn ~ 7250 4100 -NoConn ~ 7300 4600 -$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub index b10679cc..b10679cc 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~fellowship2019-python3 deleted file mode 100644 index 15208169..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~fellowship2019-python3 +++ /dev/null @@ -1,10 +0,0 @@ -* Subcircuit 4073 -.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? -* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir -.include 3_and.sub -x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and -x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and -x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and -* Control Statements - -.ends 4073
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml index 5acac768..5acac768 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~HEAD +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~fellowship2019-python3 deleted file mode 100644 index 5acac768..00000000 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~fellowship2019-python3 +++ /dev/null @@ -1 +0,0 @@ -<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro index a356f8bb..c3d75252 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro @@ -1,6 +1,6 @@ -update=Wed Aug 14 12:44:12 2019 +update=Wed Mar 18 18:23:19 2020 version=1 -last_client=kicad +last_client=eeschema [general] version=1 RootSch= @@ -31,22 +31,14 @@ NetIExt=net version=1 LibDir=../../eSim/kicadSchematicLibrary [eeschema/libraries] -LibName1=4073_test-rescue -LibName2=power -LibName3=eSim_Analog -LibName4=eSim_Devices -LibName5=eSim_Digital -LibName6=eSim_Hybrid -LibName7=eSim_Miscellaneous -LibName8=eSim_Plot -LibName9=eSim_Power -<<<<<<< HEAD -LibName10=eSim_PSpice -LibName11=eSim_Sources -LibName12=eSim_Subckt -LibName13=eSim_User -======= -LibName10=eSim_User -LibName11=eSim_Sources -LibName12=eSim_Subckt ->>>>>>> fellowship2019-python3 +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib index b26d4bdf..b3066f61 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib @@ -27,19 +27,11 @@ X VDD 14 550 300 200 L 50 50 1 1 I ENDDRAW ENDDEF # -<<<<<<< HEAD -# DC -# -DEF DC v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC" -200 -50 60 H V C CNN -======= # DC-RESCUE-4_Input_NAND_Charcateristics # DEF DC-RESCUE-4_Input_NAND_Charcateristics v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN F1 "DC-RESCUE-4_Input_NAND_Charcateristics" -200 -50 60 H V C CNN ->>>>>>> fellowship2019-python3 F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro index cacee8d6..f614a5d4 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro @@ -1,51 +1,4 @@ -<<<<<<< HEAD -update=06/01/19 15:09:21
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../eSim/kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_User
-LibName12=eSim_Subckt
-======= -update=Wed Mar 11 12:52:26 2020 +update=Wed Mar 18 18:09:45 2020 version=1 last_client=eeschema [general] @@ -90,4 +43,3 @@ LibName9=eSim_Power LibName10=eSim_Subckt LibName11=eSim_Sources LibName12=eSim_User ->>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch index 40e78f30..5d230393 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch @@ -1,8 +1,5 @@ EESchema Schematic File Version 2 -<<<<<<< HEAD -======= LIBS:4_Input_NAND_Charcateristics-rescue ->>>>>>> fellowship2019-python3 LIBS:power LIBS:eSim_Analog LIBS:eSim_Devices @@ -11,10 +8,6 @@ LIBS:eSim_Hybrid LIBS:eSim_Miscellaneous LIBS:eSim_Plot LIBS:eSim_Power -<<<<<<< HEAD -LIBS:eSim_PSpice -======= ->>>>>>> fellowship2019-python3 LIBS:eSim_Sources LIBS:eSim_User LIBS:eSim_Subckt @@ -58,11 +51,7 @@ $EndComp NoConn ~ 4550 4350 NoConn ~ 5600 3750 $Comp -<<<<<<< HEAD -L DC v1 -======= L DC-RESCUE-4_Input_NAND_Charcateristics v1 ->>>>>>> fellowship2019-python3 U 1 1 5CF2488C P 1900 3450 F 0 "v1" H 1700 3550 60 0000 C CNN @@ -73,11 +62,7 @@ F 3 "" H 1900 3450 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v2 -======= L DC-RESCUE-4_Input_NAND_Charcateristics v2 ->>>>>>> fellowship2019-python3 U 1 1 5CF248E2 P 1900 4000 F 0 "v2" H 1700 4100 60 0000 C CNN @@ -88,11 +73,7 @@ F 3 "" H 1900 4000 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v3 -======= L DC-RESCUE-4_Input_NAND_Charcateristics v3 ->>>>>>> fellowship2019-python3 U 1 1 5CF24906 P 1900 4550 F 0 "v3" H 1700 4650 60 0000 C CNN @@ -103,11 +84,7 @@ F 3 "" H 1900 4550 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v4 -======= L DC-RESCUE-4_Input_NAND_Charcateristics v4 ->>>>>>> fellowship2019-python3 U 1 1 5CF24935 P 1900 5100 F 0 "v4" H 1700 5200 60 0000 C CNN @@ -161,11 +138,7 @@ F 3 "" H 6450 4050 60 0000 C CNN -1 0 0 1 $EndComp $Comp -<<<<<<< HEAD -L DC v8 -======= L DC-RESCUE-4_Input_NAND_Charcateristics v8 ->>>>>>> fellowship2019-python3 U 1 1 5CF24B50 P 8150 4650 F 0 "v8" H 7950 4750 60 0000 C CNN @@ -176,11 +149,7 @@ F 3 "" H 8150 4650 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v7 -======= L DC-RESCUE-4_Input_NAND_Charcateristics v7 ->>>>>>> fellowship2019-python3 U 1 1 5CF24B56 P 8150 4100 F 0 "v7" H 7950 4200 60 0000 C CNN @@ -191,11 +160,7 @@ F 3 "" H 8150 4100 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v6 -======= L DC-RESCUE-4_Input_NAND_Charcateristics v6 ->>>>>>> fellowship2019-python3 U 1 1 5CF24B5C P 8150 3550 F 0 "v6" H 7950 3650 60 0000 C CNN @@ -206,11 +171,7 @@ F 3 "" H 8150 3550 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v5 -======= L DC-RESCUE-4_Input_NAND_Charcateristics v5 ->>>>>>> fellowship2019-python3 U 1 1 5CF24B62 P 8150 3000 F 0 "v5" H 7950 3100 60 0000 C CNN diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib index c955612e..798ad8bc 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib @@ -1,19 +1,11 @@ EESchema-LIBRARY Version 2.3 #encoding utf-8 # -<<<<<<< HEAD -# DC -# -DEF DC v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC" -200 -50 60 H V C CNN -======= # DC-RESCUE-4_Input_NOR_Characteristics # DEF DC-RESCUE-4_Input_NOR_Characteristics v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN F1 "DC-RESCUE-4_Input_NOR_Characteristics" -200 -50 60 H V C CNN ->>>>>>> fellowship2019-python3 F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST @@ -118,16 +110,10 @@ ENDDEF # DEF eSim_R R 0 0 N Y 1 F N F0 "R" 50 130 50 H V C CNN -<<<<<<< HEAD -F1 "eSim_R" 50 50 50 H V C CNN -F2 "" 50 -20 30 H V C CNN -F3 "" 50 50 30 V V C CNN -======= F1 "eSim_R" 50 -50 50 H V C CNN F2 "" 50 -20 30 H V C CNN F3 "" 50 50 30 V V C CNN ALIAS resistor ->>>>>>> fellowship2019-python3 $FPLIST R_* Resistor_* diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro index 7634e0b8..9f91a19f 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro @@ -1,50 +1,4 @@ -<<<<<<< HEAD -update=06/01/19 05:45:01
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
-LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
-LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
-LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
-LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
-LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
-LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
-LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
-LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
-LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
-======= -update=Wed Mar 11 12:54:03 2020 +update=Wed Mar 18 19:49:13 2020 version=1 last_client=eeschema [general] @@ -89,4 +43,3 @@ LibName9=eSim_Miscellaneous LibName10=eSim_Hybrid LibName11=eSim_Digital LibName12=eSim_Analog ->>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch index f18161c9..9ecf9c77 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch @@ -1,7 +1,4 @@ EESchema Schematic File Version 2 -<<<<<<< HEAD -LIBS:power -======= LIBS:4_Input_NOR_Characteristics-rescue LIBS:power LIBS:eSim_Devices @@ -14,7 +11,6 @@ LIBS:eSim_Miscellaneous LIBS:eSim_Hybrid LIBS:eSim_Digital LIBS:eSim_Analog ->>>>>>> fellowship2019-python3 LIBS:4_Input_NOR_Characteristics-cache EELAYER 25 0 EELAYER END @@ -379,11 +375,7 @@ F 3 "" V 7400 3450 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -<<<<<<< HEAD -L DC v6 -======= L DC-RESCUE-4_Input_NOR_Characteristics v6 ->>>>>>> fellowship2019-python3 U 1 1 5CF1E4C8 P 8200 3550 F 0 "v6" H 8000 3650 60 0000 C CNN @@ -394,11 +386,7 @@ F 3 "" H 8200 3550 60 0000 C CNN 0 -1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v5 -======= L DC-RESCUE-4_Input_NOR_Characteristics v5 ->>>>>>> fellowship2019-python3 U 1 1 5CF1E4C2 P 8200 3650 F 0 "v5" H 8000 3750 60 0000 C CNN @@ -409,11 +397,7 @@ F 3 "" H 8200 3650 60 0000 C CNN 0 -1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v8 -======= L DC-RESCUE-4_Input_NOR_Characteristics v8 ->>>>>>> fellowship2019-python3 U 1 1 5CF1E4BC P 8200 3350 F 0 "v8" H 8000 3450 60 0000 C CNN @@ -424,11 +408,7 @@ F 3 "" H 8200 3350 60 0000 C CNN 0 -1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v7 -======= L DC-RESCUE-4_Input_NOR_Characteristics v7 ->>>>>>> fellowship2019-python3 U 1 1 5CF1E4B6 P 8200 3450 F 0 "v7" H 8000 3550 60 0000 C CNN @@ -587,11 +567,7 @@ F 3 "" V 3600 3350 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -<<<<<<< HEAD -L DC v4 -======= L DC-RESCUE-4_Input_NOR_Characteristics v4 ->>>>>>> fellowship2019-python3 U 1 1 5CF1D11E P 2750 3550 F 0 "v4" H 2550 3650 60 0000 C CNN @@ -602,11 +578,7 @@ F 3 "" H 2750 3550 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v3 -======= L DC-RESCUE-4_Input_NOR_Characteristics v3 ->>>>>>> fellowship2019-python3 U 1 1 5CF1D0EF P 2750 3450 F 0 "v3" H 2550 3550 60 0000 C CNN @@ -617,11 +589,7 @@ F 3 "" H 2750 3450 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v2 -======= L DC-RESCUE-4_Input_NOR_Characteristics v2 ->>>>>>> fellowship2019-python3 U 1 1 5CF1D0C3 P 2700 3350 F 0 "v2" H 2500 3450 60 0000 C CNN @@ -632,11 +600,7 @@ F 3 "" H 2700 3350 60 0000 C CNN 0 1 1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v1 -======= L DC-RESCUE-4_Input_NOR_Characteristics v1 ->>>>>>> fellowship2019-python3 U 1 1 5CF1CE2E P 2700 3250 F 0 "v1" H 2500 3350 60 0000 C CNN diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib index 81e6945f..29acff42 100644 --- a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib @@ -29,19 +29,11 @@ X Vdd 16 500 350 200 L 50 50 1 1 O ENDDRAW ENDDEF # -<<<<<<< HEAD -# DC -# -DEF DC v 0 40 Y Y 1 F N -F0 "v" -200 100 60 H V C CNN -F1 "DC" -200 -50 60 H V C CNN -======= # DC-RESCUE-BCDToDecimalDecoder # DEF DC-RESCUE-BCDToDecimalDecoder v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN F1 "DC-RESCUE-BCDToDecimalDecoder" -200 -50 60 H V C CNN ->>>>>>> fellowship2019-python3 F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro index 3a7a5a58..33b3cf61 100644 --- a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro @@ -1,50 +1,4 @@ -<<<<<<< HEAD -update=06/01/19 16:07:13
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
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-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../eSim/kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_Sources
-LibName10=eSim_Subckt
-LibName11=eSim_User
-======= -update=Wed Mar 11 12:54:17 2020 +update=Wed Mar 18 18:24:51 2020 version=1 last_client=eeschema [general] @@ -77,16 +31,14 @@ NetIExt=net version=1 LibDir=../../eSim/kicadSchematicLibrary [eeschema/libraries] -LibName1=BCDToDecimalDecoder-rescue -LibName2=power -LibName3=eSim_Analog -LibName4=eSim_Devices -LibName5=eSim_Digital -LibName6=eSim_Hybrid -LibName7=eSim_Miscellaneous -LibName8=eSim_Plot -LibName9=eSim_Power -LibName10=eSim_Sources -LibName11=eSim_Subckt -LibName12=eSim_User ->>>>>>> fellowship2019-python3 +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch index 15ab433e..093956bb 100644 --- a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch @@ -1,8 +1,5 @@ EESchema Schematic File Version 2 -<<<<<<< HEAD -======= LIBS:BCDToDecimalDecoder-rescue ->>>>>>> fellowship2019-python3 LIBS:power LIBS:eSim_Analog LIBS:eSim_Devices @@ -74,11 +71,7 @@ F 3 "" H 3800 5050 60 0000 C CNN -1 0 0 -1 $EndComp $Comp -<<<<<<< HEAD -L DC v2 -======= L DC-RESCUE-BCDToDecimalDecoder v2 ->>>>>>> fellowship2019-python3 U 1 1 5CF25946 P 9400 3950 F 0 "v2" H 9200 4050 60 0000 C CNN @@ -89,11 +82,7 @@ F 3 "" H 9400 3950 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v1 -======= L DC-RESCUE-BCDToDecimalDecoder v1 ->>>>>>> fellowship2019-python3 U 1 1 5CF259A4 P 9400 3400 F 0 "v1" H 9200 3500 60 0000 C CNN @@ -104,11 +93,7 @@ F 3 "" H 9400 3400 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v3 -======= L DC-RESCUE-BCDToDecimalDecoder v3 ->>>>>>> fellowship2019-python3 U 1 1 5CF259F8 P 9400 4500 F 0 "v3" H 9200 4600 60 0000 C CNN @@ -119,11 +104,7 @@ F 3 "" H 9400 4500 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp -<<<<<<< HEAD -L DC v4 -======= L DC-RESCUE-BCDToDecimalDecoder v4 ->>>>>>> fellowship2019-python3 U 1 1 5CF25A37 P 9450 5000 F 0 "v4" H 9250 5100 60 0000 C CNN |