7404 subcircuit added

18 files changed, 1072 insertions, 0 deletions

diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-cache.lib b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-cache.lib
new file mode 100644
index 00000000..9c38feb3
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-cache.lib
@@ -0,0 +1,82 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test-cache.lib b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test-cache.lib
new file mode 100644
index 00000000..e1d82216
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test-cache.lib
@@ -0,0 +1,114 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_74LS04
+#
+DEF eSim_74LS04 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "eSim_74LS04" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S 350 500 -350 -500 0 1 0 N
+X ~ 1 -550 450 200 R 50 50 1 1 P
+X ~ 2 -550 300 200 R 50 50 1 1 P I
+X ~ 3 -550 150 200 R 50 50 1 1 P
+X ~ 4 -550 0 200 R 50 50 1 1 P I
+X ~ 5 -550 -150 200 R 50 50 1 1 P
+X ~ 6 -550 -300 200 R 50 50 1 1 P I
+X GND 7 -550 -450 200 R 50 50 1 1 P
+X ~ 8 550 -450 200 L 50 50 1 1 P I
+X ~ 9 550 -300 200 L 50 50 1 1 P
+X ~ 10 550 -150 200 L 50 50 1 1 P I
+X ~ 11 550 0 200 L 50 50 1 1 P
+X ~ 12 550 150 200 L 50 50 1 1 P I
+X ~ 13 550 300 200 L 50 50 1 1 P
+X VCC 14 550 450 200 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.cir b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.cir
new file mode 100644
index 00000000..60d54ea3
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.cir
@@ -0,0 +1,17 @@
+* /home/ash98/eSim-Workspace/74LS04-test/74LS04-test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jan 14 13:18:34 2020
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v2  Net-_X1-Pad14_ GND DC		
+v1  in1 GND pulse		
+R2  in1 Net-_R2-Pad2_ 1k		
+U2  out1 plot_v1		
+U1  in1 plot_v1		
+R1  out1 GND 2k		
+X1  Net-_R2-Pad2_ out1 ? ? ? ? GND ? ? ? ? ? ? Net-_X1-Pad14_ eSim_74LS04		
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.cir.out b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.cir.out
new file mode 100644
index 00000000..640835b1
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.cir.out
@@ -0,0 +1,21 @@
+* /home/ash98/esim-workspace/74ls04-test/74ls04-test.cir
+
+.include 74LS04.sub
+v2 net-_x1-pad14_ gnd  dc 0.7
+v1  in1 gnd pulse(0 5 0 0 0 14e-9 28e-9)
+r2  in1 net-_r2-pad2_ 1k
+* u2  out1 plot_v1
+* u1  in1 plot_v1
+r1  out1 gnd 2k
+x1 net-_r2-pad2_ out1 ? ? ? ? gnd ? ? ? ? ? ? net-_x1-pad14_ 74LS04
+.tran 10e-12 100e-09 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out1)
+plot v(in1)
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.pro b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.pro
new file mode 100644
index 00000000..543c22c9
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.pro
@@ -0,0 +1,69 @@
+update=Sun Apr  5 11:08:06 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=transistors
+LibName23=conn
+LibName24=regul
+LibName25=74xx
+LibName26=cmos4000
+LibName27=eSim_Analog
+LibName28=eSim_Devices
+LibName29=eSim_Digital
+LibName30=eSim_Hybrid
+LibName31=eSim_Miscellaneous
+LibName32=eSim_Power
+LibName33=eSim_Sources
+LibName34=eSim_Subckt
+LibName35=eSim_User
+LibName36=eSim_Plot
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.proj b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.proj
new file mode 100644
index 00000000..185af7de
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.proj
@@ -0,0 +1 @@
+schematicFile 74LS04-test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.sch b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.sch
new file mode 100644
index 00000000..4d6d401e
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test.sch
@@ -0,0 +1,193 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:74LS04-test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L DC v2
+U 1 1 5E1D63E6
+P 5400 3400
+F 0 "v2" H 5200 3500 60  0000 C CNN
+F 1 "DC" H 5200 3350 60  0000 C CNN
+F 2 "R1" H 5100 3400 60  0000 C CNN
+F 3 "" H 5400 3400 60  0000 C CNN
+	1    5400 3400
+	0    1    1    0   
+$EndComp
+$Comp
+L pulse v1
+U 1 1 5E1D6488
+P 3200 2150
+F 0 "v1" H 3000 2250 60  0000 C CNN
+F 1 "pulse" H 3000 2100 60  0000 C CNN
+F 2 "R1" H 2900 2150 60  0000 C CNN
+F 3 "" H 3200 2150 60  0000 C CNN
+	1    3200 2150
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_R R2
+U 1 1 5E1D64F5
+P 3900 2200
+F 0 "R2" H 3950 2330 50  0000 C CNN
+F 1 "1k" H 3950 2150 50  0000 C CNN
+F 2 "" H 3950 2180 30  0000 C CNN
+F 3 "" V 3950 2250 30  0000 C CNN
+	1    3900 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L plot_v1 U2
+U 1 1 5E1D6966
+P 4650 2400
+F 0 "U2" H 4650 2900 60  0000 C CNN
+F 1 "plot_v1" H 4850 2750 60  0000 C CNN
+F 2 "" H 4650 2400 60  0000 C CNN
+F 3 "" H 4650 2400 60  0000 C CNN
+	1    4650 2400
+	1    0    0    -1  
+$EndComp
+Text GLabel 4300 2350 0    60   Input ~ 0
+out1
+$Comp
+L plot_v1 U1
+U 1 1 5E1D6B17
+P 3750 2200
+F 0 "U1" H 3750 2700 60  0000 C CNN
+F 1 "plot_v1" H 3950 2550 60  0000 C CNN
+F 2 "" H 3750 2200 60  0000 C CNN
+F 3 "" H 3750 2200 60  0000 C CNN
+	1    3750 2200
+	1    0    0    -1  
+$EndComp
+Text GLabel 3650 2050 0    60   Input ~ 0
+in1
+Wire Wire Line
+	6100 2150 6100 3400
+Wire Wire Line
+	2650 3050 4950 3050
+Wire Wire Line
+	4850 3050 4850 3400
+Wire Wire Line
+	4850 3400 4950 3400
+Wire Wire Line
+	6100 3400 5850 3400
+Wire Wire Line
+	4100 2150 4950 2150
+Wire Wire Line
+	3650 2150 3800 2150
+Wire Wire Line
+	3750 2000 3750 2150
+Connection ~ 3750 2150
+Wire Wire Line
+	3650 2050 3700 2050
+Wire Wire Line
+	3700 2050 3700 2150
+Connection ~ 3700 2150
+$Comp
+L GND #PWR01
+U 1 1 5E1D7F75
+P 3850 3400
+F 0 "#PWR01" H 3850 3150 50  0001 C CNN
+F 1 "GND" H 3850 3250 50  0000 C CNN
+F 2 "" H 3850 3400 50  0001 C CNN
+F 3 "" H 3850 3400 50  0001 C CNN
+	1    3850 3400
+	1    0    0    -1  
+$EndComp
+Connection ~ 4850 3050
+Wire Wire Line
+	3850 3400 3850 3050
+Connection ~ 3850 3050
+Wire Wire Line
+	4650 2200 4650 2300
+Connection ~ 4650 2300
+$Comp
+L eSim_R R1
+U 1 1 5E1D823A
+P 4400 2600
+F 0 "R1" H 4450 2730 50  0000 C CNN
+F 1 "2k" H 4450 2550 50  0000 C CNN
+F 2 "" H 4450 2580 30  0000 C CNN
+F 3 "" V 4450 2650 30  0000 C CNN
+	1    4400 2600
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	4450 2500 4450 2300
+Wire Wire Line
+	4450 2800 4450 3050
+Connection ~ 4450 3050
+Wire Wire Line
+	4450 2300 4950 2300
+Wire Wire Line
+	2750 2150 2650 2150
+Wire Wire Line
+	2650 2150 2650 3050
+Wire Wire Line
+	4300 2350 4450 2350
+Connection ~ 4450 2350
+$Comp
+L eSim_74LS04 X1
+U 1 1 5E1D88C9
+P 5500 2600
+F 0 "X1" H 5500 2700 60  0000 C CNN
+F 1 "eSim_74LS04" H 5500 2600 60  0000 C CNN
+F 2 "" H 5500 2600 60  0001 C CNN
+F 3 "" H 5500 2600 60  0001 C CNN
+	1    5500 2600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 2150 6100 2150
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test_Previous_Values.xml
new file mode 100644
index 00000000..a5b20c5f
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04-test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value">0.7</field1></v2><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0</field4><field5 name="Fall Time">0</field5><field5 name="Pulse width">14e-9</field5><field5 name="Period">28e-9</field5></v1><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0</field4><field5 name="Fall Time">0</field5><field5 name="Pulse width">7e-9</field5><field5 name="Period">10e-9</field5></v3></source><model /><devicemodel /><subcircuit><x1><field>/home/saurabh/Desktop/IC74LS04/74LS04</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1">v2</field1><field2 name="Start">0</field2><field3 name="Increment">1</field3><field4 name="Stop">10</field4><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">mV or mA</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ps</field5><field6 name="Stop Combo">ns</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.cir b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.cir
new file mode 100644
index 00000000..bb2d0f69
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.cir
@@ -0,0 +1,23 @@
+* /home/ash98/Downloads/eSim-1.1.3/src/SubcircuitLibrary/74LS04/74LS04.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jan 14 11:36:33 2020
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q5  Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+R5  Net-_R1-Pad1_ Net-_Q5-Pad1_ 100		
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+R1  Net-_R1-Pad1_ Net-_Q1-Pad1_ 100		
+Q3  Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+R3  Net-_R1-Pad1_ Net-_Q3-Pad1_ 100		
+Q6  Net-_Q6-Pad1_ Net-_Q6-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+R6  Net-_R1-Pad1_ Net-_Q6-Pad1_ 100		
+Q2  Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+R2  Net-_R1-Pad1_ Net-_Q2-Pad1_ 100		
+Q4  Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+R4  Net-_R1-Pad1_ Net-_Q4-Pad1_ 100		
+U1  Net-_Q1-Pad2_ Net-_Q1-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad1_ Net-_Q1-Pad3_ Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q6-Pad1_ Net-_Q6-Pad2_ Net-_R1-Pad1_ PORT		
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.cir.out b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.cir.out
new file mode 100644
index 00000000..c222c723
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.cir.out
@@ -0,0 +1,25 @@
+* /home/ash98/downloads/esim-1.1.3/src/subcircuitlibrary/74ls04/74ls04.cir
+
+.include Ideal_npn1.lib
+q5 net-_q5-pad1_ net-_q5-pad2_ net-_q1-pad3_ Ideal_npn2
+r5  net-_r1-pad1_ net-_q5-pad1_ 100
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Ideal_npn2
+r1  net-_r1-pad1_ net-_q1-pad1_ 100
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Ideal_npn2
+r3  net-_r1-pad1_ net-_q3-pad1_ 100
+q6 net-_q6-pad1_ net-_q6-pad2_ net-_q1-pad3_ Ideal_npn2
+r6  net-_r1-pad1_ net-_q6-pad1_ 100
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q1-pad3_ Ideal_npn2
+r2  net-_r1-pad1_ net-_q2-pad1_ 100
+q4 net-_q4-pad1_ net-_q4-pad2_ net-_q1-pad3_ Ideal_npn2
+r4  net-_r1-pad1_ net-_q4-pad1_ 100
+* u1  net-_q1-pad2_ net-_q1-pad1_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad1_ net-_q1-pad3_ net-_q2-pad1_ net-_q2-pad2_ net-_q4-pad1_ net-_q4-pad2_ net-_q6-pad1_ net-_q6-pad2_ net-_r1-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.pro b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.pro
new file mode 100644
index 00000000..38d194c6
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.pro
@@ -0,0 +1,72 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=device
+LibName23=transistors
+LibName24=conn
+LibName25=linear
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_User
+LibName38=eSim_Plot
+LibName39=eSim_PSpice
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.sch b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.sch
new file mode 100644
index 00000000..577aa134
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.sch
@@ -0,0 +1,427 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
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+EELAYER END
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+	1    5950 4500
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+$EndComp
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+U 1 1 5E1D6683
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+F 2 "" H 3250 2950 60  0000 C CNN
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+U 2 1 5E1D6721
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+	2    4500 2700
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+$Comp
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+U 6 1 5E1D68AB
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+F 1 "PORT" H 8750 2700 30  0000 C CNN
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+F 3 "" H 8750 2700 60  0000 C CNN
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+F 2 "" H 8650 2200 60  0000 C CNN
+F 3 "" H 8650 2200 60  0000 C CNN
+	14   8650 2200
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+Wire Wire Line
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+Wire Wire Line
+	3950 2650 3950 2750
+Connection ~ 6000 2700
+Wire Wire Line
+	6000 2700 6300 2700
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+	6000 2650 6000 2750
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+Wire Wire Line
+	8200 4750 8500 4750
+Wire Wire Line
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+Wire Wire Line
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+	3950 4700 3950 4800
+Connection ~ 6000 4750
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+Wire Wire Line
+	3950 3300 9850 3300
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+	8200 3300 8200 3150
+Wire Wire Line
+	6000 3150 6000 3300
+Connection ~ 6000 3300
+Wire Wire Line
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+Wire Wire Line
+	3950 5300 9850 5300
+Wire Wire Line
+	8200 5300 8200 5200
+Wire Wire Line
+	6000 5200 6000 5300
+Connection ~ 6000 5300
+Wire Wire Line
+	9850 5300 9850 3300
+Connection ~ 8200 5300
+Connection ~ 8200 3300
+Wire Wire Line
+	3950 2350 3950 2200
+Wire Wire Line
+	2800 2200 8400 2200
+Wire Wire Line
+	8200 2200 8200 2350
+Wire Wire Line
+	6000 2350 6000 2200
+Connection ~ 6000 2200
+Wire Wire Line
+	2800 2200 2800 4300
+Wire Wire Line
+	2800 4300 8200 4300
+Wire Wire Line
+	3950 4300 3950 4400
+Connection ~ 3950 2200
+Wire Wire Line
+	8200 4300 8200 4400
+Connection ~ 3950 4300
+Wire Wire Line
+	6000 4400 6000 4300
+Connection ~ 6000 4300
+Connection ~ 8200 2200
+Wire Wire Line
+	9650 4050 9850 4050
+Connection ~ 9850 4050
+Text Label 8350 2150 0    60   ~ 0
+VCC
+Text Label 9650 4000 0    60   ~ 0
+GND
+Text Label 5850 6000 0    60   ~ 0
+IC_74LS04_subcircuit
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.sub b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.sub
new file mode 100644
index 00000000..8687a3cc
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04.sub
@@ -0,0 +1,19 @@
+* Subcircuit 74LS04
+.subckt 74LS04 net-_q1-pad2_ net-_q1-pad1_ net-_q3-pad2_ net-_q3-pad1_ net-_q5-pad2_ net-_q5-pad1_ net-_q1-pad3_ net-_q2-pad1_ net-_q2-pad2_ net-_q4-pad1_ net-_q4-pad2_ net-_q6-pad1_ net-_q6-pad2_ net-_r1-pad1_ 
+* /home/ash98/downloads/esim-1.1.3/src/subcircuitlibrary/74ls04/74ls04.cir
+.include Ideal_npn1.lib
+q5 net-_q5-pad1_ net-_q5-pad2_ net-_q1-pad3_ Ideal_npn2
+r5  net-_r1-pad1_ net-_q5-pad1_ 100
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Ideal_npn2
+r1  net-_r1-pad1_ net-_q1-pad1_ 100
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_q1-pad3_ Ideal_npn2
+r3  net-_r1-pad1_ net-_q3-pad1_ 100
+q6 net-_q6-pad1_ net-_q6-pad2_ net-_q1-pad3_ Ideal_npn2
+r6  net-_r1-pad1_ net-_q6-pad1_ 100
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q1-pad3_ Ideal_npn2
+r2  net-_r1-pad1_ net-_q2-pad1_ 100
+q4 net-_q4-pad1_ net-_q4-pad2_ net-_q1-pad3_ Ideal_npn2
+r4  net-_r1-pad1_ net-_q4-pad1_ 100
+* Control Statements
+
+.ends 74LS04
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04_Previous_Values.xml
new file mode 100644
index 00000000..fcf16953
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/74LS04_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel><q1><field>/home/ash98/Downloads/eSim-1.1.3/src/deviceModelLibrary/User Libraries/Ideal_npn1.lib</field></q1><q3><field>/home/ash98/Downloads/eSim-1.1.3/src/deviceModelLibrary/User Libraries/Ideal_npn1.lib</field></q3><q2><field>/home/ash98/Downloads/eSim-1.1.3/src/deviceModelLibrary/User Libraries/Ideal_npn1.lib</field></q2><q5><field>/home/ash98/Downloads/eSim-1.1.3/src/deviceModelLibrary/User Libraries/Ideal_npn1.lib</field></q5><q4><field>/home/ash98/Downloads/eSim-1.1.3/src/deviceModelLibrary/User Libraries/Ideal_npn1.lib</field></q4><q6><field>/home/ash98/Downloads/eSim-1.1.3/src/deviceModelLibrary/User Libraries/Ideal_npn1.lib</field></q6></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/BC547B.lib b/Examples/Analysis_Of_Digital_IC/74LS04-test/BC547B.lib
new file mode 100644
index 00000000..723537a7
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/BC547B.lib
@@ -0,0 +1 @@
+.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14  NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56  RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8)
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/Ideal_npn1.lib b/Examples/Analysis_Of_Digital_IC/74LS04-test/Ideal_npn1.lib
new file mode 100644
index 00000000..7d77cf88
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/Ideal_npn1.lib
@@ -0,0 +1 @@
+.model Ideal_npn2 NPN(MJE=0.337 BF=400 BR=6 IKF=0.3 VTF=1.7 ITF=0.6 CJC=0 IS=1E-14 MJC=0.33 TR=1.25e-12 CJE=0 VAF=1e12 XTF=3 RE=.2  RB=1  RC=.3 TF=12.5e-12 EG=1.11 XTB=1.5)
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/NPN.lib b/Examples/Analysis_Of_Digital_IC/74LS04-test/NPN.lib
new file mode 100644
index 00000000..6509fe7a
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p 
++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) 
diff --git a/Examples/Analysis_Of_Digital_IC/74LS04-test/analysis b/Examples/Analysis_Of_Digital_IC/74LS04-test/analysis
new file mode 100644
index 00000000..5b601865
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/74LS04-test/analysis
@@ -0,0 +1 @@
+.tran 10e-12 100e-09 0e-00
\ No newline at end of file