diff options
| author | rahulp13 | 2020-02-14 15:16:35 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-14 15:16:35 +0530 |
| commit | cb55e59de7ee4383c04edfae7c39ad9ae9552b36 (patch) | |
| tree | de1b292a10e8196689bf1a208fe6fe32f4618846 /Examples/Analysis_Of_Digital_IC | |
| parent | 08d4a0336550a0e610709970a0c5d366e109fe82 (diff) | |
| download | eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.gz eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.bz2 eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.zip | |
common code for Win and Linux, merged py2 changes
Diffstat (limited to 'Examples/Analysis_Of_Digital_IC')
157 files changed, 13958 insertions, 0 deletions
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib new file mode 100644 index 00000000..3c64b7f9 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4023 +# +DEF 4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_3 +# +DEF dac_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.cir b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.cir new file mode 100644 index 00000000..9356242a --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.cir @@ -0,0 +1,36 @@ +* C:\Users\malli\eSim-Workspace\4023_test\4023_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 15:46:37
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U7-Pad4_ Net-_U7-Pad5_ Net-_U8-Pad4_ Net-_U8-Pad5_ Net-_U8-Pad6_ Net-_U9-Pad2_ ? Net-_U7-Pad6_ Net-_U9-Pad1_ Net-_U9-Pad3_ Net-_U10-Pad6_ Net-_U10-Pad5_ Net-_U10-Pad4_ ? 4023
+U8 a2 b2 c2 Net-_U8-Pad4_ Net-_U8-Pad5_ Net-_U8-Pad6_ adc_bridge_3
+U7 a1 b1 c1 Net-_U7-Pad4_ Net-_U7-Pad5_ Net-_U7-Pad6_ adc_bridge_3
+U10 a3 b3 c3 Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U10-Pad6_ adc_bridge_3
+U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U9-Pad3_ q1 q2 q3 dac_bridge_3
+v1 a1 GND DC
+v2 b1 GND DC
+v3 c1 GND DC
+v4 a2 GND DC
+v5 b2 GND DC
+v6 c2 GND DC
+v7 a3 GND DC
+v8 b3 GND DC
+v9 c3 GND DC
+U16 b3 plot_v1
+U12 a3 plot_v1
+U14 c3 plot_v1
+U2 b2 plot_v1
+U5 c2 plot_v1
+U4 a2 plot_v1
+U3 c1 plot_v1
+U6 a1 plot_v1
+U1 b1 plot_v1
+U13 q3 plot_v1
+U15 q2 plot_v1
+U11 q1 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.cir.out b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.cir.out new file mode 100644 index 00000000..8d3a0d92 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.cir.out @@ -0,0 +1,62 @@ +* c:\users\malli\esim-workspace\4023_test\4023_test.cir + +.include 4023.sub +x1 net-_u7-pad4_ net-_u7-pad5_ net-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ net-_u9-pad2_ ? net-_u7-pad6_ net-_u9-pad1_ net-_u9-pad3_ net-_u10-pad6_ net-_u10-pad5_ net-_u10-pad4_ ? 4023 +* u8 a2 b2 c2 net-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ adc_bridge_3 +* u7 a1 b1 c1 net-_u7-pad4_ net-_u7-pad5_ net-_u7-pad6_ adc_bridge_3 +* u10 a3 b3 c3 net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ adc_bridge_3 +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ q1 q2 q3 dac_bridge_3 +v1 a1 gnd dc 0 +v2 b1 gnd dc 5 +v3 c1 gnd dc 0 +v4 a2 gnd dc 5 +v5 b2 gnd dc 0 +v6 c2 gnd dc 0 +v7 a3 gnd dc 5 +v8 b3 gnd dc 5 +v9 c3 gnd dc 0 +* u16 b3 plot_v1 +* u12 a3 plot_v1 +* u14 c3 plot_v1 +* u2 b2 plot_v1 +* u5 c2 plot_v1 +* u4 a2 plot_v1 +* u3 c1 plot_v1 +* u6 a1 plot_v1 +* u1 b1 plot_v1 +* u13 q3 plot_v1 +* u15 q2 plot_v1 +* u11 q1 plot_v1 +a1 [a2 b2 c2 ] [net-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ ] u8 +a2 [a1 b1 c1 ] [net-_u7-pad4_ net-_u7-pad5_ net-_u7-pad6_ ] u7 +a3 [a3 b3 c3 ] [net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ ] u10 +a4 [net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ ] [q1 q2 q3 ] u9 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u8 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u7 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u10 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge +.model u9 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(b3) +plot v(a3) +plot v(c3) +plot v(b2) +plot v(c2) +plot v(a2) +plot v(c1) +plot v(a1) +plot v(b1) +plot v(q3) +plot v(q2) +plot v(q1) +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro new file mode 100644 index 00000000..e4c3c722 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro @@ -0,0 +1,45 @@ +update=06/01/19 15:31:12
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.proj b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.proj new file mode 100644 index 00000000..eb21693a --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.proj @@ -0,0 +1 @@ +schematicFile 4023_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch new file mode 100644 index 00000000..e8be1afc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch @@ -0,0 +1,578 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_Input_NAND_Characteristics-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4023 X1 +U 1 1 5CF24CF9 +P 5300 3900 +F 0 "X1" H 5300 3800 60 0000 C CNN +F 1 "4023" H 5300 4000 60 0000 C CNN +F 2 "" H 5300 3900 60 0000 C CNN +F 3 "" H 5300 3900 60 0000 C CNN + 1 5300 3900 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U8 +U 1 1 5CF24D5D +P 3450 4500 +F 0 "U8" H 3450 4500 60 0000 C CNN +F 1 "adc_bridge_3" H 3450 4650 60 0000 C CNN +F 2 "" H 3450 4500 60 0000 C CNN +F 3 "" H 3450 4500 60 0000 C CNN + 1 3450 4500 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U7 +U 1 1 5CF24DB6 +P 3400 2850 +F 0 "U7" H 3400 2850 60 0000 C CNN +F 1 "adc_bridge_3" H 3400 3000 60 0000 C CNN +F 2 "" H 3400 2850 60 0000 C CNN +F 3 "" H 3400 2850 60 0000 C CNN + 1 3400 2850 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U10 +U 1 1 5CF24DFF +P 7000 3750 +F 0 "U10" H 7000 3750 60 0000 C CNN +F 1 "adc_bridge_3" H 7000 3900 60 0000 C CNN +F 2 "" H 7000 3750 60 0000 C CNN +F 3 "" H 7000 3750 60 0000 C CNN + 1 7000 3750 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_3 U9 +U 1 1 5CF24ECA +P 6800 5750 +F 0 "U9" H 6800 5750 60 0000 C CNN +F 1 "dac_bridge_3" H 6800 5900 60 0000 C CNN +F 2 "" H 6800 5750 60 0000 C CNN +F 3 "" H 6800 5750 60 0000 C CNN + 1 6800 5750 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5CF24F1F +P 1700 2350 +F 0 "v1" H 1500 2450 60 0000 C CNN +F 1 "DC" H 1500 2300 60 0000 C CNN +F 2 "R1" H 1400 2350 60 0000 C CNN +F 3 "" H 1700 2350 60 0000 C CNN + 1 1700 2350 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 5CF24F90 +P 1700 2900 +F 0 "v2" H 1500 3000 60 0000 C CNN +F 1 "DC" H 1500 2850 60 0000 C CNN +F 2 "R1" H 1400 2900 60 0000 C CNN +F 3 "" H 1700 2900 60 0000 C CNN + 1 1700 2900 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 5CF24FC7 +P 1700 3450 +F 0 "v3" H 1500 3550 60 0000 C CNN +F 1 "DC" H 1500 3400 60 0000 C CNN +F 2 "R1" H 1400 3450 60 0000 C CNN +F 3 "" H 1700 3450 60 0000 C CNN + 1 1700 3450 + 0 1 1 0 +$EndComp +$Comp +L DC v4 +U 1 1 5CF25001 +P 1750 4000 +F 0 "v4" H 1550 4100 60 0000 C CNN +F 1 "DC" H 1550 3950 60 0000 C CNN +F 2 "R1" H 1450 4000 60 0000 C CNN +F 3 "" H 1750 4000 60 0000 C CNN + 1 1750 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v5 +U 1 1 5CF25044 +P 1750 4550 +F 0 "v5" H 1550 4650 60 0000 C CNN +F 1 "DC" H 1550 4500 60 0000 C CNN +F 2 "R1" H 1450 4550 60 0000 C CNN +F 3 "" H 1750 4550 60 0000 C CNN + 1 1750 4550 + 0 1 1 0 +$EndComp +$Comp +L DC v6 +U 1 1 5CF25082 +P 1750 5050 +F 0 "v6" H 1550 5150 60 0000 C CNN +F 1 "DC" H 1550 5000 60 0000 C CNN +F 2 "R1" H 1450 5050 60 0000 C CNN +F 3 "" H 1750 5050 60 0000 C CNN + 1 1750 5050 + 0 1 1 0 +$EndComp +Wire Wire Line + 2800 2800 2800 2350 +Wire Wire Line + 2800 2350 2150 2350 +Wire Wire Line + 2150 2900 2800 2900 +Wire Wire Line + 2150 3450 2800 3450 +Wire Wire Line + 2800 3450 2800 3000 +Wire Wire Line + 2200 4000 2850 4000 +Wire Wire Line + 2850 3900 2850 4450 +Wire Wire Line + 2850 4550 2200 4550 +Wire Wire Line + 2200 5050 2850 5050 +Wire Wire Line + 2850 5050 2850 4650 +Wire Wire Line + 900 5050 1300 5050 +Wire Wire Line + 900 2350 900 5050 +Wire Wire Line + 900 2350 1250 2350 +Wire Wire Line + 1250 2900 900 2900 +Connection ~ 900 2900 +Wire Wire Line + 1250 3450 900 3450 +Connection ~ 900 3450 +Wire Wire Line + 1300 4000 900 4000 +Connection ~ 900 4000 +Wire Wire Line + 1300 4550 900 4550 +Connection ~ 900 4550 +Wire Wire Line + 3950 2800 4500 2800 +Wire Wire Line + 4500 2800 4500 3600 +Wire Wire Line + 4500 3600 4800 3600 +Wire Wire Line + 3950 2900 4400 2900 +Wire Wire Line + 4400 2900 4400 3700 +Wire Wire Line + 4400 3700 4800 3700 +Wire Wire Line + 3950 3000 5900 3000 +Wire Wire Line + 5900 3000 5900 4200 +Wire Wire Line + 5900 4200 5800 4200 +Wire Wire Line + 6450 3900 5800 3900 +Wire Wire Line + 5800 3800 6450 3800 +Wire Wire Line + 6450 3700 5800 3700 +Wire Wire Line + 4000 4450 4000 3800 +Wire Wire Line + 4000 3800 4800 3800 +Wire Wire Line + 4800 3900 4100 3900 +Wire Wire Line + 4100 3900 4100 4550 +Wire Wire Line + 4100 4550 4000 4550 +Wire Wire Line + 4000 4650 4200 4650 +Wire Wire Line + 4200 4650 4200 4000 +Wire Wire Line + 4200 4000 4800 4000 +Wire Wire Line + 4800 4100 4450 4100 +Wire Wire Line + 4450 4100 4450 5800 +Wire Wire Line + 4450 5800 6200 5800 +Wire Wire Line + 5800 4100 5850 4100 +Wire Wire Line + 5850 4100 5850 5700 +Wire Wire Line + 5850 5700 6200 5700 +Wire Wire Line + 5800 4000 5950 4000 +Wire Wire Line + 5950 4000 5950 5900 +Wire Wire Line + 5950 5900 6200 5900 +$Comp +L DC v7 +U 1 1 5CF25804 +P 9250 3250 +F 0 "v7" H 9050 3350 60 0000 C CNN +F 1 "DC" H 9050 3200 60 0000 C CNN +F 2 "R1" H 8950 3250 60 0000 C CNN +F 3 "" H 9250 3250 60 0000 C CNN + 1 9250 3250 + 0 -1 1 0 +$EndComp +$Comp +L DC v8 +U 1 1 5CF2580A +P 9250 3800 +F 0 "v8" H 9050 3900 60 0000 C CNN +F 1 "DC" H 9050 3750 60 0000 C CNN +F 2 "R1" H 8950 3800 60 0000 C CNN +F 3 "" H 9250 3800 60 0000 C CNN + 1 9250 3800 + 0 -1 1 0 +$EndComp +$Comp +L DC v9 +U 1 1 5CF25810 +P 9250 4300 +F 0 "v9" H 9050 4400 60 0000 C CNN +F 1 "DC" H 9050 4250 60 0000 C CNN +F 2 "R1" H 8950 4300 60 0000 C CNN +F 3 "" H 9250 4300 60 0000 C CNN + 1 9250 4300 + 0 -1 1 0 +$EndComp +Wire Wire Line + 7600 3250 8800 3250 +Wire Wire Line + 7600 3800 8800 3800 +Wire Wire Line + 7600 4300 8800 4300 +Wire Wire Line + 10150 4300 9700 4300 +Wire Wire Line + 9700 3250 10150 3250 +Wire Wire Line + 9700 3800 10500 3800 +Wire Wire Line + 7600 3250 7600 3700 +Wire Wire Line + 7600 4300 7600 3900 +Wire Wire Line + 10150 3250 10150 4300 +Connection ~ 10150 3800 +Wire Wire Line + 10500 3800 10500 4050 +NoConn ~ 5800 3600 +NoConn ~ 4800 4200 +$Comp +L plot_v1 U16 +U 1 1 5CF25B68 +P 8450 3050 +F 0 "U16" H 8450 3550 60 0000 C CNN +F 1 "plot_v1" H 8650 3400 60 0000 C CNN +F 2 "" H 8450 3050 60 0000 C CNN +F 3 "" H 8450 3050 60 0000 C CNN + 1 8450 3050 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 5CF25BF8 +P 7750 3100 +F 0 "U12" H 7750 3600 60 0000 C CNN +F 1 "plot_v1" H 7950 3450 60 0000 C CNN +F 2 "" H 7750 3100 60 0000 C CNN +F 3 "" H 7750 3100 60 0000 C CNN + 1 7750 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U14 +U 1 1 5CF25C4E +P 8050 4300 +F 0 "U14" H 8050 4800 60 0000 C CNN +F 1 "plot_v1" H 8250 4650 60 0000 C CNN +F 2 "" H 8050 4300 60 0000 C CNN +F 3 "" H 8050 4300 60 0000 C CNN + 1 8050 4300 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 5CF25E02 +P 2450 5100 +F 0 "U2" H 2450 5600 60 0000 C CNN +F 1 "plot_v1" H 2650 5450 60 0000 C CNN +F 2 "" H 2450 5100 60 0000 C CNN +F 3 "" H 2450 5100 60 0000 C CNN + 1 2450 5100 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5CF25F10 +P 3000 5000 +F 0 "U5" H 3000 5500 60 0000 C CNN +F 1 "plot_v1" H 3200 5350 60 0000 C CNN +F 2 "" H 3000 5000 60 0000 C CNN +F 3 "" H 3000 5000 60 0000 C CNN + 1 3000 5000 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5CF25F95 +P 2950 3900 +F 0 "U4" H 2950 4400 60 0000 C CNN +F 1 "plot_v1" H 3150 4250 60 0000 C CNN +F 2 "" H 2950 3900 60 0000 C CNN +F 3 "" H 2950 3900 60 0000 C CNN + 1 2950 3900 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5CF25FFB +P 2850 3250 +F 0 "U3" H 2850 3750 60 0000 C CNN +F 1 "plot_v1" H 3050 3600 60 0000 C CNN +F 2 "" H 2850 3250 60 0000 C CNN +F 3 "" H 2850 3250 60 0000 C CNN + 1 2850 3250 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5CF260BA +P 3100 2400 +F 0 "U6" H 3100 2900 60 0000 C CNN +F 1 "plot_v1" H 3300 2750 60 0000 C CNN +F 2 "" H 3100 2400 60 0000 C CNN +F 3 "" H 3100 2400 60 0000 C CNN + 1 3100 2400 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 5CF26164 +P 2400 2300 +F 0 "U1" H 2400 2800 60 0000 C CNN +F 1 "plot_v1" H 2600 2650 60 0000 C CNN +F 2 "" H 2400 2300 60 0000 C CNN +F 3 "" H 2400 2300 60 0000 C CNN + 1 2400 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 5CF261BC +P 700 3900 +F 0 "#PWR01" H 700 3650 50 0001 C CNN +F 1 "eSim_GND" H 700 3750 50 0000 C CNN +F 2 "" H 700 3900 50 0001 C CNN +F 3 "" H 700 3900 50 0001 C CNN + 1 700 3900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5CF262FB +P 700 3700 +F 0 "#FLG02" H 700 3795 50 0001 C CNN +F 1 "PWR_FLAG" H 700 3880 50 0000 C CNN +F 2 "" H 700 3700 50 0000 C CNN +F 3 "" H 700 3700 50 0000 C CNN + 1 700 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 700 3700 700 3900 +Wire Wire Line + 700 3800 900 3800 +Connection ~ 900 3800 +Connection ~ 700 3800 +Wire Wire Line + 3100 2200 3100 2450 +Wire Wire Line + 3100 2450 2800 2450 +Connection ~ 2800 2450 +Wire Wire Line + 2400 2100 2400 2900 +Connection ~ 2400 2900 +Wire Wire Line + 3050 3250 2800 3250 +Connection ~ 2800 3250 +Wire Wire Line + 3150 3900 2850 3900 +Connection ~ 2850 4000 +Wire Wire Line + 3200 5000 2850 5000 +Connection ~ 2850 5000 +Wire Wire Line + 2450 5300 2450 4550 +Connection ~ 2450 4550 +Wire Wire Line + 7750 2900 7750 3250 +Connection ~ 7750 3250 +Wire Wire Line + 8450 2850 8450 3800 +Connection ~ 8450 3800 +Wire Wire Line + 8050 4500 8050 4300 +Connection ~ 8050 4300 +$Comp +L eSim_GND #PWR03 +U 1 1 5CF26B7B +P 10500 4050 +F 0 "#PWR03" H 10500 3800 50 0001 C CNN +F 1 "eSim_GND" H 10500 3900 50 0000 C CNN +F 2 "" H 10500 4050 50 0001 C CNN +F 3 "" H 10500 4050 50 0001 C CNN + 1 10500 4050 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U13 +U 1 1 5CF26CF6 +P 7900 6100 +F 0 "U13" H 7900 6600 60 0000 C CNN +F 1 "plot_v1" H 8100 6450 60 0000 C CNN +F 2 "" H 7900 6100 60 0000 C CNN +F 3 "" H 7900 6100 60 0000 C CNN + 1 7900 6100 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U15 +U 1 1 5CF26DF2 +P 8250 5700 +F 0 "U15" H 8250 6200 60 0000 C CNN +F 1 "plot_v1" H 8450 6050 60 0000 C CNN +F 2 "" H 8250 5700 60 0000 C CNN +F 3 "" H 8250 5700 60 0000 C CNN + 1 8250 5700 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 5CF26E57 +P 7600 5200 +F 0 "U11" H 7600 5700 60 0000 C CNN +F 1 "plot_v1" H 7800 5550 60 0000 C CNN +F 2 "" H 7600 5200 60 0000 C CNN +F 3 "" H 7600 5200 60 0000 C CNN + 1 7600 5200 + 0 1 1 0 +$EndComp +Wire Wire Line + 7800 5200 7350 5200 +Wire Wire Line + 7350 5200 7350 5700 +Wire Wire Line + 7350 5800 7850 5800 +Wire Wire Line + 7850 5800 7850 5700 +Wire Wire Line + 7850 5700 8450 5700 +Wire Wire Line + 7350 5900 7650 5900 +Wire Wire Line + 7650 5900 7650 6100 +Wire Wire Line + 7450 6100 8100 6100 +Text GLabel 7200 5300 0 60 Input ~ 0 +q1 +Text GLabel 7700 5650 1 60 Input ~ 0 +q2 +Text GLabel 7450 6100 0 60 Input ~ 0 +q3 +Text GLabel 7900 4400 0 60 Input ~ 0 +c3 +Text GLabel 8300 3500 0 60 Input ~ 0 +b3 +Text GLabel 7600 3050 0 60 Input ~ 0 +a3 +Wire Wire Line + 7550 3050 7750 3050 +Connection ~ 7750 3050 +Wire Wire Line + 8300 3500 8450 3500 +Connection ~ 8450 3500 +Wire Wire Line + 7900 4400 8050 4400 +Connection ~ 8050 4400 +Wire Wire Line + 7200 5300 7350 5300 +Connection ~ 7350 5300 +Wire Wire Line + 7700 5650 7700 5800 +Connection ~ 7700 5800 +Connection ~ 7650 6100 +Text GLabel 2350 4750 0 60 Input ~ 0 +b2 +Text GLabel 3050 5150 3 60 Input ~ 0 +c2 +Text GLabel 3000 4000 3 60 Input ~ 0 +a2 +Text GLabel 2950 3400 3 60 Input ~ 0 +c1 +Text GLabel 2250 2650 0 60 Input ~ 0 +b1 +Text GLabel 3000 2300 0 60 Input ~ 0 +a1 +Wire Wire Line + 3000 2300 3100 2300 +Connection ~ 3100 2300 +Wire Wire Line + 2250 2650 2400 2650 +Connection ~ 2400 2650 +Wire Wire Line + 2950 3400 2950 3250 +Connection ~ 2950 3250 +Wire Wire Line + 3000 4000 3000 3900 +Connection ~ 3000 3900 +Wire Wire Line + 2350 4750 2450 4750 +Connection ~ 2450 4750 +Wire Wire Line + 3050 5150 3050 5000 +Connection ~ 3050 5000 +Text Notes 4500 6300 0 118 Italic 24 +IC 4023 Characteristics +$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics_Previous_Values.xml new file mode 100644 index 00000000..50f05f7b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">5</field1></v4><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v7 name="Source type">dc<field1 name="Value">5</field1></v7><v8 name="Source type">dc<field1 name="Value">5</field1></v8><v9 name="Source type">dc<field1 name="Value">0</field1></v9></source><model><u8 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u8><u7 name="type">adc_bridge<field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter value for in_low (default=1.0)" /></u7><u10 name="type">adc_bridge<field9 name="Enter Fall Delay (default=1.0e-9)" /><field10 name="Enter value for in_high (default=2.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter value for in_low (default=1.0)" /></u10><u9 name="type">dac_bridge<field13 name="Enter value for input load (default=1.0e-12)" /><field14 name="Enter value for out_low (default=0.0)" /><field15 name="Enter value for out_high (default=5.0)" /><field16 name="Enter the Rise Time (default=1.0e-9)" /><field17 name="Enter the Fall Time (default=1.0e-9)" /><field18 name="Enter value for out_undef (default=0.5)" /></u9></model><devicemodel /><subcircuit><x1><field>/home/saurabh/Pilot_Related/New_Installer/eSim-1.1.2/src/SubcircuitLibrary/4023</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023-cache.lib b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023-cache.lib new file mode 100644 index 00000000..e7a4d719 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.cir b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.cir new file mode 100644 index 00000000..3c228446 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.cir @@ -0,0 +1,17 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X3 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and
+U4 Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
+U3 Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.cir.out b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.cir.out new file mode 100644 index 00000000..09b30237 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.cir.out @@ -0,0 +1,28 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
+
+.include 3_and.sub
+x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
+* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter
+a1 net-_u4-pad1_ net-_u1-pad10_ u4
+a2 net-_u3-pad1_ net-_u1-pad6_ u3
+a3 net-_u2-pad1_ net-_u1-pad9_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.pro b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.pro new file mode 100644 index 00000000..6a83e3e3 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:32:35
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.sch b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.sch new file mode 100644 index 00000000..ed64345f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.sch @@ -0,0 +1,309 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X3
+U 1 1 5CF0FA82
+P 4800 2500
+F 0 "X3" H 4900 2450 60 0000 C CNN
+F 1 "3_and" H 4950 2650 60 0000 C CNN
+F 2 "" H 4800 2500 60 0000 C CNN
+F 3 "" H 4800 2500 60 0000 C CNN
+ 1 4800 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 5CF0FB13
+P 6150 2450
+F 0 "U4" H 6150 2350 60 0000 C CNN
+F 1 "d_inverter" H 6150 2600 60 0000 C CNN
+F 2 "" H 6200 2400 60 0000 C CNN
+F 3 "" H 6200 2400 60 0000 C CNN
+ 1 6150 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CF0FB34
+P 3100 1950
+F 0 "U1" H 3150 2050 30 0000 C CNN
+F 1 "PORT" H 3100 1950 30 0000 C CNN
+F 2 "" H 3100 1950 60 0000 C CNN
+F 3 "" H 3100 1950 60 0000 C CNN
+ 11 3100 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CF0FB90
+P 3100 2350
+F 0 "U1" H 3150 2450 30 0000 C CNN
+F 1 "PORT" H 3100 2350 30 0000 C CNN
+F 2 "" H 3100 2350 60 0000 C CNN
+F 3 "" H 3100 2350 60 0000 C CNN
+ 12 3100 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CF0FBB8
+P 3100 2750
+F 0 "U1" H 3150 2850 30 0000 C CNN
+F 1 "PORT" H 3100 2750 30 0000 C CNN
+F 2 "" H 3100 2750 60 0000 C CNN
+F 3 "" H 3100 2750 60 0000 C CNN
+ 13 3100 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CF0FBED
+P 7800 2450
+F 0 "U1" H 7850 2550 30 0000 C CNN
+F 1 "PORT" H 7800 2450 30 0000 C CNN
+F 2 "" H 7800 2450 60 0000 C CNN
+F 3 "" H 7800 2450 60 0000 C CNN
+ 10 7800 2450
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7550 2450 6450 2450
+Wire Wire Line
+ 5850 2450 5300 2450
+Wire Wire Line
+ 4450 2350 4450 1950
+Wire Wire Line
+ 4450 1950 3350 1950
+Wire Wire Line
+ 4450 2450 4100 2450
+Wire Wire Line
+ 4100 2450 4100 2350
+Wire Wire Line
+ 4100 2350 3350 2350
+Wire Wire Line
+ 3350 2750 3950 2750
+Wire Wire Line
+ 3950 2750 3950 2550
+Wire Wire Line
+ 3950 2550 4450 2550
+$Comp
+L 3_and X2
+U 1 1 5CF0FF35
+P 4700 3800
+F 0 "X2" H 4800 3750 60 0000 C CNN
+F 1 "3_and" H 4850 3950 60 0000 C CNN
+F 2 "" H 4700 3800 60 0000 C CNN
+F 3 "" H 4700 3800 60 0000 C CNN
+ 1 4700 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 5CF0FF3B
+P 6050 3750
+F 0 "U3" H 6050 3650 60 0000 C CNN
+F 1 "d_inverter" H 6050 3900 60 0000 C CNN
+F 2 "" H 6100 3700 60 0000 C CNN
+F 3 "" H 6100 3700 60 0000 C CNN
+ 1 6050 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CF0FF41
+P 3000 3250
+F 0 "U1" H 3050 3350 30 0000 C CNN
+F 1 "PORT" H 3000 3250 30 0000 C CNN
+F 2 "" H 3000 3250 60 0000 C CNN
+F 3 "" H 3000 3250 60 0000 C CNN
+ 4 3000 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CF0FF47
+P 3000 3650
+F 0 "U1" H 3050 3750 30 0000 C CNN
+F 1 "PORT" H 3000 3650 30 0000 C CNN
+F 2 "" H 3000 3650 60 0000 C CNN
+F 3 "" H 3000 3650 60 0000 C CNN
+ 5 3000 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CF0FF4D
+P 3000 4050
+F 0 "U1" H 3050 4150 30 0000 C CNN
+F 1 "PORT" H 3000 4050 30 0000 C CNN
+F 2 "" H 3000 4050 60 0000 C CNN
+F 3 "" H 3000 4050 60 0000 C CNN
+ 3 3000 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CF0FF53
+P 7700 3750
+F 0 "U1" H 7750 3850 30 0000 C CNN
+F 1 "PORT" H 7700 3750 30 0000 C CNN
+F 2 "" H 7700 3750 60 0000 C CNN
+F 3 "" H 7700 3750 60 0000 C CNN
+ 6 7700 3750
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7450 3750 6350 3750
+Wire Wire Line
+ 5750 3750 5200 3750
+Wire Wire Line
+ 4350 3650 4350 3250
+Wire Wire Line
+ 4350 3250 3250 3250
+Wire Wire Line
+ 4350 3750 4000 3750
+Wire Wire Line
+ 4000 3750 4000 3650
+Wire Wire Line
+ 4000 3650 3250 3650
+Wire Wire Line
+ 3250 4050 3850 4050
+Wire Wire Line
+ 3850 4050 3850 3850
+Wire Wire Line
+ 3850 3850 4350 3850
+$Comp
+L 3_and X1
+U 1 1 5CF100B9
+P 4650 5100
+F 0 "X1" H 4750 5050 60 0000 C CNN
+F 1 "3_and" H 4800 5250 60 0000 C CNN
+F 2 "" H 4650 5100 60 0000 C CNN
+F 3 "" H 4650 5100 60 0000 C CNN
+ 1 4650 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 5CF100BF
+P 6000 5050
+F 0 "U2" H 6000 4950 60 0000 C CNN
+F 1 "d_inverter" H 6000 5200 60 0000 C CNN
+F 2 "" H 6050 5000 60 0000 C CNN
+F 3 "" H 6050 5000 60 0000 C CNN
+ 1 6000 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CF100C5
+P 2950 4550
+F 0 "U1" H 3000 4650 30 0000 C CNN
+F 1 "PORT" H 2950 4550 30 0000 C CNN
+F 2 "" H 2950 4550 60 0000 C CNN
+F 3 "" H 2950 4550 60 0000 C CNN
+ 1 2950 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CF100CB
+P 2950 4950
+F 0 "U1" H 3000 5050 30 0000 C CNN
+F 1 "PORT" H 2950 4950 30 0000 C CNN
+F 2 "" H 2950 4950 60 0000 C CNN
+F 3 "" H 2950 4950 60 0000 C CNN
+ 2 2950 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CF100D1
+P 2950 5350
+F 0 "U1" H 3000 5450 30 0000 C CNN
+F 1 "PORT" H 2950 5350 30 0000 C CNN
+F 2 "" H 2950 5350 60 0000 C CNN
+F 3 "" H 2950 5350 60 0000 C CNN
+ 8 2950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CF100D7
+P 7650 5050
+F 0 "U1" H 7700 5150 30 0000 C CNN
+F 1 "PORT" H 7650 5050 30 0000 C CNN
+F 2 "" H 7650 5050 60 0000 C CNN
+F 3 "" H 7650 5050 60 0000 C CNN
+ 9 7650 5050
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7400 5050 6300 5050
+Wire Wire Line
+ 5700 5050 5150 5050
+Wire Wire Line
+ 4300 4950 4300 4550
+Wire Wire Line
+ 4300 4550 3200 4550
+Wire Wire Line
+ 4300 5050 3950 5050
+Wire Wire Line
+ 3950 5050 3950 4950
+Wire Wire Line
+ 3950 4950 3200 4950
+Wire Wire Line
+ 3200 5350 3800 5350
+Wire Wire Line
+ 3800 5350 3800 5150
+Wire Wire Line
+ 3800 5150 4300 5150
+$Comp
+L PORT U1
+U 7 1 5CF101BF
+P 9950 3350
+F 0 "U1" H 10000 3450 30 0000 C CNN
+F 1 "PORT" H 9950 3350 30 0000 C CNN
+F 2 "" H 9950 3350 60 0000 C CNN
+F 3 "" H 9950 3350 60 0000 C CNN
+ 7 9950 3350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CF1025C
+P 9950 3900
+F 0 "U1" H 10000 4000 30 0000 C CNN
+F 1 "PORT" H 9950 3900 30 0000 C CNN
+F 2 "" H 9950 3900 60 0000 C CNN
+F 3 "" H 9950 3900 60 0000 C CNN
+ 14 9950 3900
+ -1 0 0 1
+$EndComp
+NoConn ~ 9700 3350
+NoConn ~ 9700 3900
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.sub b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.sub new file mode 100644 index 00000000..049fad06 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023.sub @@ -0,0 +1,22 @@ +* Subcircuit 4023
+.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
+.include 3_and.sub
+x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
+* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter
+a1 net-_u4-pad1_ net-_u1-pad10_ u4
+a2 net-_u3-pad1_ net-_u1-pad6_ u3
+a3 net-_u2-pad1_ net-_u1-pad9_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4023
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023_Previous_Values.xml new file mode 100644 index 00000000..ad900de2 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/4023_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002-cache.lib b/Examples/Analysis_Of_Digital_IC/4002_test/4002-cache.lib new file mode 100644 index 00000000..dd565db9 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir b/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir new file mode 100644 index 00000000..36ad9450 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or
+U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or
+U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir.out b/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir.out new file mode 100644 index 00000000..ca055749 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro b/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro new file mode 100644 index 00000000..e7859256 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.pro @@ -0,0 +1,44 @@ +update=05/31/19 09:35:41
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
+LibName11=power
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.sch b/Examples/Analysis_Of_Digital_IC/4002_test/4002.sch new file mode 100644 index 00000000..38f453cd --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.sch @@ -0,0 +1,315 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5CEE059A
+P 4750 2900
+F 0 "U2" H 4750 2900 60 0000 C CNN
+F 1 "d_or" H 4750 3000 60 0000 C CNN
+F 2 "" H 4750 2900 60 0000 C CNN
+F 3 "" H 4750 2900 60 0000 C CNN
+ 1 4750 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5CEE0629
+P 4750 3450
+F 0 "U3" H 4750 3450 60 0000 C CNN
+F 1 "d_or" H 4750 3550 60 0000 C CNN
+F 2 "" H 4750 3450 60 0000 C CNN
+F 3 "" H 4750 3450 60 0000 C CNN
+ 1 4750 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 5CEE0663
+P 6000 3100
+F 0 "U6" H 6000 3100 60 0000 C CNN
+F 1 "d_nor" H 6050 3200 60 0000 C CNN
+F 2 "" H 6000 3100 60 0000 C CNN
+F 3 "" H 6000 3100 60 0000 C CNN
+ 1 6000 3100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5200 2850 5400 2850
+Wire Wire Line
+ 5400 2850 5400 3000
+Wire Wire Line
+ 5400 3000 5550 3000
+Wire Wire Line
+ 5200 3400 5400 3400
+Wire Wire Line
+ 5400 3400 5400 3100
+Wire Wire Line
+ 5400 3100 5550 3100
+Wire Wire Line
+ 5650 5350 6050 5350
+Wire Wire Line
+ 5650 5550 6050 5550
+Wire Wire Line
+ 5650 5800 6050 5800
+Wire Wire Line
+ 5650 6000 6050 6000
+NoConn ~ 5650 5350
+NoConn ~ 5650 5550
+NoConn ~ 5650 5800
+NoConn ~ 5650 6000
+$Comp
+L PORT U1
+U 2 1 5CEE1C41
+P 3850 2800
+F 0 "U1" H 3900 2900 30 0000 C CNN
+F 1 "PORT" H 3850 2800 30 0000 C CNN
+F 2 "" H 3850 2800 60 0000 C CNN
+F 3 "" H 3850 2800 60 0000 C CNN
+ 2 3850 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CEE22EE
+P 3900 3050
+F 0 "U1" H 3950 3150 30 0000 C CNN
+F 1 "PORT" H 3900 3050 30 0000 C CNN
+F 2 "" H 3900 3050 60 0000 C CNN
+F 3 "" H 3900 3050 60 0000 C CNN
+ 3 3900 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CEE2322
+P 3900 3250
+F 0 "U1" H 3950 3350 30 0000 C CNN
+F 1 "PORT" H 3900 3250 30 0000 C CNN
+F 2 "" H 3900 3250 60 0000 C CNN
+F 3 "" H 3900 3250 60 0000 C CNN
+ 5 3900 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CEE2351
+P 3900 3550
+F 0 "U1" H 3950 3650 30 0000 C CNN
+F 1 "PORT" H 3900 3550 30 0000 C CNN
+F 2 "" H 3900 3550 60 0000 C CNN
+F 3 "" H 3900 3550 60 0000 C CNN
+ 4 3900 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE2387
+P 6950 3050
+F 0 "U1" H 7000 3150 30 0000 C CNN
+F 1 "PORT" H 6950 3050 30 0000 C CNN
+F 2 "" H 6950 3050 60 0000 C CNN
+F 3 "" H 6950 3050 60 0000 C CNN
+ 1 6950 3050
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4100 2800 4300 2800
+Wire Wire Line
+ 4150 3050 4150 2900
+Wire Wire Line
+ 4150 2900 4300 2900
+Wire Wire Line
+ 4150 3250 4300 3250
+Wire Wire Line
+ 4300 3250 4300 3350
+Wire Wire Line
+ 4150 3550 4150 3450
+Wire Wire Line
+ 4150 3450 4300 3450
+Wire Wire Line
+ 6700 3050 6450 3050
+$Comp
+L d_or U4
+U 1 1 5CEE4ED7
+P 4900 4100
+F 0 "U4" H 4900 4100 60 0000 C CNN
+F 1 "d_or" H 4900 4200 60 0000 C CNN
+F 2 "" H 4900 4100 60 0000 C CNN
+F 3 "" H 4900 4100 60 0000 C CNN
+ 1 4900 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U5
+U 1 1 5CEE4EDD
+P 4900 4650
+F 0 "U5" H 4900 4650 60 0000 C CNN
+F 1 "d_or" H 4900 4750 60 0000 C CNN
+F 2 "" H 4900 4650 60 0000 C CNN
+F 3 "" H 4900 4650 60 0000 C CNN
+ 1 4900 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 5CEE4EE3
+P 6150 4300
+F 0 "U7" H 6150 4300 60 0000 C CNN
+F 1 "d_nor" H 6200 4400 60 0000 C CNN
+F 2 "" H 6150 4300 60 0000 C CNN
+F 3 "" H 6150 4300 60 0000 C CNN
+ 1 6150 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5350 4050 5550 4050
+Wire Wire Line
+ 5550 4050 5550 4200
+Wire Wire Line
+ 5550 4200 5700 4200
+Wire Wire Line
+ 5350 4600 5550 4600
+Wire Wire Line
+ 5550 4600 5550 4300
+Wire Wire Line
+ 5550 4300 5700 4300
+$Comp
+L PORT U1
+U 9 1 5CEE4EEF
+P 4000 4000
+F 0 "U1" H 4050 4100 30 0000 C CNN
+F 1 "PORT" H 4000 4000 30 0000 C CNN
+F 2 "" H 4000 4000 60 0000 C CNN
+F 3 "" H 4000 4000 60 0000 C CNN
+ 9 4000 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE4EF5
+P 4050 4250
+F 0 "U1" H 4100 4350 30 0000 C CNN
+F 1 "PORT" H 4050 4250 30 0000 C CNN
+F 2 "" H 4050 4250 60 0000 C CNN
+F 3 "" H 4050 4250 60 0000 C CNN
+ 10 4050 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE4EFB
+P 4050 4450
+F 0 "U1" H 4100 4550 30 0000 C CNN
+F 1 "PORT" H 4050 4450 30 0000 C CNN
+F 2 "" H 4050 4450 60 0000 C CNN
+F 3 "" H 4050 4450 60 0000 C CNN
+ 11 4050 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE4F01
+P 4050 4750
+F 0 "U1" H 4100 4850 30 0000 C CNN
+F 1 "PORT" H 4050 4750 30 0000 C CNN
+F 2 "" H 4050 4750 60 0000 C CNN
+F 3 "" H 4050 4750 60 0000 C CNN
+ 12 4050 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CEE4F07
+P 7100 4250
+F 0 "U1" H 7150 4350 30 0000 C CNN
+F 1 "PORT" H 7100 4250 30 0000 C CNN
+F 2 "" H 7100 4250 60 0000 C CNN
+F 3 "" H 7100 4250 60 0000 C CNN
+ 13 7100 4250
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4250 4000 4450 4000
+Wire Wire Line
+ 4300 4250 4300 4100
+Wire Wire Line
+ 4300 4100 4450 4100
+Wire Wire Line
+ 4300 4450 4450 4450
+Wire Wire Line
+ 4450 4450 4450 4550
+Wire Wire Line
+ 4300 4750 4300 4650
+Wire Wire Line
+ 4300 4650 4450 4650
+Wire Wire Line
+ 6850 4250 6600 4250
+$Comp
+L PORT U1
+U 6 1 5CEE51A5
+P 6300 5350
+F 0 "U1" H 6350 5450 30 0000 C CNN
+F 1 "PORT" H 6300 5350 30 0000 C CNN
+F 2 "" H 6300 5350 60 0000 C CNN
+F 3 "" H 6300 5350 60 0000 C CNN
+ 6 6300 5350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CEE522C
+P 6300 5550
+F 0 "U1" H 6350 5650 30 0000 C CNN
+F 1 "PORT" H 6300 5550 30 0000 C CNN
+F 2 "" H 6300 5550 60 0000 C CNN
+F 3 "" H 6300 5550 60 0000 C CNN
+ 7 6300 5550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CEE5276
+P 6300 5800
+F 0 "U1" H 6350 5900 30 0000 C CNN
+F 1 "PORT" H 6300 5800 30 0000 C CNN
+F 2 "" H 6300 5800 60 0000 C CNN
+F 3 "" H 6300 5800 60 0000 C CNN
+ 8 6300 5800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CEE52C5
+P 6300 6000
+F 0 "U1" H 6350 6100 30 0000 C CNN
+F 1 "PORT" H 6300 6000 30 0000 C CNN
+F 2 "" H 6300 6000 60 0000 C CNN
+F 3 "" H 6300 6000 60 0000 C CNN
+ 14 6300 6000
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002.sub b/Examples/Analysis_Of_Digital_IC/4002_test/4002.sub new file mode 100644 index 00000000..522ba7ae --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002.sub @@ -0,0 +1,30 @@ +* Subcircuit 4002
+.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4002
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4002_test/4002_Previous_Values.xml new file mode 100644 index 00000000..75360e5e --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib new file mode 100644 index 00000000..53c89e01 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib @@ -0,0 +1,140 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# IC_4002
+#
+DEF IC_4002 X 0 40 Y Y 1 F N
+F0 "X" 0 150 60 H V C CNN
+F1 "IC_4002" 0 0 60 H V C CNN
+F2 "" 50 -150 60 H V C CNN
+F3 "" 50 -150 60 H V C CNN
+DRAW
+S -250 350 250 -400 0 1 0 N
+X 1Y 1 -450 250 200 R 50 50 1 1 O
+X 1A 2 -450 150 200 R 50 50 1 1 I
+X 1B 3 -450 50 200 R 50 50 1 1 I
+X 1C 4 -450 -50 200 R 50 50 1 1 I
+X 1D 5 -450 -150 200 R 50 50 1 1 I
+X NC 6 -450 -250 200 R 50 50 1 1 I
+X GND 7 -450 -350 200 R 50 50 1 1 I
+X NC 8 450 -350 200 L 50 50 1 1 I
+X 2A 9 450 -250 200 L 50 50 1 1 I
+X 2B 10 450 -150 200 L 50 50 1 1 I
+X 2C 11 450 -50 200 L 50 50 1 1 I
+X 2D 12 450 50 200 L 50 50 1 1 I
+X 2Y 13 450 150 200 L 50 50 1 1 O
+X VCC 14 450 250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir new file mode 100644 index 00000000..a667c576 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir @@ -0,0 +1,42 @@ +* C:\Users\Bhargav\eSim-Workspace\4002_test\4002_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 06:09:49
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U2-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ ? ? ? Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U2-Pad2_ ? IC_4002
+U1 Net-_R1-Pad2_ Net-_R2-Pad2_ Net-_R3-Pad2_ Net-_R4-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ adc_bridge_4
+U3 Net-_R10-Pad1_ Net-_R9-Pad1_ Net-_R8-Pad1_ Net-_R7-Pad1_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ adc_bridge_4
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ out1 out2 dac_bridge_2
+R5 out1 GND 1k
+R6 out2 GND 1k
+U9 out1 plot_v1
+U8 out2 plot_v1
+U13 v8 plot_v1
+U10 v7 plot_v1
+U11 v6 plot_v1
+U12 v5 plot_v1
+R10 Net-_R10-Pad1_ v8 1k
+R9 Net-_R9-Pad1_ v7 1k
+R8 Net-_R8-Pad1_ v6 1k
+R7 Net-_R7-Pad1_ v5 1k
+v6 v7 GND DC
+v5 v8 GND DC
+v8 v5 GND DC
+v7 v6 GND DC
+U7 v4 plot_v1
+U4 v3 plot_v1
+U6 v2 plot_v1
+U5 v1 plot_v1
+R4 v4 Net-_R4-Pad2_ 1k
+R3 v3 Net-_R3-Pad2_ 1k
+R2 v2 Net-_R2-Pad2_ 1k
+R1 v1 Net-_R1-Pad2_ 1k
+v4 v4 GND DC
+v3 v3 GND DC
+v2 v2 GND DC
+v1 v1 GND DC
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir.out b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir.out new file mode 100644 index 00000000..2dbfc43b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.cir.out @@ -0,0 +1,63 @@ +* c:\users\bhargav\esim-workspace\4002_test\4002_test.cir
+
+.include 4002.sub
+x1 net-_u2-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ? ? ? net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u2-pad2_ ? 4002
+* u1 net-_r1-pad2_ net-_r2-pad2_ net-_r3-pad2_ net-_r4-pad2_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4
+* u3 net-_r10-pad1_ net-_r9-pad1_ net-_r8-pad1_ net-_r7-pad1_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4
+* u2 net-_u2-pad1_ net-_u2-pad2_ out1 out2 dac_bridge_2
+r5 out1 gnd 1k
+r6 out2 gnd 1k
+* u9 out1 plot_v1
+* u8 out2 plot_v1
+* u13 v8 plot_v1
+* u10 v7 plot_v1
+* u11 v6 plot_v1
+* u12 v5 plot_v1
+r10 net-_r10-pad1_ v8 1k
+r9 net-_r9-pad1_ v7 1k
+r8 net-_r8-pad1_ v6 1k
+r7 net-_r7-pad1_ v5 1k
+v6 v7 gnd dc 0
+v5 v8 gnd dc 0
+v8 v5 gnd dc 0
+v7 v6 gnd dc 5
+* u7 v4 plot_v1
+* u4 v3 plot_v1
+* u6 v2 plot_v1
+* u5 v1 plot_v1
+r4 v4 net-_r4-pad2_ 1k
+r3 v3 net-_r3-pad2_ 1k
+r2 v2 net-_r2-pad2_ 1k
+r1 v1 net-_r1-pad2_ 1k
+v4 v4 gnd dc 0
+v3 v3 gnd dc 0
+v2 v2 gnd dc 0
+v1 v1 gnd dc 0
+a1 [net-_r1-pad2_ net-_r2-pad2_ net-_r3-pad2_ net-_r4-pad2_ ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1
+a2 [net-_r10-pad1_ net-_r9-pad1_ net-_r8-pad1_ net-_r7-pad1_ ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3
+a3 [net-_u2-pad1_ net-_u2-pad2_ ] [out1 out2 ] u2
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u3 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out1)
+plot v(out2)
+plot v(v8)
+plot v(v7)
+plot v(v6)
+plot v(v5)
+plot v(v4)
+plot v(v3)
+plot v(v2)
+plot v(v1)
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro new file mode 100644 index 00000000..43701631 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro @@ -0,0 +1,44 @@ +update=06/01/19 05:45:01
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.proj b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.proj new file mode 100644 index 00000000..e13b6026 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.proj @@ -0,0 +1 @@ +schematicFile 4002_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch new file mode 100644 index 00000000..1cce0878 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch @@ -0,0 +1,617 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L IC_4002 X1
+U 1 1 5CF1C395
+P 5500 3400
+F 0 "X1" H 5500 3550 60 0000 C CNN
+F 1 "IC_4002" H 5500 3400 60 0000 C CNN
+F 2 "" H 5550 3250 60 0000 C CNN
+F 3 "" H 5550 3250 60 0000 C CNN
+ 1 5500 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_4 U1
+U 1 1 5CF1C610
+P 4350 3450
+F 0 "U1" H 4350 3450 60 0000 C CNN
+F 1 "adc_bridge_4" H 4350 3750 60 0000 C CNN
+F 2 "" H 4350 3450 60 0000 C CNN
+F 3 "" H 4350 3450 60 0000 C CNN
+ 1 4350 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_4 U3
+U 1 1 5CF1C67F
+P 6650 3450
+F 0 "U3" H 6650 3450 60 0000 C CNN
+F 1 "adc_bridge_4" H 6650 3750 60 0000 C CNN
+F 2 "" H 6650 3450 60 0000 C CNN
+F 3 "" H 6650 3450 60 0000 C CNN
+ 1 6650 3450
+ -1 0 0 1
+$EndComp
+$Comp
+L dac_bridge_2 U2
+U 1 1 5CF1CADD
+P 6200 2350
+F 0 "U2" H 6200 2350 60 0000 C CNN
+F 1 "dac_bridge_2" H 6250 2500 60 0000 C CNN
+F 2 "" H 6200 2350 60 0000 C CNN
+F 3 "" H 6200 2350 60 0000 C CNN
+ 1 6200 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R5
+U 1 1 5CF29F39
+P 7000 2350
+F 0 "R5" H 7050 2480 50 0000 C CNN
+F 1 "1k" H 7050 2400 50 0000 C CNN
+F 2 "" H 7050 2330 30 0000 C CNN
+F 3 "" V 7050 2400 30 0000 C CNN
+ 1 7000 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R6
+U 1 1 5CF2A627
+P 7000 2450
+F 0 "R6" H 7050 2580 50 0000 C CNN
+F 1 "1k" H 7050 2500 50 0000 C CNN
+F 2 "" H 7050 2430 30 0000 C CNN
+F 3 "" V 7050 2500 30 0000 C CNN
+ 1 7000 2450
+ 1 0 0 -1
+$EndComp
+NoConn ~ 5050 3750
+NoConn ~ 5050 3650
+NoConn ~ 5950 3750
+NoConn ~ 5950 3150
+$Comp
+L plot_v1 U9
+U 1 1 5CF2F0DA
+P 6800 2300
+F 0 "U9" H 6800 2800 60 0000 C CNN
+F 1 "plot_v1" H 7000 2650 60 0000 C CNN
+F 2 "" H 6800 2300 60 0000 C CNN
+F 3 "" H 6800 2300 60 0000 C CNN
+ 1 6800 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U8
+U 1 1 5CF2FF74
+P 6750 2350
+F 0 "U8" H 6750 2850 60 0000 C CNN
+F 1 "plot_v1" H 6950 2700 60 0000 C CNN
+F 2 "" H 6750 2350 60 0000 C CNN
+F 3 "" H 6750 2350 60 0000 C CNN
+ 1 6750 2350
+ -1 0 0 1
+$EndComp
+Text GLabel 6950 2150 2 60 Input ~ 0
+out1
+Text GLabel 6850 2500 2 60 Input ~ 0
+out2
+Wire Wire Line
+ 3750 3250 3800 3250
+Wire Wire Line
+ 3750 3350 3800 3350
+Wire Wire Line
+ 3750 3450 3800 3450
+Wire Wire Line
+ 3750 3550 3800 3550
+Wire Wire Line
+ 6100 3350 5950 3350
+Wire Wire Line
+ 6100 3450 5950 3450
+Wire Wire Line
+ 6100 3550 5950 3550
+Wire Wire Line
+ 6100 3650 5950 3650
+Wire Wire Line
+ 7250 3350 7200 3350
+Wire Wire Line
+ 7250 3450 7200 3450
+Wire Wire Line
+ 7250 3550 7200 3550
+Wire Wire Line
+ 7250 3650 7200 3650
+Wire Wire Line
+ 8700 4050 8700 2350
+Wire Wire Line
+ 4900 3250 5050 3250
+Wire Wire Line
+ 4900 3350 5050 3350
+Wire Wire Line
+ 4900 3450 5050 3450
+Wire Wire Line
+ 4900 3550 5050 3550
+Wire Wire Line
+ 5050 3150 4950 3150
+Wire Wire Line
+ 4950 3150 4950 2300
+Wire Wire Line
+ 4950 2300 5750 2300
+Wire Wire Line
+ 5950 3250 6100 3250
+Wire Wire Line
+ 6100 3250 6100 3000
+Wire Wire Line
+ 6100 3000 5150 3000
+Wire Wire Line
+ 5150 3000 5150 2400
+Wire Wire Line
+ 5150 2400 5750 2400
+Wire Wire Line
+ 6900 2300 6750 2300
+Wire Wire Line
+ 6900 2400 6750 2400
+Wire Wire Line
+ 7200 2300 7350 2300
+Wire Wire Line
+ 7350 2300 7350 2400
+Wire Wire Line
+ 7350 2400 7200 2400
+Wire Wire Line
+ 8700 2350 7350 2350
+Connection ~ 7350 2350
+Wire Wire Line
+ 2050 4050 8700 4050
+Wire Wire Line
+ 6800 2100 6800 2300
+Wire Wire Line
+ 6750 2450 6750 2550
+Wire Wire Line
+ 6850 2500 6750 2500
+Connection ~ 6750 2500
+Wire Wire Line
+ 6950 2150 6800 2150
+Connection ~ 6800 2150
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5CF4D6F1
+P 4750 3950
+F 0 "#FLG01" H 4750 4045 50 0001 C CNN
+F 1 "PWR_FLAG" H 4750 4130 50 0000 C CNN
+F 2 "" H 4750 3950 50 0000 C CNN
+F 3 "" H 4750 3950 50 0000 C CNN
+ 1 4750 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5CF4EA85
+P 4750 4150
+F 0 "#PWR02" H 4750 3900 50 0001 C CNN
+F 1 "GND" H 4750 4000 50 0000 C CNN
+F 2 "" H 4750 4150 50 0000 C CNN
+F 3 "" H 4750 4150 50 0000 C CNN
+ 1 4750 4150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4750 3950 4750 4150
+Connection ~ 4750 4050
+Connection ~ 8700 3650
+Wire Wire Line
+ 8700 3650 8650 3650
+Connection ~ 8700 3550
+Wire Wire Line
+ 8650 3550 8700 3550
+Connection ~ 8700 3450
+Wire Wire Line
+ 8650 3450 8700 3450
+Connection ~ 8700 3350
+Wire Wire Line
+ 8650 3350 8700 3350
+Wire Wire Line
+ 2050 3550 2050 4050
+Wire Wire Line
+ 3250 3850 2850 3850
+Connection ~ 7750 3700
+Wire Wire Line
+ 7800 3700 7750 3700
+Wire Wire Line
+ 7800 3750 7850 3750
+Wire Wire Line
+ 7800 3700 7800 3750
+Connection ~ 7700 3550
+Wire Wire Line
+ 7700 3800 7700 3550
+Wire Wire Line
+ 7500 3800 7700 3800
+Wire Wire Line
+ 7900 3300 7700 3300
+Wire Wire Line
+ 7900 3050 7900 3300
+Connection ~ 7650 3450
+Wire Wire Line
+ 7650 3200 7650 3450
+Wire Wire Line
+ 7400 3200 7650 3200
+Wire Wire Line
+ 7750 3750 7750 3650
+Connection ~ 7600 3550
+Wire Wire Line
+ 7600 3600 7600 3550
+Connection ~ 7600 3450
+Wire Wire Line
+ 7600 3400 7600 3450
+Connection ~ 7700 3350
+Wire Wire Line
+ 7700 3300 7700 3350
+Wire Wire Line
+ 7750 3650 7550 3650
+Wire Wire Line
+ 7550 3550 7750 3550
+Wire Wire Line
+ 7750 3450 7550 3450
+Wire Wire Line
+ 7750 3350 7550 3350
+Text GLabel 7900 3050 2 60 Input ~ 0
+v5
+Text GLabel 7400 3200 0 60 Input ~ 0
+v6
+Text GLabel 7500 3800 0 60 Input ~ 0
+v7
+Text GLabel 7850 3750 2 60 Input ~ 0
+v8
+$Comp
+L plot_v1 U13
+U 1 1 5CF460B3
+P 7750 3550
+F 0 "U13" H 7750 4050 60 0000 C CNN
+F 1 "plot_v1" H 7950 3900 60 0000 C CNN
+F 2 "" H 7750 3550 60 0000 C CNN
+F 3 "" H 7750 3550 60 0000 C CNN
+ 1 7750 3550
+ -1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U10
+U 1 1 5CF46008
+P 7600 3400
+F 0 "U10" H 7600 3900 60 0000 C CNN
+F 1 "plot_v1" H 7800 3750 60 0000 C CNN
+F 2 "" H 7600 3400 60 0000 C CNN
+F 3 "" H 7600 3400 60 0000 C CNN
+ 1 7600 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U11
+U 1 1 5CF45F98
+P 7600 3600
+F 0 "U11" H 7600 4100 60 0000 C CNN
+F 1 "plot_v1" H 7800 3950 60 0000 C CNN
+F 2 "" H 7600 3600 60 0000 C CNN
+F 3 "" H 7600 3600 60 0000 C CNN
+ 1 7600 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U12
+U 1 1 5CF45618
+P 7700 3500
+F 0 "U12" H 7700 4000 60 0000 C CNN
+F 1 "plot_v1" H 7900 3850 60 0000 C CNN
+F 2 "" H 7700 3500 60 0000 C CNN
+F 3 "" H 7700 3500 60 0000 C CNN
+ 1 7700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R10
+U 1 1 5CF232CD
+P 7350 3700
+F 0 "R10" H 7400 3830 50 0000 C CNN
+F 1 "1k" H 7400 3750 50 0000 C CNN
+F 2 "" H 7400 3680 30 0000 C CNN
+F 3 "" V 7400 3750 30 0000 C CNN
+ 1 7350 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R9
+U 1 1 5CF232C7
+P 7350 3600
+F 0 "R9" H 7400 3730 50 0000 C CNN
+F 1 "1k" H 7400 3650 50 0000 C CNN
+F 2 "" H 7400 3580 30 0000 C CNN
+F 3 "" V 7400 3650 30 0000 C CNN
+ 1 7350 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R8
+U 1 1 5CF232C1
+P 7350 3500
+F 0 "R8" H 7400 3630 50 0000 C CNN
+F 1 "1k" H 7400 3550 50 0000 C CNN
+F 2 "" H 7400 3480 30 0000 C CNN
+F 3 "" V 7400 3550 30 0000 C CNN
+ 1 7350 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R7
+U 1 1 5CF232BB
+P 7350 3400
+F 0 "R7" H 7400 3530 50 0000 C CNN
+F 1 "1k" H 7400 3450 50 0000 C CNN
+F 2 "" H 7400 3380 30 0000 C CNN
+F 3 "" V 7400 3450 30 0000 C CNN
+ 1 7350 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v6
+U 1 1 5CF1E4C8
+P 8200 3550
+F 0 "v6" H 8000 3650 60 0000 C CNN
+F 1 "DC" H 8000 3500 60 0000 C CNN
+F 2 "R1" H 7900 3550 60 0000 C CNN
+F 3 "" H 8200 3550 60 0000 C CNN
+ 1 8200 3550
+ 0 -1 1 0
+$EndComp
+$Comp
+L DC v5
+U 1 1 5CF1E4C2
+P 8200 3650
+F 0 "v5" H 8000 3750 60 0000 C CNN
+F 1 "DC" H 8000 3600 60 0000 C CNN
+F 2 "R1" H 7900 3650 60 0000 C CNN
+F 3 "" H 8200 3650 60 0000 C CNN
+ 1 8200 3650
+ 0 -1 1 0
+$EndComp
+$Comp
+L DC v8
+U 1 1 5CF1E4BC
+P 8200 3350
+F 0 "v8" H 8000 3450 60 0000 C CNN
+F 1 "DC" H 8000 3300 60 0000 C CNN
+F 2 "R1" H 7900 3350 60 0000 C CNN
+F 3 "" H 8200 3350 60 0000 C CNN
+ 1 8200 3350
+ 0 -1 1 0
+$EndComp
+$Comp
+L DC v7
+U 1 1 5CF1E4B6
+P 8200 3450
+F 0 "v7" H 8000 3550 60 0000 C CNN
+F 1 "DC" H 8000 3400 60 0000 C CNN
+F 2 "R1" H 7900 3450 60 0000 C CNN
+F 3 "" H 8200 3450 60 0000 C CNN
+ 1 8200 3450
+ 0 -1 1 0
+$EndComp
+Connection ~ 3300 3350
+Wire Wire Line
+ 3300 3150 3300 3350
+Wire Wire Line
+ 3100 3150 3300 3150
+Connection ~ 3350 3250
+Wire Wire Line
+ 3350 3100 3350 3250
+Wire Wire Line
+ 3500 3100 3350 3100
+Connection ~ 3400 3600
+Wire Wire Line
+ 3500 3600 3400 3600
+Wire Wire Line
+ 3500 3750 3500 3600
+Connection ~ 3250 3700
+Wire Wire Line
+ 3050 3700 3250 3700
+Wire Wire Line
+ 3250 3600 3250 3850
+Connection ~ 3400 3550
+Wire Wire Line
+ 3400 3550 3400 3650
+Connection ~ 2200 3550
+Wire Wire Line
+ 3250 3600 3200 3450
+Connection ~ 3250 3350
+Wire Wire Line
+ 3250 3300 3250 3350
+Connection ~ 3200 3250
+Wire Wire Line
+ 3200 3200 3200 3250
+Connection ~ 2200 3350
+Wire Wire Line
+ 2250 3350 2200 3350
+Connection ~ 2200 3450
+Wire Wire Line
+ 2300 3450 2200 3450
+Wire Wire Line
+ 2050 3550 2300 3550
+Wire Wire Line
+ 2200 3250 2200 3550
+Wire Wire Line
+ 2250 3250 2200 3250
+Wire Wire Line
+ 3200 3550 3450 3550
+Wire Wire Line
+ 3200 3450 3450 3450
+Wire Wire Line
+ 3150 3350 3450 3350
+Wire Wire Line
+ 3150 3250 3450 3250
+Text GLabel 3500 3750 2 60 Input ~ 0
+v4
+Text GLabel 3050 3700 0 60 Input ~ 0
+v3
+Text GLabel 3100 3150 0 60 Input ~ 0
+v2
+Text GLabel 3500 3100 2 60 Input ~ 0
+v1
+$Comp
+L plot_v1 U7
+U 1 1 5CF31477
+P 3400 3450
+F 0 "U7" H 3400 3950 60 0000 C CNN
+F 1 "plot_v1" H 3600 3800 60 0000 C CNN
+F 2 "" H 3400 3450 60 0000 C CNN
+F 3 "" H 3400 3450 60 0000 C CNN
+ 1 3400 3450
+ -1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 5CF31400
+P 3050 3850
+F 0 "U4" H 3050 4350 60 0000 C CNN
+F 1 "plot_v1" H 3250 4200 60 0000 C CNN
+F 2 "" H 3050 3850 60 0000 C CNN
+F 3 "" H 3050 3850 60 0000 C CNN
+ 1 3050 3850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 5CF313A0
+P 3250 3500
+F 0 "U6" H 3250 4000 60 0000 C CNN
+F 1 "plot_v1" H 3450 3850 60 0000 C CNN
+F 2 "" H 3250 3500 60 0000 C CNN
+F 3 "" H 3250 3500 60 0000 C CNN
+ 1 3250 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 5CF303CA
+P 3200 3400
+F 0 "U5" H 3200 3900 60 0000 C CNN
+F 1 "plot_v1" H 3400 3750 60 0000 C CNN
+F 2 "" H 3200 3400 60 0000 C CNN
+F 3 "" H 3200 3400 60 0000 C CNN
+ 1 3200 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R4
+U 1 1 5CF1FDB5
+P 3550 3600
+F 0 "R4" H 3600 3730 50 0000 C CNN
+F 1 "1k" H 3600 3650 50 0000 C CNN
+F 2 "" H 3600 3580 30 0000 C CNN
+F 3 "" V 3600 3650 30 0000 C CNN
+ 1 3550 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R3
+U 1 1 5CF1FD69
+P 3550 3500
+F 0 "R3" H 3600 3630 50 0000 C CNN
+F 1 "1k" H 3600 3550 50 0000 C CNN
+F 2 "" H 3600 3480 30 0000 C CNN
+F 3 "" V 3600 3550 30 0000 C CNN
+ 1 3550 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R2
+U 1 1 5CF1FD21
+P 3550 3400
+F 0 "R2" H 3600 3530 50 0000 C CNN
+F 1 "1k" H 3600 3450 50 0000 C CNN
+F 2 "" H 3600 3380 30 0000 C CNN
+F 3 "" V 3600 3450 30 0000 C CNN
+ 1 3550 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R1
+U 1 1 5CF1FCC6
+P 3550 3300
+F 0 "R1" H 3600 3430 50 0000 C CNN
+F 1 "1k" H 3600 3350 50 0000 C CNN
+F 2 "" H 3600 3280 30 0000 C CNN
+F 3 "" V 3600 3350 30 0000 C CNN
+ 1 3550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v4
+U 1 1 5CF1D11E
+P 2750 3550
+F 0 "v4" H 2550 3650 60 0000 C CNN
+F 1 "DC" H 2550 3500 60 0000 C CNN
+F 2 "R1" H 2450 3550 60 0000 C CNN
+F 3 "" H 2750 3550 60 0000 C CNN
+ 1 2750 3550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v3
+U 1 1 5CF1D0EF
+P 2750 3450
+F 0 "v3" H 2550 3550 60 0000 C CNN
+F 1 "DC" H 2550 3400 60 0000 C CNN
+F 2 "R1" H 2450 3450 60 0000 C CNN
+F 3 "" H 2750 3450 60 0000 C CNN
+ 1 2750 3450
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v2
+U 1 1 5CF1D0C3
+P 2700 3350
+F 0 "v2" H 2500 3450 60 0000 C CNN
+F 1 "DC" H 2500 3300 60 0000 C CNN
+F 2 "R1" H 2400 3350 60 0000 C CNN
+F 3 "" H 2700 3350 60 0000 C CNN
+ 1 2700 3350
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v1
+U 1 1 5CF1CE2E
+P 2700 3250
+F 0 "v1" H 2500 3350 60 0000 C CNN
+F 1 "DC" H 2500 3200 60 0000 C CNN
+F 2 "R1" H 2400 3250 60 0000 C CNN
+F 3 "" H 2700 3250 60 0000 C CNN
+ 1 2700 3250
+ 0 1 1 0
+$EndComp
+Connection ~ 6800 2300
+Wire Wire Line
+ 6750 2450 6800 2450
+Wire Wire Line
+ 6800 2450 6800 2400
+Connection ~ 6800 2400
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test_Previous_Values.xml new file mode 100644 index 00000000..9d4b9450 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v7 name="Source type">dc<field1 name="Value">5</field1></v7><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u3 name="type">adc_bridge<field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter value for in_low (default=1.0)" /></u3><u2 name="type">dac_bridge<field9 name="Enter value for input load (default=1.0e-12)" /><field10 name="Enter value for out_low (default=0.0)" /><field11 name="Enter value for out_high (default=5.0)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /><field14 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/analysis b/Examples/Analysis_Of_Digital_IC/4002_test/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012-cache.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012-cache.lib new file mode 100644 index 00000000..6e0697ee --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir new file mode 100644 index 00000000..c81542fc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U8 Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter
+U9 Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and
+U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and
+U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and
+U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and
+U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and
+U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out new file mode 100644 index 00000000..b34bbe45 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.cir.out @@ -0,0 +1,44 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+
+* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.pro b/Examples/Analysis_Of_Digital_IC/4012_test/4012.pro new file mode 100644 index 00000000..6ce7d980 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.pro @@ -0,0 +1,44 @@ +update=06/01/19 13:10:32
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_User
+LibName11=eSim_Subckt
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.sch b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sch new file mode 100644 index 00000000..6b950a1d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sch @@ -0,0 +1,342 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4012-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 3350 2600 2550 2600
+Wire Wire Line
+ 3350 2700 3150 2700
+Wire Wire Line
+ 3150 2700 3150 2850
+Wire Wire Line
+ 3150 2850 2550 2850
+Wire Wire Line
+ 3350 3200 3150 3200
+Wire Wire Line
+ 3150 3200 3150 3100
+Wire Wire Line
+ 3150 3100 2550 3100
+Wire Wire Line
+ 3350 3300 2550 3300
+Wire Wire Line
+ 5200 2950 5500 2950
+$Comp
+L d_inverter U8
+U 1 1 5CEE55AB
+P 5800 2950
+F 0 "U8" H 5800 2850 60 0000 C CNN
+F 1 "d_inverter" H 5800 3100 60 0000 C CNN
+F 2 "" H 5850 2900 60 0000 C CNN
+F 3 "" H 5850 2900 60 0000 C CNN
+ 1 5800 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6100 2950 6500 2950
+Wire Wire Line
+ 3400 3950 2600 3950
+Wire Wire Line
+ 3400 4050 3200 4050
+Wire Wire Line
+ 3200 4050 3200 4200
+Wire Wire Line
+ 3200 4200 2600 4200
+Wire Wire Line
+ 3400 4550 3200 4550
+Wire Wire Line
+ 3200 4550 3200 4450
+Wire Wire Line
+ 3200 4450 2600 4450
+Wire Wire Line
+ 3400 4650 2600 4650
+Wire Wire Line
+ 5250 4300 5550 4300
+$Comp
+L d_inverter U9
+U 1 1 5CEE5715
+P 5850 4300
+F 0 "U9" H 5850 4200 60 0000 C CNN
+F 1 "d_inverter" H 5850 4450 60 0000 C CNN
+F 2 "" H 5900 4250 60 0000 C CNN
+F 3 "" H 5900 4250 60 0000 C CNN
+ 1 5850 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6150 4300 6550 4300
+$Comp
+L PORT U1
+U 2 1 5CEE57D6
+P 2300 2600
+F 0 "U1" H 2350 2700 30 0000 C CNN
+F 1 "PORT" H 2300 2600 30 0000 C CNN
+F 2 "" H 2300 2600 60 0000 C CNN
+F 3 "" H 2300 2600 60 0000 C CNN
+ 2 2300 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CEE587B
+P 2300 2850
+F 0 "U1" H 2350 2950 30 0000 C CNN
+F 1 "PORT" H 2300 2850 30 0000 C CNN
+F 2 "" H 2300 2850 60 0000 C CNN
+F 3 "" H 2300 2850 60 0000 C CNN
+ 3 2300 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CEE58AF
+P 2300 3100
+F 0 "U1" H 2350 3200 30 0000 C CNN
+F 1 "PORT" H 2300 3100 30 0000 C CNN
+F 2 "" H 2300 3100 60 0000 C CNN
+F 3 "" H 2300 3100 60 0000 C CNN
+ 4 2300 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CEE58E6
+P 6800 4300
+F 0 "U1" H 6850 4400 30 0000 C CNN
+F 1 "PORT" H 6800 4300 30 0000 C CNN
+F 2 "" H 6800 4300 60 0000 C CNN
+F 3 "" H 6800 4300 60 0000 C CNN
+ 13 6800 4300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CEE5922
+P 2300 3300
+AR Path="/5CEE58E6" Ref="U1" Part="1"
+AR Path="/5CEE5922" Ref="U1" Part="5"
+F 0 "U1" H 2350 3400 30 0000 C CNN
+F 1 "PORT" H 2300 3300 30 0000 C CNN
+F 2 "" H 2300 3300 60 0000 C CNN
+F 3 "" H 2300 3300 60 0000 C CNN
+ 5 2300 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CEE596F
+P 2350 3950
+AR Path="/5CEE5922" Ref="U1" Part="5"
+AR Path="/5CEE596F" Ref="U1" Part="9"
+F 0 "U1" H 2400 4050 30 0000 C CNN
+F 1 "PORT" H 2350 3950 30 0000 C CNN
+F 2 "" H 2350 3950 60 0000 C CNN
+F 3 "" H 2350 3950 60 0000 C CNN
+ 9 2350 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE59AF
+P 2350 4200
+AR Path="/5CEE596F" Ref="U1" Part="6"
+AR Path="/5CEE59AF" Ref="U1" Part="10"
+F 0 "U1" H 2400 4300 30 0000 C CNN
+F 1 "PORT" H 2350 4200 30 0000 C CNN
+F 2 "" H 2350 4200 60 0000 C CNN
+F 3 "" H 2350 4200 60 0000 C CNN
+ 10 2350 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE59F6
+P 2350 4450
+AR Path="/5CEE59AF" Ref="U1" Part="7"
+AR Path="/5CEE59F6" Ref="U1" Part="11"
+F 0 "U1" H 2400 4550 30 0000 C CNN
+F 1 "PORT" H 2350 4450 30 0000 C CNN
+F 2 "" H 2350 4450 60 0000 C CNN
+F 3 "" H 2350 4450 60 0000 C CNN
+ 11 2350 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE5A6A
+P 2350 4650
+AR Path="/5CEE59F6" Ref="U1" Part="8"
+AR Path="/5CEE5A6A" Ref="U1" Part="12"
+F 0 "U1" H 2400 4750 30 0000 C CNN
+F 1 "PORT" H 2350 4650 30 0000 C CNN
+F 2 "" H 2350 4650 60 0000 C CNN
+F 3 "" H 2350 4650 60 0000 C CNN
+ 12 2350 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE5BF8
+P 6750 2950
+AR Path="/5CEE5A6A" Ref="U1" Part="9"
+AR Path="/5CEE5BF8" Ref="U1" Part="1"
+F 0 "U1" H 6800 3050 30 0000 C CNN
+F 1 "PORT" H 6750 2950 30 0000 C CNN
+F 2 "" H 6750 2950 60 0000 C CNN
+F 3 "" H 6750 2950 60 0000 C CNN
+ 1 6750 2950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CEE5C72
+P 7850 1450
+F 0 "U1" H 7900 1550 30 0000 C CNN
+F 1 "PORT" H 7850 1450 30 0000 C CNN
+F 2 "" H 7850 1450 60 0000 C CNN
+F 3 "" H 7850 1450 60 0000 C CNN
+ 6 7850 1450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CEE5D23
+P 7850 1700
+F 0 "U1" H 7900 1800 30 0000 C CNN
+F 1 "PORT" H 7850 1700 30 0000 C CNN
+F 2 "" H 7850 1700 60 0000 C CNN
+F 3 "" H 7850 1700 60 0000 C CNN
+ 7 7850 1700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CEE5D75
+P 7850 1950
+F 0 "U1" H 7900 2050 30 0000 C CNN
+F 1 "PORT" H 7850 1950 30 0000 C CNN
+F 2 "" H 7850 1950 60 0000 C CNN
+F 3 "" H 7850 1950 60 0000 C CNN
+ 14 7850 1950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CEE5DCA
+P 7850 2250
+F 0 "U1" H 7900 2350 30 0000 C CNN
+F 1 "PORT" H 7850 2250 30 0000 C CNN
+F 2 "" H 7850 2250 60 0000 C CNN
+F 3 "" H 7850 2250 60 0000 C CNN
+ 8 7850 2250
+ -1 0 0 1
+$EndComp
+NoConn ~ 7600 1450
+NoConn ~ 7600 1700
+NoConn ~ 7600 1950
+NoConn ~ 7600 2250
+$Comp
+L d_and U4
+U 1 1 5CEE56F6
+P 3850 4050
+F 0 "U4" H 3850 4050 60 0000 C CNN
+F 1 "d_and" H 3900 4150 60 0000 C CNN
+F 2 "" H 3850 4050 60 0000 C CNN
+F 3 "" H 3850 4050 60 0000 C CNN
+ 1 3850 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 5CEE56FC
+P 3850 4650
+F 0 "U5" H 3850 4650 60 0000 C CNN
+F 1 "d_and" H 3900 4750 60 0000 C CNN
+F 2 "" H 3850 4650 60 0000 C CNN
+F 3 "" H 3850 4650 60 0000 C CNN
+ 1 3850 4650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4350 4600 4300 4600
+Wire Wire Line
+ 4350 4350 4350 4600
+Wire Wire Line
+ 4350 4000 4350 4250
+Wire Wire Line
+ 4300 4000 4350 4000
+$Comp
+L d_and U7
+U 1 1 5CEE5702
+P 4800 4350
+F 0 "U7" H 4800 4350 60 0000 C CNN
+F 1 "d_and" H 4850 4450 60 0000 C CNN
+F 2 "" H 4800 4350 60 0000 C CNN
+F 3 "" H 4800 4350 60 0000 C CNN
+ 1 4800 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4250 2650 4300 2650
+Wire Wire Line
+ 4300 3250 4250 3250
+Wire Wire Line
+ 4300 2650 4300 2900
+Wire Wire Line
+ 4300 3000 4300 3250
+$Comp
+L d_and U6
+U 1 1 5CEE5432
+P 4750 3000
+F 0 "U6" H 4750 3000 60 0000 C CNN
+F 1 "d_and" H 4800 3100 60 0000 C CNN
+F 2 "" H 4750 3000 60 0000 C CNN
+F 3 "" H 4750 3000 60 0000 C CNN
+ 1 4750 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5CEE540C
+P 3800 3300
+F 0 "U3" H 3800 3300 60 0000 C CNN
+F 1 "d_and" H 3850 3400 60 0000 C CNN
+F 2 "" H 3800 3300 60 0000 C CNN
+F 3 "" H 3800 3300 60 0000 C CNN
+ 1 3800 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5CEE53DC
+P 3800 2700
+F 0 "U2" H 3800 2700 60 0000 C CNN
+F 1 "d_and" H 3850 2800 60 0000 C CNN
+F 2 "" H 3800 2700 60 0000 C CNN
+F 3 "" H 3800 2700 60 0000 C CNN
+ 1 3800 2700
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012.sub b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sub new file mode 100644 index 00000000..a92e83f3 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012.sub @@ -0,0 +1,38 @@ +* Subcircuit 4012
+.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4012
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4012_test/4012_Previous_Values.xml new file mode 100644 index 00000000..4e7e73b2 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib new file mode 100644 index 00000000..b58b86b5 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4012
+#
+DEF 4012 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "4012" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 350 -400 0 1 0 N
+X Q1 1 -500 300 200 R 50 50 1 1 O
+X A1 2 -500 200 200 R 50 50 1 1 I
+X B1 3 -500 100 200 R 50 50 1 1 I
+X C1 4 -500 0 200 R 50 50 1 1 I
+X D1 5 -500 -100 200 R 50 50 1 1 I
+X NC 6 -500 -200 200 R 50 50 1 1 N
+X VSS 7 -500 -300 200 R 50 50 1 1 I
+X NC 8 550 -300 200 L 50 50 1 1 N
+X A2 9 550 -200 200 L 50 50 1 1 I
+X B2 10 550 -100 200 L 50 50 1 1 I
+X C2 11 550 0 200 L 50 50 1 1 I
+X D2 12 550 100 200 L 50 50 1 1 I
+X Q2 13 550 200 200 L 50 50 1 1 O
+X VDD 14 550 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir new file mode 100644 index 00000000..89708044 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim-Workspace\4012_test\4012_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 15:21:40
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U7-Pad1_ Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ ? ? ? Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ Net-_U7-Pad2_ ? 4012
+U5 a1 b1 c1 d1 Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ adc_bridge_4
+v1 a1 GND DC
+v2 b1 GND DC
+v3 c1 GND DC
+v4 d1 GND DC
+U9 a2 b2 d2 c2 Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ adc_bridge_4
+v8 a2 GND DC
+v7 b2 GND DC
+v6 d2 GND DC
+v5 c2 GND DC
+U1 a1 plot_v1
+U3 b1 plot_v1
+U4 c1 plot_v1
+U2 d1 plot_v1
+U11 d2 plot_v1
+U10 c2 plot_v1
+U13 a2 plot_v1
+U12 b2 plot_v1
+U7 Net-_U7-Pad1_ Net-_U7-Pad2_ q1 q2 dac_bridge_2
+U8 q2 plot_v1
+U6 q1 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out new file mode 100644 index 00000000..1b8ab981 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.cir.out @@ -0,0 +1,53 @@ +* c:\users\malli\esim-workspace\4012_test\4012_test.cir + +.include 4012.sub +x1 net-_u7-pad1_ net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ? ? ? net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ net-_u7-pad2_ ? 4012 +* u5 a1 b1 c1 d1 net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ adc_bridge_4 +v1 a1 gnd dc 0 +v2 b1 gnd dc 0 +v3 c1 gnd dc 0 +v4 d1 gnd dc 0 +* u9 a2 b2 d2 c2 net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ adc_bridge_4 +v8 a2 gnd dc 0 +v7 b2 gnd dc 0 +v6 d2 gnd dc 0 +v5 c2 gnd dc 0 +* u1 a1 plot_v1 +* u3 b1 plot_v1 +* u4 c1 plot_v1 +* u2 d1 plot_v1 +* u11 d2 plot_v1 +* u10 c2 plot_v1 +* u13 a2 plot_v1 +* u12 b2 plot_v1 +* u7 net-_u7-pad1_ net-_u7-pad2_ q1 q2 dac_bridge_2 +* u8 q2 plot_v1 +* u6 q1 plot_v1 +a1 [a1 b1 c1 d1 ] [net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ] u5 +a2 [a2 b2 d2 c2 ] [net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] u9 +a3 [net-_u7-pad1_ net-_u7-pad2_ ] [q1 q2 ] u7 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(a1) +plot v(b1) +plot v(c1) +plot v(d1) +plot v(d2) +plot v(c2) +plot v(a2) +plot v(b2) +plot v(q2) +plot v(q1) +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro new file mode 100644 index 00000000..ee32c69b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro @@ -0,0 +1,45 @@ +update=06/01/19 15:09:21
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_User
+LibName12=eSim_Subckt
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.proj b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.proj new file mode 100644 index 00000000..6d5be088 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.proj @@ -0,0 +1 @@ +schematicFile 4012_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch new file mode 100644 index 00000000..1380bb1d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch @@ -0,0 +1,501 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4012_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4012 X1
+U 1 1 5CF22C85
+P 5050 4050
+F 0 "X1" H 5050 4050 60 0000 C CNN
+F 1 "4012" H 5050 4250 60 0000 C CNN
+F 2 "" H 5050 4050 60 0000 C CNN
+F 3 "" H 5050 4050 60 0000 C CNN
+ 1 5050 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_4 U5
+U 1 1 5CF24801
+P 3600 4050
+F 0 "U5" H 3600 4050 60 0000 C CNN
+F 1 "adc_bridge_4" H 3600 4350 60 0000 C CNN
+F 2 "" H 3600 4050 60 0000 C CNN
+F 3 "" H 3600 4050 60 0000 C CNN
+ 1 3600 4050
+ 1 0 0 -1
+$EndComp
+NoConn ~ 4550 4350
+NoConn ~ 5600 3750
+$Comp
+L DC v1
+U 1 1 5CF2488C
+P 1900 3450
+F 0 "v1" H 1700 3550 60 0000 C CNN
+F 1 "DC" H 1700 3400 60 0000 C CNN
+F 2 "R1" H 1600 3450 60 0000 C CNN
+F 3 "" H 1900 3450 60 0000 C CNN
+ 1 1900 3450
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v2
+U 1 1 5CF248E2
+P 1900 4000
+F 0 "v2" H 1700 4100 60 0000 C CNN
+F 1 "DC" H 1700 3950 60 0000 C CNN
+F 2 "R1" H 1600 4000 60 0000 C CNN
+F 3 "" H 1900 4000 60 0000 C CNN
+ 1 1900 4000
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v3
+U 1 1 5CF24906
+P 1900 4550
+F 0 "v3" H 1700 4650 60 0000 C CNN
+F 1 "DC" H 1700 4500 60 0000 C CNN
+F 2 "R1" H 1600 4550 60 0000 C CNN
+F 3 "" H 1900 4550 60 0000 C CNN
+ 1 1900 4550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v4
+U 1 1 5CF24935
+P 1900 5100
+F 0 "v4" H 1700 5200 60 0000 C CNN
+F 1 "DC" H 1700 5050 60 0000 C CNN
+F 2 "R1" H 1600 5100 60 0000 C CNN
+F 3 "" H 1900 5100 60 0000 C CNN
+ 1 1900 5100
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 2350 3450 2800 3450
+Wire Wire Line
+ 2800 3450 2800 3850
+Wire Wire Line
+ 2800 3850 3050 3850
+Wire Wire Line
+ 3050 3950 2350 3950
+Wire Wire Line
+ 2350 3950 2350 4000
+Wire Wire Line
+ 2350 4550 2700 4550
+Wire Wire Line
+ 2700 4550 2700 4050
+Wire Wire Line
+ 2700 4050 3050 4050
+Wire Wire Line
+ 3050 4150 3050 5100
+Wire Wire Line
+ 3050 5100 2350 5100
+Wire Wire Line
+ 1450 3450 1200 3450
+Wire Wire Line
+ 1200 3450 1200 5100
+Wire Wire Line
+ 1200 4000 1450 4000
+Wire Wire Line
+ 1200 4550 1450 4550
+Connection ~ 1200 4000
+Wire Wire Line
+ 1200 5100 1450 5100
+Connection ~ 1200 4550
+$Comp
+L adc_bridge_4 U9
+U 1 1 5CF24B4A
+P 6450 4050
+F 0 "U9" H 6450 4050 60 0000 C CNN
+F 1 "adc_bridge_4" H 6450 4350 60 0000 C CNN
+F 2 "" H 6450 4050 60 0000 C CNN
+F 3 "" H 6450 4050 60 0000 C CNN
+ 1 6450 4050
+ -1 0 0 1
+$EndComp
+$Comp
+L DC v8
+U 1 1 5CF24B50
+P 8150 4650
+F 0 "v8" H 7950 4750 60 0000 C CNN
+F 1 "DC" H 7950 4600 60 0000 C CNN
+F 2 "R1" H 7850 4650 60 0000 C CNN
+F 3 "" H 8150 4650 60 0000 C CNN
+ 1 8150 4650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v7
+U 1 1 5CF24B56
+P 8150 4100
+F 0 "v7" H 7950 4200 60 0000 C CNN
+F 1 "DC" H 7950 4050 60 0000 C CNN
+F 2 "R1" H 7850 4100 60 0000 C CNN
+F 3 "" H 8150 4100 60 0000 C CNN
+ 1 8150 4100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v6
+U 1 1 5CF24B5C
+P 8150 3550
+F 0 "v6" H 7950 3650 60 0000 C CNN
+F 1 "DC" H 7950 3500 60 0000 C CNN
+F 2 "R1" H 7850 3550 60 0000 C CNN
+F 3 "" H 8150 3550 60 0000 C CNN
+ 1 8150 3550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v5
+U 1 1 5CF24B62
+P 8150 3000
+F 0 "v5" H 7950 3100 60 0000 C CNN
+F 1 "DC" H 7950 2950 60 0000 C CNN
+F 2 "R1" H 7850 3000 60 0000 C CNN
+F 3 "" H 8150 3000 60 0000 C CNN
+ 1 8150 3000
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 7700 4650 7250 4650
+Wire Wire Line
+ 7250 4650 7250 4250
+Wire Wire Line
+ 7250 4250 7000 4250
+Wire Wire Line
+ 7000 4150 7700 4150
+Wire Wire Line
+ 7700 4150 7700 4100
+Wire Wire Line
+ 7700 3550 7350 3550
+Wire Wire Line
+ 7350 3400 7350 4050
+Wire Wire Line
+ 7350 4050 7000 4050
+Wire Wire Line
+ 7000 3950 7000 3000
+Wire Wire Line
+ 7000 3000 7700 3000
+Wire Wire Line
+ 8600 4650 8850 4650
+Wire Wire Line
+ 8850 4650 8850 3000
+Wire Wire Line
+ 8850 4100 8600 4100
+Wire Wire Line
+ 8850 3550 8600 3550
+Connection ~ 8850 4100
+Wire Wire Line
+ 8850 3000 8600 3000
+Connection ~ 8850 3550
+Wire Wire Line
+ 5900 3950 5600 3950
+Wire Wire Line
+ 5600 4050 5900 4050
+Wire Wire Line
+ 5600 4150 5900 4150
+Wire Wire Line
+ 5600 4250 5900 4250
+Wire Wire Line
+ 4550 3850 4150 3850
+Wire Wire Line
+ 4150 3950 4550 3950
+Wire Wire Line
+ 4150 4050 4550 4050
+Wire Wire Line
+ 4550 4150 4150 4150
+$Comp
+L plot_v1 U1
+U 1 1 5CF2512D
+P 2400 3300
+F 0 "U1" H 2400 3800 60 0000 C CNN
+F 1 "plot_v1" H 2600 3650 60 0000 C CNN
+F 2 "" H 2400 3300 60 0000 C CNN
+F 3 "" H 2400 3300 60 0000 C CNN
+ 1 2400 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U3
+U 1 1 5CF25268
+P 3000 3450
+F 0 "U3" H 3000 3950 60 0000 C CNN
+F 1 "plot_v1" H 3200 3800 60 0000 C CNN
+F 2 "" H 3000 3450 60 0000 C CNN
+F 3 "" H 3000 3450 60 0000 C CNN
+ 1 3000 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 5CF252A7
+P 3050 4600
+F 0 "U4" H 3050 5100 60 0000 C CNN
+F 1 "plot_v1" H 3250 4950 60 0000 C CNN
+F 2 "" H 3050 4600 60 0000 C CNN
+F 3 "" H 3050 4600 60 0000 C CNN
+ 1 3050 4600
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U2
+U 1 1 5CF25311
+P 2900 5100
+F 0 "U2" H 2900 5600 60 0000 C CNN
+F 1 "plot_v1" H 3100 5450 60 0000 C CNN
+F 2 "" H 2900 5100 60 0000 C CNN
+F 3 "" H 2900 5100 60 0000 C CNN
+ 1 2900 5100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 2400 3100 2400 3450
+Connection ~ 2400 3450
+Wire Wire Line
+ 3000 3250 3000 3550
+Wire Wire Line
+ 3000 3550 2700 3550
+Wire Wire Line
+ 2700 3550 2700 3950
+Connection ~ 2700 3950
+Wire Wire Line
+ 2700 4450 3250 4450
+Wire Wire Line
+ 3250 4450 3250 4600
+Connection ~ 2700 4450
+Wire Wire Line
+ 2900 5100 2900 5300
+Connection ~ 2900 5100
+Wire Wire Line
+ 1200 4250 850 4250
+Wire Wire Line
+ 850 4150 850 4500
+Connection ~ 1200 4250
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5CF254BC
+P 850 4150
+F 0 "#FLG01" H 850 4245 50 0001 C CNN
+F 1 "PWR_FLAG" H 850 4330 50 0000 C CNN
+F 2 "" H 850 4150 50 0000 C CNN
+F 3 "" H 850 4150 50 0000 C CNN
+ 1 850 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 5CF254EE
+P 850 4500
+F 0 "#PWR02" H 850 4250 50 0001 C CNN
+F 1 "eSim_GND" H 850 4350 50 0000 C CNN
+F 2 "" H 850 4500 50 0001 C CNN
+F 3 "" H 850 4500 50 0001 C CNN
+ 1 850 4500
+ 1 0 0 -1
+$EndComp
+Connection ~ 850 4250
+Text GLabel 2300 3250 0 60 Input ~ 0
+a1
+Text GLabel 2900 3350 0 60 Input ~ 0
+b1
+Text GLabel 2900 4550 3 60 Input ~ 0
+c1
+Text GLabel 2800 5200 0 60 Input ~ 0
+d1
+Wire Wire Line
+ 2800 5200 2900 5200
+Connection ~ 2900 5200
+Wire Wire Line
+ 2900 4450 2900 4550
+Connection ~ 2900 4450
+Wire Wire Line
+ 2900 3350 3000 3350
+Connection ~ 3000 3350
+Wire Wire Line
+ 2300 3250 2400 3250
+Connection ~ 2400 3250
+$Comp
+L plot_v1 U11
+U 1 1 5CF2581B
+P 7200 3000
+F 0 "U11" H 7200 3500 60 0000 C CNN
+F 1 "plot_v1" H 7400 3350 60 0000 C CNN
+F 2 "" H 7200 3000 60 0000 C CNN
+F 3 "" H 7200 3000 60 0000 C CNN
+ 1 7200 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U10
+U 1 1 5CF25889
+P 6500 3450
+F 0 "U10" H 6500 3950 60 0000 C CNN
+F 1 "plot_v1" H 6700 3800 60 0000 C CNN
+F 2 "" H 6500 3450 60 0000 C CNN
+F 3 "" H 6500 3450 60 0000 C CNN
+ 1 6500 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U13
+U 1 1 5CF258F2
+P 7550 4750
+F 0 "U13" H 7550 5250 60 0000 C CNN
+F 1 "plot_v1" H 7750 5100 60 0000 C CNN
+F 2 "" H 7550 4750 60 0000 C CNN
+F 3 "" H 7550 4750 60 0000 C CNN
+ 1 7550 4750
+ -1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U12
+U 1 1 5CF2597E
+P 7200 4800
+F 0 "U12" H 7200 5300 60 0000 C CNN
+F 1 "plot_v1" H 7400 5150 60 0000 C CNN
+F 2 "" H 7200 4800 60 0000 C CNN
+F 3 "" H 7200 4800 60 0000 C CNN
+ 1 7200 4800
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 7550 4950 7550 4650
+Connection ~ 7550 4650
+Wire Wire Line
+ 7000 4800 7150 4800
+Wire Wire Line
+ 7150 4800 7150 4150
+Connection ~ 7150 4150
+Wire Wire Line
+ 7200 2800 7200 3400
+Wire Wire Line
+ 7200 3400 7350 3400
+Connection ~ 7350 3550
+Wire Wire Line
+ 6500 3250 6500 3450
+Wire Wire Line
+ 6500 3450 7000 3450
+Connection ~ 7000 3450
+Wire Wire Line
+ 8850 3800 9450 3800
+Wire Wire Line
+ 9450 3800 9450 4150
+Connection ~ 8850 3800
+$Comp
+L eSim_GND #PWR03
+U 1 1 5CF25F3B
+P 9450 4150
+F 0 "#PWR03" H 9450 3900 50 0001 C CNN
+F 1 "eSim_GND" H 9450 4000 50 0000 C CNN
+F 2 "" H 9450 4150 50 0001 C CNN
+F 3 "" H 9450 4150 50 0001 C CNN
+ 1 9450 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_2 U7
+U 1 1 5CF26149
+P 5050 2800
+F 0 "U7" H 5050 2800 60 0000 C CNN
+F 1 "dac_bridge_2" H 5100 2950 60 0000 C CNN
+F 2 "" H 5050 2800 60 0000 C CNN
+F 3 "" H 5050 2800 60 0000 C CNN
+ 1 5050 2800
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 4550 3250 4550 3750
+Wire Wire Line
+ 4550 3250 5000 3250
+Wire Wire Line
+ 5100 3250 5800 3250
+Wire Wire Line
+ 5800 3250 5800 3850
+Wire Wire Line
+ 5800 3850 5600 3850
+$Comp
+L plot_v1 U8
+U 1 1 5CF263AC
+P 5400 2000
+F 0 "U8" H 5400 2500 60 0000 C CNN
+F 1 "plot_v1" H 5600 2350 60 0000 C CNN
+F 2 "" H 5400 2000 60 0000 C CNN
+F 3 "" H 5400 2000 60 0000 C CNN
+ 1 5400 2000
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 5CF26445
+P 4800 2050
+F 0 "U6" H 4800 2550 60 0000 C CNN
+F 1 "plot_v1" H 5000 2400 60 0000 C CNN
+F 2 "" H 4800 2050 60 0000 C CNN
+F 3 "" H 4800 2050 60 0000 C CNN
+ 1 4800 2050
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 5000 2250 5000 2050
+Wire Wire Line
+ 5000 2050 4600 2050
+Wire Wire Line
+ 5100 2250 5100 2000
+Wire Wire Line
+ 5100 2000 5600 2000
+Text GLabel 4800 1850 1 60 Output ~ 0
+q1
+Text GLabel 5400 1850 1 60 Output ~ 0
+q2
+Text GLabel 7350 2900 2 60 Input ~ 0
+d2
+Text GLabel 6800 3350 1 60 Input ~ 0
+c2
+Text GLabel 7100 4500 0 60 Input ~ 0
+b2
+Text GLabel 7450 4800 0 60 Input ~ 0
+a2
+Wire Wire Line
+ 7450 4800 7550 4800
+Connection ~ 7550 4800
+Wire Wire Line
+ 7100 4500 7150 4500
+Connection ~ 7150 4500
+Wire Wire Line
+ 6800 3350 6800 3450
+Connection ~ 6800 3450
+Wire Wire Line
+ 7350 2900 7200 2900
+Connection ~ 7200 2900
+Wire Wire Line
+ 5400 1850 5400 2000
+Connection ~ 5400 2000
+Wire Wire Line
+ 4800 1850 4800 2050
+Connection ~ 4800 2050
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test_Previous_Values.xml new file mode 100644 index 00000000..87c47261 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v7 name="Source type">dc<field1 name="Value">0</field1></v7><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v5 name="Source type">dc<field1 name="Value">0</field1></v5></source><model><u5 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u5><u9 name="type">adc_bridge<field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter value for in_low (default=1.0)" /></u9><u7 name="type">dac_bridge<field9 name="Enter value for input load (default=1.0e-12)" /><field10 name="Enter value for out_low (default=0.0)" /><field11 name="Enter value for out_high (default=5.0)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /><field14 name="Enter value for out_undef (default=0.5)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4012</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/analysis b/Examples/Analysis_Of_Digital_IC/4012_test/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023-cache.lib b/Examples/Analysis_Of_Digital_IC/4023_test/4023-cache.lib new file mode 100644 index 00000000..e7a4d719 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023-cache.lib @@ -0,0 +1,76 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023.cir b/Examples/Analysis_Of_Digital_IC/4023_test/4023.cir new file mode 100644 index 00000000..3c228446 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023.cir @@ -0,0 +1,17 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4023\4023.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 15:33:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X3 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad1_ 3_and
+U4 Net-_U4-Pad1_ Net-_U1-Pad10_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
+U3 Net-_U3-Pad1_ Net-_U1-Pad6_ d_inverter
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad9_ d_inverter
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023.cir.out b/Examples/Analysis_Of_Digital_IC/4023_test/4023.cir.out new file mode 100644 index 00000000..09b30237 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023.cir.out @@ -0,0 +1,28 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
+
+.include 3_and.sub
+x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
+* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter
+a1 net-_u4-pad1_ net-_u1-pad10_ u4
+a2 net-_u3-pad1_ net-_u1-pad6_ u3
+a3 net-_u2-pad1_ net-_u1-pad9_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023.pro b/Examples/Analysis_Of_Digital_IC/4023_test/4023.pro new file mode 100644 index 00000000..6a83e3e3 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:32:35
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023.sch b/Examples/Analysis_Of_Digital_IC/4023_test/4023.sch new file mode 100644 index 00000000..ed64345f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023.sch @@ -0,0 +1,309 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X3
+U 1 1 5CF0FA82
+P 4800 2500
+F 0 "X3" H 4900 2450 60 0000 C CNN
+F 1 "3_and" H 4950 2650 60 0000 C CNN
+F 2 "" H 4800 2500 60 0000 C CNN
+F 3 "" H 4800 2500 60 0000 C CNN
+ 1 4800 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 5CF0FB13
+P 6150 2450
+F 0 "U4" H 6150 2350 60 0000 C CNN
+F 1 "d_inverter" H 6150 2600 60 0000 C CNN
+F 2 "" H 6200 2400 60 0000 C CNN
+F 3 "" H 6200 2400 60 0000 C CNN
+ 1 6150 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CF0FB34
+P 3100 1950
+F 0 "U1" H 3150 2050 30 0000 C CNN
+F 1 "PORT" H 3100 1950 30 0000 C CNN
+F 2 "" H 3100 1950 60 0000 C CNN
+F 3 "" H 3100 1950 60 0000 C CNN
+ 11 3100 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CF0FB90
+P 3100 2350
+F 0 "U1" H 3150 2450 30 0000 C CNN
+F 1 "PORT" H 3100 2350 30 0000 C CNN
+F 2 "" H 3100 2350 60 0000 C CNN
+F 3 "" H 3100 2350 60 0000 C CNN
+ 12 3100 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CF0FBB8
+P 3100 2750
+F 0 "U1" H 3150 2850 30 0000 C CNN
+F 1 "PORT" H 3100 2750 30 0000 C CNN
+F 2 "" H 3100 2750 60 0000 C CNN
+F 3 "" H 3100 2750 60 0000 C CNN
+ 13 3100 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CF0FBED
+P 7800 2450
+F 0 "U1" H 7850 2550 30 0000 C CNN
+F 1 "PORT" H 7800 2450 30 0000 C CNN
+F 2 "" H 7800 2450 60 0000 C CNN
+F 3 "" H 7800 2450 60 0000 C CNN
+ 10 7800 2450
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7550 2450 6450 2450
+Wire Wire Line
+ 5850 2450 5300 2450
+Wire Wire Line
+ 4450 2350 4450 1950
+Wire Wire Line
+ 4450 1950 3350 1950
+Wire Wire Line
+ 4450 2450 4100 2450
+Wire Wire Line
+ 4100 2450 4100 2350
+Wire Wire Line
+ 4100 2350 3350 2350
+Wire Wire Line
+ 3350 2750 3950 2750
+Wire Wire Line
+ 3950 2750 3950 2550
+Wire Wire Line
+ 3950 2550 4450 2550
+$Comp
+L 3_and X2
+U 1 1 5CF0FF35
+P 4700 3800
+F 0 "X2" H 4800 3750 60 0000 C CNN
+F 1 "3_and" H 4850 3950 60 0000 C CNN
+F 2 "" H 4700 3800 60 0000 C CNN
+F 3 "" H 4700 3800 60 0000 C CNN
+ 1 4700 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 5CF0FF3B
+P 6050 3750
+F 0 "U3" H 6050 3650 60 0000 C CNN
+F 1 "d_inverter" H 6050 3900 60 0000 C CNN
+F 2 "" H 6100 3700 60 0000 C CNN
+F 3 "" H 6100 3700 60 0000 C CNN
+ 1 6050 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CF0FF41
+P 3000 3250
+F 0 "U1" H 3050 3350 30 0000 C CNN
+F 1 "PORT" H 3000 3250 30 0000 C CNN
+F 2 "" H 3000 3250 60 0000 C CNN
+F 3 "" H 3000 3250 60 0000 C CNN
+ 4 3000 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CF0FF47
+P 3000 3650
+F 0 "U1" H 3050 3750 30 0000 C CNN
+F 1 "PORT" H 3000 3650 30 0000 C CNN
+F 2 "" H 3000 3650 60 0000 C CNN
+F 3 "" H 3000 3650 60 0000 C CNN
+ 5 3000 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CF0FF4D
+P 3000 4050
+F 0 "U1" H 3050 4150 30 0000 C CNN
+F 1 "PORT" H 3000 4050 30 0000 C CNN
+F 2 "" H 3000 4050 60 0000 C CNN
+F 3 "" H 3000 4050 60 0000 C CNN
+ 3 3000 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CF0FF53
+P 7700 3750
+F 0 "U1" H 7750 3850 30 0000 C CNN
+F 1 "PORT" H 7700 3750 30 0000 C CNN
+F 2 "" H 7700 3750 60 0000 C CNN
+F 3 "" H 7700 3750 60 0000 C CNN
+ 6 7700 3750
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7450 3750 6350 3750
+Wire Wire Line
+ 5750 3750 5200 3750
+Wire Wire Line
+ 4350 3650 4350 3250
+Wire Wire Line
+ 4350 3250 3250 3250
+Wire Wire Line
+ 4350 3750 4000 3750
+Wire Wire Line
+ 4000 3750 4000 3650
+Wire Wire Line
+ 4000 3650 3250 3650
+Wire Wire Line
+ 3250 4050 3850 4050
+Wire Wire Line
+ 3850 4050 3850 3850
+Wire Wire Line
+ 3850 3850 4350 3850
+$Comp
+L 3_and X1
+U 1 1 5CF100B9
+P 4650 5100
+F 0 "X1" H 4750 5050 60 0000 C CNN
+F 1 "3_and" H 4800 5250 60 0000 C CNN
+F 2 "" H 4650 5100 60 0000 C CNN
+F 3 "" H 4650 5100 60 0000 C CNN
+ 1 4650 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 5CF100BF
+P 6000 5050
+F 0 "U2" H 6000 4950 60 0000 C CNN
+F 1 "d_inverter" H 6000 5200 60 0000 C CNN
+F 2 "" H 6050 5000 60 0000 C CNN
+F 3 "" H 6050 5000 60 0000 C CNN
+ 1 6000 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CF100C5
+P 2950 4550
+F 0 "U1" H 3000 4650 30 0000 C CNN
+F 1 "PORT" H 2950 4550 30 0000 C CNN
+F 2 "" H 2950 4550 60 0000 C CNN
+F 3 "" H 2950 4550 60 0000 C CNN
+ 1 2950 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CF100CB
+P 2950 4950
+F 0 "U1" H 3000 5050 30 0000 C CNN
+F 1 "PORT" H 2950 4950 30 0000 C CNN
+F 2 "" H 2950 4950 60 0000 C CNN
+F 3 "" H 2950 4950 60 0000 C CNN
+ 2 2950 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CF100D1
+P 2950 5350
+F 0 "U1" H 3000 5450 30 0000 C CNN
+F 1 "PORT" H 2950 5350 30 0000 C CNN
+F 2 "" H 2950 5350 60 0000 C CNN
+F 3 "" H 2950 5350 60 0000 C CNN
+ 8 2950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CF100D7
+P 7650 5050
+F 0 "U1" H 7700 5150 30 0000 C CNN
+F 1 "PORT" H 7650 5050 30 0000 C CNN
+F 2 "" H 7650 5050 60 0000 C CNN
+F 3 "" H 7650 5050 60 0000 C CNN
+ 9 7650 5050
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7400 5050 6300 5050
+Wire Wire Line
+ 5700 5050 5150 5050
+Wire Wire Line
+ 4300 4950 4300 4550
+Wire Wire Line
+ 4300 4550 3200 4550
+Wire Wire Line
+ 4300 5050 3950 5050
+Wire Wire Line
+ 3950 5050 3950 4950
+Wire Wire Line
+ 3950 4950 3200 4950
+Wire Wire Line
+ 3200 5350 3800 5350
+Wire Wire Line
+ 3800 5350 3800 5150
+Wire Wire Line
+ 3800 5150 4300 5150
+$Comp
+L PORT U1
+U 7 1 5CF101BF
+P 9950 3350
+F 0 "U1" H 10000 3450 30 0000 C CNN
+F 1 "PORT" H 9950 3350 30 0000 C CNN
+F 2 "" H 9950 3350 60 0000 C CNN
+F 3 "" H 9950 3350 60 0000 C CNN
+ 7 9950 3350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CF1025C
+P 9950 3900
+F 0 "U1" H 10000 4000 30 0000 C CNN
+F 1 "PORT" H 9950 3900 30 0000 C CNN
+F 2 "" H 9950 3900 60 0000 C CNN
+F 3 "" H 9950 3900 60 0000 C CNN
+ 14 9950 3900
+ -1 0 0 1
+$EndComp
+NoConn ~ 9700 3350
+NoConn ~ 9700 3900
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023.sub b/Examples/Analysis_Of_Digital_IC/4023_test/4023.sub new file mode 100644 index 00000000..049fad06 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023.sub @@ -0,0 +1,22 @@ +* Subcircuit 4023
+.subckt 4023 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4023\4023.cir
+.include 3_and.sub
+x3 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad1_ 3_and
+* u4 net-_u4-pad1_ net-_u1-pad10_ d_inverter
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u3 net-_u3-pad1_ net-_u1-pad6_ d_inverter
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad9_ d_inverter
+a1 net-_u4-pad1_ net-_u1-pad10_ u4
+a2 net-_u3-pad1_ net-_u1-pad6_ u3
+a3 net-_u2-pad1_ net-_u1-pad9_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4023
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4023_test/4023_Previous_Values.xml new file mode 100644 index 00000000..ad900de2 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u4 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u4><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib new file mode 100644 index 00000000..725472f5 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4023
+#
+DEF 4023 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "4023" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X C3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X A3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_3
+#
+DEF adc_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_3
+#
+DEF dac_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.cir b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.cir new file mode 100644 index 00000000..9356242a --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.cir @@ -0,0 +1,36 @@ +* C:\Users\malli\eSim-Workspace\4023_test\4023_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 15:46:37
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U7-Pad4_ Net-_U7-Pad5_ Net-_U8-Pad4_ Net-_U8-Pad5_ Net-_U8-Pad6_ Net-_U9-Pad2_ ? Net-_U7-Pad6_ Net-_U9-Pad1_ Net-_U9-Pad3_ Net-_U10-Pad6_ Net-_U10-Pad5_ Net-_U10-Pad4_ ? 4023
+U8 a2 b2 c2 Net-_U8-Pad4_ Net-_U8-Pad5_ Net-_U8-Pad6_ adc_bridge_3
+U7 a1 b1 c1 Net-_U7-Pad4_ Net-_U7-Pad5_ Net-_U7-Pad6_ adc_bridge_3
+U10 a3 b3 c3 Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U10-Pad6_ adc_bridge_3
+U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U9-Pad3_ q1 q2 q3 dac_bridge_3
+v1 a1 GND DC
+v2 b1 GND DC
+v3 c1 GND DC
+v4 a2 GND DC
+v5 b2 GND DC
+v6 c2 GND DC
+v7 a3 GND DC
+v8 b3 GND DC
+v9 c3 GND DC
+U16 b3 plot_v1
+U12 a3 plot_v1
+U14 c3 plot_v1
+U2 b2 plot_v1
+U5 c2 plot_v1
+U4 a2 plot_v1
+U3 c1 plot_v1
+U6 a1 plot_v1
+U1 b1 plot_v1
+U13 q3 plot_v1
+U15 q2 plot_v1
+U11 q1 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.cir.out b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.cir.out new file mode 100644 index 00000000..7daf875f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.cir.out @@ -0,0 +1,62 @@ +* c:\users\malli\esim-workspace\4023_test\4023_test.cir
+
+.include 4023.sub
+x1 net-_u7-pad4_ net-_u7-pad5_ net-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ net-_u9-pad2_ ? net-_u7-pad6_ net-_u9-pad1_ net-_u9-pad3_ net-_u10-pad6_ net-_u10-pad5_ net-_u10-pad4_ ? 4023
+* u8 a2 b2 c2 net-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ adc_bridge_3
+* u7 a1 b1 c1 net-_u7-pad4_ net-_u7-pad5_ net-_u7-pad6_ adc_bridge_3
+* u10 a3 b3 c3 net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ adc_bridge_3
+* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ q1 q2 q3 dac_bridge_3
+v1 a1 gnd dc 5
+v2 b1 gnd dc 5
+v3 c1 gnd dc 5
+v4 a2 gnd dc 5
+v5 b2 gnd dc 5
+v6 c2 gnd dc 5
+v7 a3 gnd dc 5
+v8 b3 gnd dc 5
+v9 c3 gnd dc 5
+* u16 b3 plot_v1
+* u12 a3 plot_v1
+* u14 c3 plot_v1
+* u2 b2 plot_v1
+* u5 c2 plot_v1
+* u4 a2 plot_v1
+* u3 c1 plot_v1
+* u6 a1 plot_v1
+* u1 b1 plot_v1
+* u13 q3 plot_v1
+* u15 q2 plot_v1
+* u11 q1 plot_v1
+a1 [a2 b2 c2 ] [net-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ ] u8
+a2 [a1 b1 c1 ] [net-_u7-pad4_ net-_u7-pad5_ net-_u7-pad6_ ] u7
+a3 [a3 b3 c3 ] [net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ ] u10
+a4 [net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ ] [q1 q2 q3 ] u9
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u8 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u7 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u10 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge
+.model u9 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(b3)
+plot v(a3)
+plot v(c3)
+plot v(b2)
+plot v(c2)
+plot v(a2)
+plot v(c1)
+plot v(a1)
+plot v(b1)
+plot v(q3)
+plot v(q2)
+plot v(q1)
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro new file mode 100644 index 00000000..e4c3c722 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro @@ -0,0 +1,45 @@ +update=06/01/19 15:31:12
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.proj b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.proj new file mode 100644 index 00000000..eb21693a --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.proj @@ -0,0 +1 @@ +schematicFile 4023_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch new file mode 100644 index 00000000..37e50cf7 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch @@ -0,0 +1,575 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4023 X1
+U 1 1 5CF24CF9
+P 5300 3900
+F 0 "X1" H 5300 3800 60 0000 C CNN
+F 1 "4023" H 5300 4000 60 0000 C CNN
+F 2 "" H 5300 3900 60 0000 C CNN
+F 3 "" H 5300 3900 60 0000 C CNN
+ 1 5300 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_3 U8
+U 1 1 5CF24D5D
+P 3450 4500
+F 0 "U8" H 3450 4500 60 0000 C CNN
+F 1 "adc_bridge_3" H 3450 4650 60 0000 C CNN
+F 2 "" H 3450 4500 60 0000 C CNN
+F 3 "" H 3450 4500 60 0000 C CNN
+ 1 3450 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_3 U7
+U 1 1 5CF24DB6
+P 3400 2850
+F 0 "U7" H 3400 2850 60 0000 C CNN
+F 1 "adc_bridge_3" H 3400 3000 60 0000 C CNN
+F 2 "" H 3400 2850 60 0000 C CNN
+F 3 "" H 3400 2850 60 0000 C CNN
+ 1 3400 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_3 U10
+U 1 1 5CF24DFF
+P 7000 3750
+F 0 "U10" H 7000 3750 60 0000 C CNN
+F 1 "adc_bridge_3" H 7000 3900 60 0000 C CNN
+F 2 "" H 7000 3750 60 0000 C CNN
+F 3 "" H 7000 3750 60 0000 C CNN
+ 1 7000 3750
+ -1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_3 U9
+U 1 1 5CF24ECA
+P 6800 5750
+F 0 "U9" H 6800 5750 60 0000 C CNN
+F 1 "dac_bridge_3" H 6800 5900 60 0000 C CNN
+F 2 "" H 6800 5750 60 0000 C CNN
+F 3 "" H 6800 5750 60 0000 C CNN
+ 1 6800 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v1
+U 1 1 5CF24F1F
+P 1700 2350
+F 0 "v1" H 1500 2450 60 0000 C CNN
+F 1 "DC" H 1500 2300 60 0000 C CNN
+F 2 "R1" H 1400 2350 60 0000 C CNN
+F 3 "" H 1700 2350 60 0000 C CNN
+ 1 1700 2350
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v2
+U 1 1 5CF24F90
+P 1700 2900
+F 0 "v2" H 1500 3000 60 0000 C CNN
+F 1 "DC" H 1500 2850 60 0000 C CNN
+F 2 "R1" H 1400 2900 60 0000 C CNN
+F 3 "" H 1700 2900 60 0000 C CNN
+ 1 1700 2900
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v3
+U 1 1 5CF24FC7
+P 1700 3450
+F 0 "v3" H 1500 3550 60 0000 C CNN
+F 1 "DC" H 1500 3400 60 0000 C CNN
+F 2 "R1" H 1400 3450 60 0000 C CNN
+F 3 "" H 1700 3450 60 0000 C CNN
+ 1 1700 3450
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v4
+U 1 1 5CF25001
+P 1750 4000
+F 0 "v4" H 1550 4100 60 0000 C CNN
+F 1 "DC" H 1550 3950 60 0000 C CNN
+F 2 "R1" H 1450 4000 60 0000 C CNN
+F 3 "" H 1750 4000 60 0000 C CNN
+ 1 1750 4000
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v5
+U 1 1 5CF25044
+P 1750 4550
+F 0 "v5" H 1550 4650 60 0000 C CNN
+F 1 "DC" H 1550 4500 60 0000 C CNN
+F 2 "R1" H 1450 4550 60 0000 C CNN
+F 3 "" H 1750 4550 60 0000 C CNN
+ 1 1750 4550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v6
+U 1 1 5CF25082
+P 1750 5050
+F 0 "v6" H 1550 5150 60 0000 C CNN
+F 1 "DC" H 1550 5000 60 0000 C CNN
+F 2 "R1" H 1450 5050 60 0000 C CNN
+F 3 "" H 1750 5050 60 0000 C CNN
+ 1 1750 5050
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 2800 2800 2800 2350
+Wire Wire Line
+ 2800 2350 2150 2350
+Wire Wire Line
+ 2150 2900 2800 2900
+Wire Wire Line
+ 2150 3450 2800 3450
+Wire Wire Line
+ 2800 3450 2800 3000
+Wire Wire Line
+ 2200 4000 2850 4000
+Wire Wire Line
+ 2850 3900 2850 4450
+Wire Wire Line
+ 2850 4550 2200 4550
+Wire Wire Line
+ 2200 5050 2850 5050
+Wire Wire Line
+ 2850 5050 2850 4650
+Wire Wire Line
+ 900 5050 1300 5050
+Wire Wire Line
+ 900 2350 900 5050
+Wire Wire Line
+ 900 2350 1250 2350
+Wire Wire Line
+ 1250 2900 900 2900
+Connection ~ 900 2900
+Wire Wire Line
+ 1250 3450 900 3450
+Connection ~ 900 3450
+Wire Wire Line
+ 1300 4000 900 4000
+Connection ~ 900 4000
+Wire Wire Line
+ 1300 4550 900 4550
+Connection ~ 900 4550
+Wire Wire Line
+ 3950 2800 4500 2800
+Wire Wire Line
+ 4500 2800 4500 3600
+Wire Wire Line
+ 4500 3600 4800 3600
+Wire Wire Line
+ 3950 2900 4400 2900
+Wire Wire Line
+ 4400 2900 4400 3700
+Wire Wire Line
+ 4400 3700 4800 3700
+Wire Wire Line
+ 3950 3000 5900 3000
+Wire Wire Line
+ 5900 3000 5900 4200
+Wire Wire Line
+ 5900 4200 5800 4200
+Wire Wire Line
+ 6450 3900 5800 3900
+Wire Wire Line
+ 5800 3800 6450 3800
+Wire Wire Line
+ 6450 3700 5800 3700
+Wire Wire Line
+ 4000 4450 4000 3800
+Wire Wire Line
+ 4000 3800 4800 3800
+Wire Wire Line
+ 4800 3900 4100 3900
+Wire Wire Line
+ 4100 3900 4100 4550
+Wire Wire Line
+ 4100 4550 4000 4550
+Wire Wire Line
+ 4000 4650 4200 4650
+Wire Wire Line
+ 4200 4650 4200 4000
+Wire Wire Line
+ 4200 4000 4800 4000
+Wire Wire Line
+ 4800 4100 4450 4100
+Wire Wire Line
+ 4450 4100 4450 5800
+Wire Wire Line
+ 4450 5800 6200 5800
+Wire Wire Line
+ 5800 4100 5850 4100
+Wire Wire Line
+ 5850 4100 5850 5700
+Wire Wire Line
+ 5850 5700 6200 5700
+Wire Wire Line
+ 5800 4000 5950 4000
+Wire Wire Line
+ 5950 4000 5950 5900
+Wire Wire Line
+ 5950 5900 6200 5900
+$Comp
+L DC v7
+U 1 1 5CF25804
+P 9250 3250
+F 0 "v7" H 9050 3350 60 0000 C CNN
+F 1 "DC" H 9050 3200 60 0000 C CNN
+F 2 "R1" H 8950 3250 60 0000 C CNN
+F 3 "" H 9250 3250 60 0000 C CNN
+ 1 9250 3250
+ 0 -1 1 0
+$EndComp
+$Comp
+L DC v8
+U 1 1 5CF2580A
+P 9250 3800
+F 0 "v8" H 9050 3900 60 0000 C CNN
+F 1 "DC" H 9050 3750 60 0000 C CNN
+F 2 "R1" H 8950 3800 60 0000 C CNN
+F 3 "" H 9250 3800 60 0000 C CNN
+ 1 9250 3800
+ 0 -1 1 0
+$EndComp
+$Comp
+L DC v9
+U 1 1 5CF25810
+P 9250 4300
+F 0 "v9" H 9050 4400 60 0000 C CNN
+F 1 "DC" H 9050 4250 60 0000 C CNN
+F 2 "R1" H 8950 4300 60 0000 C CNN
+F 3 "" H 9250 4300 60 0000 C CNN
+ 1 9250 4300
+ 0 -1 1 0
+$EndComp
+Wire Wire Line
+ 7600 3250 8800 3250
+Wire Wire Line
+ 7600 3800 8800 3800
+Wire Wire Line
+ 7600 4300 8800 4300
+Wire Wire Line
+ 10150 4300 9700 4300
+Wire Wire Line
+ 9700 3250 10150 3250
+Wire Wire Line
+ 9700 3800 10500 3800
+Wire Wire Line
+ 7600 3250 7600 3700
+Wire Wire Line
+ 7600 4300 7600 3900
+Wire Wire Line
+ 10150 3250 10150 4300
+Connection ~ 10150 3800
+Wire Wire Line
+ 10500 3800 10500 4050
+NoConn ~ 5800 3600
+NoConn ~ 4800 4200
+$Comp
+L plot_v1 U16
+U 1 1 5CF25B68
+P 8450 3050
+F 0 "U16" H 8450 3550 60 0000 C CNN
+F 1 "plot_v1" H 8650 3400 60 0000 C CNN
+F 2 "" H 8450 3050 60 0000 C CNN
+F 3 "" H 8450 3050 60 0000 C CNN
+ 1 8450 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U12
+U 1 1 5CF25BF8
+P 7750 3100
+F 0 "U12" H 7750 3600 60 0000 C CNN
+F 1 "plot_v1" H 7950 3450 60 0000 C CNN
+F 2 "" H 7750 3100 60 0000 C CNN
+F 3 "" H 7750 3100 60 0000 C CNN
+ 1 7750 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U14
+U 1 1 5CF25C4E
+P 8050 4300
+F 0 "U14" H 8050 4800 60 0000 C CNN
+F 1 "plot_v1" H 8250 4650 60 0000 C CNN
+F 2 "" H 8050 4300 60 0000 C CNN
+F 3 "" H 8050 4300 60 0000 C CNN
+ 1 8050 4300
+ -1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U2
+U 1 1 5CF25E02
+P 2450 5100
+F 0 "U2" H 2450 5600 60 0000 C CNN
+F 1 "plot_v1" H 2650 5450 60 0000 C CNN
+F 2 "" H 2450 5100 60 0000 C CNN
+F 3 "" H 2450 5100 60 0000 C CNN
+ 1 2450 5100
+ -1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 5CF25F10
+P 3000 5000
+F 0 "U5" H 3000 5500 60 0000 C CNN
+F 1 "plot_v1" H 3200 5350 60 0000 C CNN
+F 2 "" H 3000 5000 60 0000 C CNN
+F 3 "" H 3000 5000 60 0000 C CNN
+ 1 3000 5000
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 5CF25F95
+P 2950 3900
+F 0 "U4" H 2950 4400 60 0000 C CNN
+F 1 "plot_v1" H 3150 4250 60 0000 C CNN
+F 2 "" H 2950 3900 60 0000 C CNN
+F 3 "" H 2950 3900 60 0000 C CNN
+ 1 2950 3900
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U3
+U 1 1 5CF25FFB
+P 2850 3250
+F 0 "U3" H 2850 3750 60 0000 C CNN
+F 1 "plot_v1" H 3050 3600 60 0000 C CNN
+F 2 "" H 2850 3250 60 0000 C CNN
+F 3 "" H 2850 3250 60 0000 C CNN
+ 1 2850 3250
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 5CF260BA
+P 3100 2400
+F 0 "U6" H 3100 2900 60 0000 C CNN
+F 1 "plot_v1" H 3300 2750 60 0000 C CNN
+F 2 "" H 3100 2400 60 0000 C CNN
+F 3 "" H 3100 2400 60 0000 C CNN
+ 1 3100 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 5CF26164
+P 2400 2300
+F 0 "U1" H 2400 2800 60 0000 C CNN
+F 1 "plot_v1" H 2600 2650 60 0000 C CNN
+F 2 "" H 2400 2300 60 0000 C CNN
+F 3 "" H 2400 2300 60 0000 C CNN
+ 1 2400 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 5CF261BC
+P 700 3900
+F 0 "#PWR01" H 700 3650 50 0001 C CNN
+F 1 "eSim_GND" H 700 3750 50 0000 C CNN
+F 2 "" H 700 3900 50 0001 C CNN
+F 3 "" H 700 3900 50 0001 C CNN
+ 1 700 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 5CF262FB
+P 700 3700
+F 0 "#FLG02" H 700 3795 50 0001 C CNN
+F 1 "PWR_FLAG" H 700 3880 50 0000 C CNN
+F 2 "" H 700 3700 50 0000 C CNN
+F 3 "" H 700 3700 50 0000 C CNN
+ 1 700 3700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 700 3700 700 3900
+Wire Wire Line
+ 700 3800 900 3800
+Connection ~ 900 3800
+Connection ~ 700 3800
+Wire Wire Line
+ 3100 2200 3100 2450
+Wire Wire Line
+ 3100 2450 2800 2450
+Connection ~ 2800 2450
+Wire Wire Line
+ 2400 2100 2400 2900
+Connection ~ 2400 2900
+Wire Wire Line
+ 3050 3250 2800 3250
+Connection ~ 2800 3250
+Wire Wire Line
+ 3150 3900 2850 3900
+Connection ~ 2850 4000
+Wire Wire Line
+ 3200 5000 2850 5000
+Connection ~ 2850 5000
+Wire Wire Line
+ 2450 5300 2450 4550
+Connection ~ 2450 4550
+Wire Wire Line
+ 7750 2900 7750 3250
+Connection ~ 7750 3250
+Wire Wire Line
+ 8450 2850 8450 3800
+Connection ~ 8450 3800
+Wire Wire Line
+ 8050 4500 8050 4300
+Connection ~ 8050 4300
+$Comp
+L eSim_GND #PWR03
+U 1 1 5CF26B7B
+P 10500 4050
+F 0 "#PWR03" H 10500 3800 50 0001 C CNN
+F 1 "eSim_GND" H 10500 3900 50 0000 C CNN
+F 2 "" H 10500 4050 50 0001 C CNN
+F 3 "" H 10500 4050 50 0001 C CNN
+ 1 10500 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U13
+U 1 1 5CF26CF6
+P 7900 6100
+F 0 "U13" H 7900 6600 60 0000 C CNN
+F 1 "plot_v1" H 8100 6450 60 0000 C CNN
+F 2 "" H 7900 6100 60 0000 C CNN
+F 3 "" H 7900 6100 60 0000 C CNN
+ 1 7900 6100
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U15
+U 1 1 5CF26DF2
+P 8250 5700
+F 0 "U15" H 8250 6200 60 0000 C CNN
+F 1 "plot_v1" H 8450 6050 60 0000 C CNN
+F 2 "" H 8250 5700 60 0000 C CNN
+F 3 "" H 8250 5700 60 0000 C CNN
+ 1 8250 5700
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U11
+U 1 1 5CF26E57
+P 7600 5200
+F 0 "U11" H 7600 5700 60 0000 C CNN
+F 1 "plot_v1" H 7800 5550 60 0000 C CNN
+F 2 "" H 7600 5200 60 0000 C CNN
+F 3 "" H 7600 5200 60 0000 C CNN
+ 1 7600 5200
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 7800 5200 7350 5200
+Wire Wire Line
+ 7350 5200 7350 5700
+Wire Wire Line
+ 7350 5800 7850 5800
+Wire Wire Line
+ 7850 5800 7850 5700
+Wire Wire Line
+ 7850 5700 8450 5700
+Wire Wire Line
+ 7350 5900 7650 5900
+Wire Wire Line
+ 7650 5900 7650 6100
+Wire Wire Line
+ 7450 6100 8100 6100
+Text GLabel 7200 5300 0 60 Input ~ 0
+q1
+Text GLabel 7700 5650 1 60 Input ~ 0
+q2
+Text GLabel 7450 6100 0 60 Input ~ 0
+q3
+Text GLabel 7900 4400 0 60 Input ~ 0
+c3
+Text GLabel 8300 3500 0 60 Input ~ 0
+b3
+Text GLabel 7600 3050 0 60 Input ~ 0
+a3
+Wire Wire Line
+ 7550 3050 7750 3050
+Connection ~ 7750 3050
+Wire Wire Line
+ 8300 3500 8450 3500
+Connection ~ 8450 3500
+Wire Wire Line
+ 7900 4400 8050 4400
+Connection ~ 8050 4400
+Wire Wire Line
+ 7200 5300 7350 5300
+Connection ~ 7350 5300
+Wire Wire Line
+ 7700 5650 7700 5800
+Connection ~ 7700 5800
+Connection ~ 7650 6100
+Text GLabel 2350 4750 0 60 Input ~ 0
+b2
+Text GLabel 3050 5150 3 60 Input ~ 0
+c2
+Text GLabel 3000 4000 3 60 Input ~ 0
+a2
+Text GLabel 2950 3400 3 60 Input ~ 0
+c1
+Text GLabel 2250 2650 0 60 Input ~ 0
+b1
+Text GLabel 3000 2300 0 60 Input ~ 0
+a1
+Wire Wire Line
+ 3000 2300 3100 2300
+Connection ~ 3100 2300
+Wire Wire Line
+ 2250 2650 2400 2650
+Connection ~ 2400 2650
+Wire Wire Line
+ 2950 3400 2950 3250
+Connection ~ 2950 3250
+Wire Wire Line
+ 3000 4000 3000 3900
+Connection ~ 3000 3900
+Wire Wire Line
+ 2350 4750 2450 4750
+Connection ~ 2450 4750
+Wire Wire Line
+ 3050 5150 3050 5000
+Connection ~ 3050 5000
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test_Previous_Values.xml new file mode 100644 index 00000000..63b00296 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">5</field1></v4><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v7 name="Source type">dc<field1 name="Value">5</field1></v7><v8 name="Source type">dc<field1 name="Value">5</field1></v8><v9 name="Source type">dc<field1 name="Value">0</field1></v9></source><model><u8 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u8><u7 name="type">adc_bridge<field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter value for in_low (default=1.0)" /></u7><u10 name="type">adc_bridge<field9 name="Enter Fall Delay (default=1.0e-9)" /><field10 name="Enter value for in_high (default=2.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter value for in_low (default=1.0)" /></u10><u9 name="type">dac_bridge<field13 name="Enter value for input load (default=1.0e-12)" /><field14 name="Enter value for out_low (default=0.0)" /><field15 name="Enter value for out_high (default=5.0)" /><field16 name="Enter the Rise Time (default=1.0e-9)" /><field17 name="Enter the Fall Time (default=1.0e-9)" /><field18 name="Enter value for out_undef (default=0.5)" /></u9></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4023</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/analysis b/Examples/Analysis_Of_Digital_IC/4023_test/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028-cache.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028-cache.lib new file mode 100644 index 00000000..4ba19fb8 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir new file mode 100644 index 00000000..c13da65d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U9 Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor
+U10 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor
+U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor
+U6 Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor
+U7 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor
+U8 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor
+U2 Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter
+U3 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter
+U4 Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter
+U5 Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter
+U15 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and
+U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and
+U17 Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and
+U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and
+U19 Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and
+U20 Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and
+U21 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and
+U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT
+U22 Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir.out b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir.out new file mode 100644 index 00000000..93e14b93 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir.out @@ -0,0 +1,96 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
+
+* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
+* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
+* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
+* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
+* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter
+* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter
+* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter
+* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
+* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
+* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
+* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
+* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
+* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
+* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
+* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
+a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
+a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
+a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
+a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
+a8 net-_u1-pad10_ net-_u11-pad1_ u2
+a9 net-_u1-pad13_ net-_u10-pad2_ u3
+a10 net-_u1-pad12_ net-_u4-pad2_ u4
+a11 net-_u1-pad11_ net-_u5-pad2_ u5
+a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
+a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
+a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
+a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
+a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
+a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
+a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
+a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
+a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.pro b/Examples/Analysis_Of_Digital_IC/4028_test/4028.pro new file mode 100644 index 00000000..6f7acdde --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:43:40
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.sch b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sch new file mode 100644 index 00000000..a487c693 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sch @@ -0,0 +1,628 @@ +EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nor U9
+U 1 1 5CF0FE64
+P 3750 2500
+F 0 "U9" H 3750 2500 60 0000 C CNN
+F 1 "d_nor" H 3800 2600 60 0000 C CNN
+F 2 "" H 3750 2500 60 0000 C CNN
+F 3 "" H 3750 2500 60 0000 C CNN
+ 1 3750 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U10
+U 1 1 5CF0FEA4
+P 3750 3050
+F 0 "U10" H 3750 3050 60 0000 C CNN
+F 1 "d_nor" H 3800 3150 60 0000 C CNN
+F 2 "" H 3750 3050 60 0000 C CNN
+F 3 "" H 3750 3050 60 0000 C CNN
+ 1 3750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U11
+U 1 1 5CF0FECC
+P 3750 3550
+F 0 "U11" H 3750 3550 60 0000 C CNN
+F 1 "d_nor" H 3800 3650 60 0000 C CNN
+F 2 "" H 3750 3550 60 0000 C CNN
+F 3 "" H 3750 3550 60 0000 C CNN
+ 1 3750 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U12
+U 1 1 5CF0FEF5
+P 3750 4150
+F 0 "U12" H 3750 4150 60 0000 C CNN
+F 1 "d_nor" H 3800 4250 60 0000 C CNN
+F 2 "" H 3750 4150 60 0000 C CNN
+F 3 "" H 3750 4150 60 0000 C CNN
+ 1 3750 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 5CF0FF23
+P 3700 4750
+F 0 "U6" H 3700 4750 60 0000 C CNN
+F 1 "d_nor" H 3750 4850 60 0000 C CNN
+F 2 "" H 3700 4750 60 0000 C CNN
+F 3 "" H 3700 4750 60 0000 C CNN
+ 1 3700 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 5CF0FF59
+P 3700 5250
+F 0 "U7" H 3700 5250 60 0000 C CNN
+F 1 "d_nor" H 3750 5350 60 0000 C CNN
+F 2 "" H 3700 5250 60 0000 C CNN
+F 3 "" H 3700 5250 60 0000 C CNN
+ 1 3700 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U8
+U 1 1 5CF0FFA9
+P 3750 2000
+F 0 "U8" H 3750 2000 60 0000 C CNN
+F 1 "d_nor" H 3800 2100 60 0000 C CNN
+F 2 "" H 3750 2000 60 0000 C CNN
+F 3 "" H 3750 2000 60 0000 C CNN
+ 1 3750 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 5CF1003A
+P 2150 2400
+F 0 "U2" H 2150 2300 60 0000 C CNN
+F 1 "d_inverter" H 2150 2550 60 0000 C CNN
+F 2 "" H 2200 2350 60 0000 C CNN
+F 3 "" H 2200 2350 60 0000 C CNN
+ 1 2150 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 5CF1007F
+P 2150 3300
+F 0 "U3" H 2150 3200 60 0000 C CNN
+F 1 "d_inverter" H 2150 3450 60 0000 C CNN
+F 2 "" H 2200 3250 60 0000 C CNN
+F 3 "" H 2200 3250 60 0000 C CNN
+ 1 2150 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 5CF100CC
+P 2150 4150
+F 0 "U4" H 2150 4050 60 0000 C CNN
+F 1 "d_inverter" H 2150 4300 60 0000 C CNN
+F 2 "" H 2200 4100 60 0000 C CNN
+F 3 "" H 2200 4100 60 0000 C CNN
+ 1 2150 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 5CF10114
+P 2150 4900
+F 0 "U5" H 2150 4800 60 0000 C CNN
+F 1 "d_inverter" H 2150 5050 60 0000 C CNN
+F 2 "" H 2200 4850 60 0000 C CNN
+F 3 "" H 2200 4850 60 0000 C CNN
+ 1 2150 4900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1400 2400 1850 2400
+Wire Wire Line
+ 1400 3300 1850 3300
+Wire Wire Line
+ 1450 4150 1850 4150
+Wire Wire Line
+ 1450 4900 1850 4900
+Wire Wire Line
+ 2450 4900 2500 4900
+Wire Wire Line
+ 2500 4900 2500 5250
+Wire Wire Line
+ 2500 5250 3250 5250
+Wire Wire Line
+ 2450 4150 2550 4150
+Wire Wire Line
+ 2550 4150 2550 4650
+Wire Wire Line
+ 2550 4650 3250 4650
+Wire Wire Line
+ 2450 3300 2550 3300
+Wire Wire Line
+ 2550 3300 2550 3550
+Wire Wire Line
+ 2550 3550 3300 3550
+Wire Wire Line
+ 2450 2400 2450 2500
+Wire Wire Line
+ 2450 2500 3300 2500
+Wire Wire Line
+ 2800 2500 2800 3450
+Wire Wire Line
+ 2800 3450 3300 3450
+Connection ~ 2800 2500
+Wire Wire Line
+ 1650 2400 1650 1900
+Wire Wire Line
+ 1650 1900 3300 1900
+Connection ~ 1650 2400
+Wire Wire Line
+ 3300 2000 2850 2000
+Wire Wire Line
+ 2850 2000 2850 3000
+Wire Wire Line
+ 2850 3000 1650 3000
+Wire Wire Line
+ 1650 3000 1650 3300
+Connection ~ 1650 3300
+Wire Wire Line
+ 2850 2400 3300 2400
+Connection ~ 2850 2400
+Wire Wire Line
+ 2950 1900 2950 2950
+Wire Wire Line
+ 2950 2950 3300 2950
+Connection ~ 2950 1900
+Wire Wire Line
+ 3100 3550 3100 3050
+Wire Wire Line
+ 3100 3050 3300 3050
+Connection ~ 3100 3550
+Wire Wire Line
+ 1650 3900 1650 4150
+Wire Wire Line
+ 1650 3900 3050 3900
+Wire Wire Line
+ 3050 3900 3050 5150
+Wire Wire Line
+ 3050 4050 3300 4050
+Connection ~ 1650 4150
+Wire Wire Line
+ 1750 4900 1750 5150
+Wire Wire Line
+ 1750 5150 2750 5150
+Connection ~ 1750 4900
+Wire Wire Line
+ 2750 5150 2750 4150
+Wire Wire Line
+ 2750 4150 3300 4150
+Wire Wire Line
+ 2750 4750 3250 4750
+Connection ~ 2750 4750
+Wire Wire Line
+ 3050 5150 3250 5150
+Connection ~ 3050 4050
+$Comp
+L d_and U15
+U 1 1 5CF106B1
+P 6600 1850
+F 0 "U15" H 6600 1850 60 0000 C CNN
+F 1 "d_and" H 6650 1950 60 0000 C CNN
+F 2 "" H 6600 1850 60 0000 C CNN
+F 3 "" H 6600 1850 60 0000 C CNN
+ 1 6600 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U16
+U 1 1 5CF10756
+P 6600 2350
+F 0 "U16" H 6600 2350 60 0000 C CNN
+F 1 "d_and" H 6650 2450 60 0000 C CNN
+F 2 "" H 6600 2350 60 0000 C CNN
+F 3 "" H 6600 2350 60 0000 C CNN
+ 1 6600 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U17
+U 1 1 5CF107A1
+P 6600 2800
+F 0 "U17" H 6600 2800 60 0000 C CNN
+F 1 "d_and" H 6650 2900 60 0000 C CNN
+F 2 "" H 6600 2800 60 0000 C CNN
+F 3 "" H 6600 2800 60 0000 C CNN
+ 1 6600 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U18
+U 1 1 5CF107E9
+P 6600 3200
+F 0 "U18" H 6600 3200 60 0000 C CNN
+F 1 "d_and" H 6650 3300 60 0000 C CNN
+F 2 "" H 6600 3200 60 0000 C CNN
+F 3 "" H 6600 3200 60 0000 C CNN
+ 1 6600 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U19
+U 1 1 5CF10834
+P 6600 3650
+F 0 "U19" H 6600 3650 60 0000 C CNN
+F 1 "d_and" H 6650 3750 60 0000 C CNN
+F 2 "" H 6600 3650 60 0000 C CNN
+F 3 "" H 6600 3650 60 0000 C CNN
+ 1 6600 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U20
+U 1 1 5CF1087E
+P 6600 4050
+F 0 "U20" H 6600 4050 60 0000 C CNN
+F 1 "d_and" H 6650 4150 60 0000 C CNN
+F 2 "" H 6600 4050 60 0000 C CNN
+F 3 "" H 6600 4050 60 0000 C CNN
+ 1 6600 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U21
+U 1 1 5CF108F9
+P 6600 4450
+F 0 "U21" H 6600 4450 60 0000 C CNN
+F 1 "d_and" H 6650 4550 60 0000 C CNN
+F 2 "" H 6600 4450 60 0000 C CNN
+F 3 "" H 6600 4450 60 0000 C CNN
+ 1 6600 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 5CF1094D
+P 6550 4900
+F 0 "U13" H 6550 4900 60 0000 C CNN
+F 1 "d_and" H 6600 5000 60 0000 C CNN
+F 2 "" H 6550 4900 60 0000 C CNN
+F 3 "" H 6550 4900 60 0000 C CNN
+ 1 6550 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 5CF109A6
+P 6550 5350
+F 0 "U14" H 6550 5350 60 0000 C CNN
+F 1 "d_and" H 6600 5450 60 0000 C CNN
+F 2 "" H 6550 5350 60 0000 C CNN
+F 3 "" H 6550 5350 60 0000 C CNN
+ 1 6550 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CF11966
+P 1150 2400
+F 0 "U1" H 1200 2500 30 0000 C CNN
+F 1 "PORT" H 1150 2400 30 0000 C CNN
+F 2 "" H 1150 2400 60 0000 C CNN
+F 3 "" H 1150 2400 60 0000 C CNN
+ 10 1150 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CF119D4
+P 1150 3300
+F 0 "U1" H 1200 3400 30 0000 C CNN
+F 1 "PORT" H 1150 3300 30 0000 C CNN
+F 2 "" H 1150 3300 60 0000 C CNN
+F 3 "" H 1150 3300 60 0000 C CNN
+ 13 1150 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CF11AFC
+P 1200 4150
+F 0 "U1" H 1250 4250 30 0000 C CNN
+F 1 "PORT" H 1200 4150 30 0000 C CNN
+F 2 "" H 1200 4150 60 0000 C CNN
+F 3 "" H 1200 4150 60 0000 C CNN
+ 12 1200 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CF11B6B
+P 1200 4900
+F 0 "U1" H 1250 5000 30 0000 C CNN
+F 1 "PORT" H 1200 4900 30 0000 C CNN
+F 2 "" H 1200 4900 60 0000 C CNN
+F 3 "" H 1200 4900 60 0000 C CNN
+ 11 1200 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CF11BDB
+P 8000 1800
+F 0 "U1" H 8050 1900 30 0000 C CNN
+F 1 "PORT" H 8000 1800 30 0000 C CNN
+F 2 "" H 8000 1800 60 0000 C CNN
+F 3 "" H 8000 1800 60 0000 C CNN
+ 3 8000 1800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CF11F59
+P 8000 2300
+F 0 "U1" H 8050 2400 30 0000 C CNN
+F 1 "PORT" H 8000 2300 30 0000 C CNN
+F 2 "" H 8000 2300 60 0000 C CNN
+F 3 "" H 8000 2300 60 0000 C CNN
+ 14 8000 2300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CF11FC5
+P 8000 2750
+F 0 "U1" H 8050 2850 30 0000 C CNN
+F 1 "PORT" H 8000 2750 30 0000 C CNN
+F 2 "" H 8000 2750 60 0000 C CNN
+F 3 "" H 8000 2750 60 0000 C CNN
+ 2 8000 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 5CF1204F
+P 8000 3150
+F 0 "U1" H 8050 3250 30 0000 C CNN
+F 1 "PORT" H 8000 3150 30 0000 C CNN
+F 2 "" H 8000 3150 60 0000 C CNN
+F 3 "" H 8000 3150 60 0000 C CNN
+ 15 8000 3150
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CF120C5
+P 7950 3600
+F 0 "U1" H 8000 3700 30 0000 C CNN
+F 1 "PORT" H 7950 3600 30 0000 C CNN
+F 2 "" H 7950 3600 60 0000 C CNN
+F 3 "" H 7950 3600 60 0000 C CNN
+ 1 7950 3600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CF1213C
+P 7950 4000
+F 0 "U1" H 8000 4100 30 0000 C CNN
+F 1 "PORT" H 7950 4000 30 0000 C CNN
+F 2 "" H 7950 4000 60 0000 C CNN
+F 3 "" H 7950 4000 60 0000 C CNN
+ 6 7950 4000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CF121B2
+P 7900 4400
+F 0 "U1" H 7950 4500 30 0000 C CNN
+F 1 "PORT" H 7900 4400 30 0000 C CNN
+F 2 "" H 7900 4400 60 0000 C CNN
+F 3 "" H 7900 4400 60 0000 C CNN
+ 7 7900 4400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CF1223D
+P 7900 4850
+F 0 "U1" H 7950 4950 30 0000 C CNN
+F 1 "PORT" H 7900 4850 30 0000 C CNN
+F 2 "" H 7900 4850 60 0000 C CNN
+F 3 "" H 7900 4850 60 0000 C CNN
+ 4 7900 4850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CF1237B
+P 7900 5300
+F 0 "U1" H 7950 5400 30 0000 C CNN
+F 1 "PORT" H 7900 5300 30 0000 C CNN
+F 2 "" H 7900 5300 60 0000 C CNN
+F 3 "" H 7900 5300 60 0000 C CNN
+ 9 7900 5300
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7750 1800 7050 1800
+Wire Wire Line
+ 7050 2300 7750 2300
+Wire Wire Line
+ 7750 2750 7050 2750
+Wire Wire Line
+ 7050 3150 7750 3150
+Wire Wire Line
+ 7700 3600 7050 3600
+Wire Wire Line
+ 7050 4000 7700 4000
+Wire Wire Line
+ 7650 4400 7050 4400
+Wire Wire Line
+ 7000 4850 7650 4850
+Wire Wire Line
+ 7650 5300 7000 5300
+$Comp
+L d_and U22
+U 1 1 5CF14904
+P 6550 5800
+F 0 "U22" H 6550 5800 60 0000 C CNN
+F 1 "d_and" H 6600 5900 60 0000 C CNN
+F 2 "" H 6550 5800 60 0000 C CNN
+F 3 "" H 6550 5800 60 0000 C CNN
+ 1 6550 5800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4200 1950 4600 1950
+Wire Wire Line
+ 4600 1750 4600 5250
+Wire Wire Line
+ 4600 1750 6150 1750
+Wire Wire Line
+ 4600 5250 6100 5250
+Connection ~ 4600 1950
+Wire Wire Line
+ 6100 5800 5900 5800
+Wire Wire Line
+ 5900 5800 5900 5350
+Wire Wire Line
+ 5900 5350 6100 5350
+Wire Wire Line
+ 5850 4900 6100 4900
+Wire Wire Line
+ 5850 3650 5850 4900
+Wire Wire Line
+ 5850 4450 6150 4450
+Wire Wire Line
+ 5850 4050 6150 4050
+Connection ~ 5850 4450
+Wire Wire Line
+ 5850 3650 6150 3650
+Connection ~ 5850 4050
+Wire Wire Line
+ 5050 3200 6150 3200
+Wire Wire Line
+ 5850 1850 5850 3200
+Wire Wire Line
+ 5850 2800 6150 2800
+Wire Wire Line
+ 5850 2350 6150 2350
+Connection ~ 5850 2800
+Wire Wire Line
+ 5850 1850 6150 1850
+Connection ~ 5850 2350
+Wire Wire Line
+ 4200 2450 4700 2450
+Wire Wire Line
+ 4700 2250 4700 5700
+Wire Wire Line
+ 4700 2250 6150 2250
+Wire Wire Line
+ 4200 3000 4800 3000
+Wire Wire Line
+ 4800 2700 4800 4350
+Wire Wire Line
+ 4800 2700 6150 2700
+Wire Wire Line
+ 4700 5700 6100 5700
+Connection ~ 4700 2450
+Wire Wire Line
+ 6150 3550 4600 3550
+Connection ~ 4600 3550
+Wire Wire Line
+ 6150 3950 4700 3950
+Connection ~ 4700 3950
+Wire Wire Line
+ 4800 4350 6150 4350
+Connection ~ 4800 3000
+Wire Wire Line
+ 4200 3500 4900 3500
+Wire Wire Line
+ 4900 3100 4900 4800
+Wire Wire Line
+ 4900 3100 6150 3100
+Wire Wire Line
+ 4900 4800 6100 4800
+Connection ~ 4900 3500
+Wire Wire Line
+ 4200 4100 5050 4100
+Wire Wire Line
+ 5050 4100 5050 3200
+Connection ~ 5850 3200
+Wire Wire Line
+ 4150 4700 5850 4700
+Connection ~ 5850 4700
+Wire Wire Line
+ 4150 5200 4500 5200
+Wire Wire Line
+ 4500 5200 4500 5550
+Wire Wire Line
+ 4500 5550 5900 5550
+Connection ~ 5900 5550
+$Comp
+L PORT U1
+U 5 1 5CF1563E
+P 7950 5750
+F 0 "U1" H 8000 5850 30 0000 C CNN
+F 1 "PORT" H 7950 5750 30 0000 C CNN
+F 2 "" H 7950 5750 60 0000 C CNN
+F 3 "" H 7950 5750 60 0000 C CNN
+ 5 7950 5750
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7700 5750 7000 5750
+$Comp
+L PORT U1
+U 8 1 5CF15953
+P 9550 4800
+F 0 "U1" H 9600 4900 30 0000 C CNN
+F 1 "PORT" H 9550 4800 30 0000 C CNN
+F 2 "" H 9550 4800 60 0000 C CNN
+F 3 "" H 9550 4800 60 0000 C CNN
+ 8 9550 4800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 5CF15A07
+P 9550 5250
+F 0 "U1" H 9600 5350 30 0000 C CNN
+F 1 "PORT" H 9550 5250 30 0000 C CNN
+F 2 "" H 9550 5250 60 0000 C CNN
+F 3 "" H 9550 5250 60 0000 C CNN
+ 16 9550 5250
+ -1 0 0 1
+$EndComp
+NoConn ~ 9300 4800
+NoConn ~ 9300 5250
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.sub b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sub new file mode 100644 index 00000000..5f9f3cf8 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sub @@ -0,0 +1,90 @@ +* Subcircuit 4028
+.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
+* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
+* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
+* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
+* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
+* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter
+* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter
+* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter
+* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
+* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
+* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
+* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
+* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
+* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
+* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
+* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
+a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
+a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
+a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
+a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
+a8 net-_u1-pad10_ net-_u11-pad1_ u2
+a9 net-_u1-pad13_ net-_u10-pad2_ u3
+a10 net-_u1-pad12_ net-_u4-pad2_ u4
+a11 net-_u1-pad11_ net-_u5-pad2_ u5
+a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
+a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
+a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
+a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
+a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
+a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
+a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
+a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
+a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4028
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4028_test/4028_Previous_Values.xml new file mode 100644 index 00000000..189fb200 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib new file mode 100644 index 00000000..43241731 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib @@ -0,0 +1,152 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4028
+#
+DEF 4028 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "4028" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X Q4 1 -500 350 200 R 50 50 1 1 O
+X Q2 2 -500 250 200 R 50 50 1 1 O
+X Q0 3 -500 150 200 R 50 50 1 1 O
+X Q7 4 -500 50 200 R 50 50 1 1 O
+X Q9 5 -500 -50 200 R 50 50 1 1 O
+X Q5 6 -500 -150 200 R 50 50 1 1 O
+X Q6 7 -500 -250 200 R 50 50 1 1 O
+X Vss 8 -500 -350 200 R 50 50 1 1 I
+X Q8 9 500 -350 200 L 50 50 1 1 O
+X A0 10 500 -250 200 L 50 50 1 1 I
+X A3 11 500 -150 200 L 50 50 1 1 I
+X A2 12 500 -50 200 L 50 50 1 1 I
+X A1 13 500 50 200 L 50 50 1 1 I
+X Q1 14 500 150 200 L 50 50 1 1 O
+X Q3 15 500 250 200 L 50 50 1 1 O
+X Vdd 16 500 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir new file mode 100644 index 00000000..66fe8e03 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim-Workspace\4028_test\4028_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 16:27:32
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U11-Pad5_ Net-_U11-Pad3_ Net-_U11-Pad1_ Net-_U11-Pad8_ Net-_U12-Pad2_ Net-_U11-Pad6_ Net-_U11-Pad7_ ? Net-_U12-Pad1_ Net-_U13-Pad5_ Net-_U13-Pad8_ Net-_U13-Pad7_ Net-_U13-Pad6_ Net-_U11-Pad2_ Net-_U11-Pad4_ ? 4028
+U13 a0 a1 a2 a3 Net-_U13-Pad5_ Net-_U13-Pad6_ Net-_U13-Pad7_ Net-_U13-Pad8_ adc_bridge_4
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ q0 q1 q2 q3 q4 q5 q6 q7 dac_bridge_8
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ q8 q9 dac_bridge_2
+v2 a1 GND DC
+v1 a0 GND DC
+v3 a2 GND DC
+v4 a3 GND DC
+U2 q1 plot_v1
+U3 q2 plot_v1
+U4 q3 plot_v1
+U5 q4 plot_v1
+U6 q5 plot_v1
+U7 q6 plot_v1
+U8 q7 plot_v1
+U9 q8 plot_v1
+U10 q9 plot_v1
+U1 q0 plot_v1
+U16 a1 plot_v1
+U15 a0 plot_v1
+U14 a3 plot_v1
+U17 a2 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out new file mode 100644 index 00000000..30ea7914 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out @@ -0,0 +1,57 @@ +* c:\users\malli\esim-workspace\4028_test\4028_test.cir
+
+.include 4028.sub
+x1 net-_u11-pad5_ net-_u11-pad3_ net-_u11-pad1_ net-_u11-pad8_ net-_u12-pad2_ net-_u11-pad6_ net-_u11-pad7_ ? net-_u12-pad1_ net-_u13-pad5_ net-_u13-pad8_ net-_u13-pad7_ net-_u13-pad6_ net-_u11-pad2_ net-_u11-pad4_ ? 4028
+* u13 a0 a1 a2 a3 net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ adc_bridge_4
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ q0 q1 q2 q3 q4 q5 q6 q7 dac_bridge_8
+* u12 net-_u12-pad1_ net-_u12-pad2_ q8 q9 dac_bridge_2
+v2 a1 gnd dc 0
+v1 a0 gnd dc 5
+v3 a2 gnd dc 5
+v4 a3 gnd dc 0
+* u2 q1 plot_v1
+* u3 q2 plot_v1
+* u4 q3 plot_v1
+* u5 q4 plot_v1
+* u6 q5 plot_v1
+* u7 q6 plot_v1
+* u8 q7 plot_v1
+* u9 q8 plot_v1
+* u10 q9 plot_v1
+* u1 q0 plot_v1
+* u16 a1 plot_v1
+* u15 a0 plot_v1
+* u14 a3 plot_v1
+* u17 a2 plot_v1
+a1 [a0 a1 a2 a3 ] [net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ ] u13
+a2 [net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ ] [q0 q1 q2 q3 q4 q5 q6 q7 ] u11
+a3 [net-_u12-pad1_ net-_u12-pad2_ ] [q8 q9 ] u12
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u13 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u12 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(q1)
+plot v(q2)
+plot v(q3)
+plot v(q4)
+plot v(q5)
+plot v(q6)
+plot v(q7)
+plot v(q8)
+plot v(q9)
+plot v(q0)
+plot v(a1)
+plot v(a0)
+plot v(a3)
+plot v(a2)
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro new file mode 100644 index 00000000..dc708582 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro @@ -0,0 +1,44 @@ +update=06/01/19 16:07:13
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.proj b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.proj new file mode 100644 index 00000000..fa2ce0cd --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.proj @@ -0,0 +1 @@ +schematicFile 4028_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch new file mode 100644 index 00000000..53226145 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch @@ -0,0 +1,551 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4028 X1
+U 1 1 5CF25569
+P 5600 4300
+F 0 "X1" H 5600 4200 60 0000 C CNN
+F 1 "4028" H 5600 4350 60 0000 C CNN
+F 2 "" H 5600 4300 60 0000 C CNN
+F 3 "" H 5600 4300 60 0000 C CNN
+ 1 5600 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_4 U13
+U 1 1 5CF25781
+P 7300 4350
+F 0 "U13" H 7300 4350 60 0000 C CNN
+F 1 "adc_bridge_4" H 7300 4650 60 0000 C CNN
+F 2 "" H 7300 4350 60 0000 C CNN
+F 3 "" H 7300 4350 60 0000 C CNN
+ 1 7300 4350
+ -1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_8 U11
+U 1 1 5CF257F0
+P 3750 3950
+F 0 "U11" H 3750 3950 60 0000 C CNN
+F 1 "dac_bridge_8" H 3750 4100 60 0000 C CNN
+F 2 "" H 3750 3950 60 0000 C CNN
+F 3 "" H 3750 3950 60 0000 C CNN
+ 1 3750 3950
+ -1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_2 U12
+U 1 1 5CF258CD
+P 3800 5050
+F 0 "U12" H 3800 5050 60 0000 C CNN
+F 1 "dac_bridge_2" H 3850 5200 60 0000 C CNN
+F 2 "" H 3800 5050 60 0000 C CNN
+F 3 "" H 3800 5050 60 0000 C CNN
+ 1 3800 5050
+ -1 0 0 -1
+$EndComp
+$Comp
+L DC v2
+U 1 1 5CF25946
+P 9400 3950
+F 0 "v2" H 9200 4050 60 0000 C CNN
+F 1 "DC" H 9200 3900 60 0000 C CNN
+F 2 "R1" H 9100 3950 60 0000 C CNN
+F 3 "" H 9400 3950 60 0000 C CNN
+ 1 9400 3950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v1
+U 1 1 5CF259A4
+P 9400 3400
+F 0 "v1" H 9200 3500 60 0000 C CNN
+F 1 "DC" H 9200 3350 60 0000 C CNN
+F 2 "R1" H 9100 3400 60 0000 C CNN
+F 3 "" H 9400 3400 60 0000 C CNN
+ 1 9400 3400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v3
+U 1 1 5CF259F8
+P 9400 4500
+F 0 "v3" H 9200 4600 60 0000 C CNN
+F 1 "DC" H 9200 4450 60 0000 C CNN
+F 2 "R1" H 9100 4500 60 0000 C CNN
+F 3 "" H 9400 4500 60 0000 C CNN
+ 1 9400 4500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v4
+U 1 1 5CF25A37
+P 9450 5000
+F 0 "v4" H 9250 5100 60 0000 C CNN
+F 1 "DC" H 9250 4950 60 0000 C CNN
+F 2 "R1" H 9150 5000 60 0000 C CNN
+F 3 "" H 9450 5000 60 0000 C CNN
+ 1 9450 5000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 5CF25C11
+P 10200 4450
+F 0 "#PWR01" H 10200 4200 50 0001 C CNN
+F 1 "eSim_GND" H 10200 4300 50 0000 C CNN
+F 2 "" H 10200 4450 50 0001 C CNN
+F 3 "" H 10200 4450 50 0001 C CNN
+ 1 10200 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 5CF25C75
+P 10200 4100
+F 0 "#FLG02" H 10200 4195 50 0001 C CNN
+F 1 "PWR_FLAG" H 10200 4280 50 0000 C CNN
+F 2 "" H 10200 4100 50 0000 C CNN
+F 3 "" H 10200 4100 50 0000 C CNN
+ 1 10200 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8950 3400 8500 3400
+Wire Wire Line
+ 8500 3400 8500 4150
+Wire Wire Line
+ 8500 4150 7850 4150
+Wire Wire Line
+ 8600 4250 7850 4250
+Wire Wire Line
+ 8600 3050 8600 4250
+Wire Wire Line
+ 8600 3950 8950 3950
+Wire Wire Line
+ 8950 4500 8500 4500
+Wire Wire Line
+ 8500 4500 8500 4350
+Wire Wire Line
+ 8500 4350 7850 4350
+Wire Wire Line
+ 7850 4450 8200 4450
+Wire Wire Line
+ 8200 4450 8200 5000
+Wire Wire Line
+ 8200 5000 9000 5000
+Wire Wire Line
+ 9900 3400 9900 5000
+Wire Wire Line
+ 9900 3400 9850 3400
+Wire Wire Line
+ 9850 3950 9900 3950
+Connection ~ 9900 3950
+Wire Wire Line
+ 9850 4500 9900 4500
+Connection ~ 9900 4500
+Wire Wire Line
+ 9900 4200 10200 4200
+Wire Wire Line
+ 10200 4100 10200 4450
+Connection ~ 9900 4200
+Connection ~ 10200 4200
+Wire Wire Line
+ 5100 4150 4750 4150
+Wire Wire Line
+ 4750 4150 4750 3900
+Wire Wire Line
+ 4750 3900 4350 3900
+Wire Wire Line
+ 6100 4150 6200 4150
+Wire Wire Line
+ 6200 4150 6200 3700
+Wire Wire Line
+ 6200 3700 4400 3700
+Wire Wire Line
+ 4400 3700 4400 4000
+Wire Wire Line
+ 4400 4000 4350 4000
+Wire Wire Line
+ 4350 4050 5100 4050
+Wire Wire Line
+ 4350 4050 4350 4100
+Wire Wire Line
+ 6100 4050 6250 4050
+Wire Wire Line
+ 6250 4050 6250 3650
+Wire Wire Line
+ 6250 3650 4450 3650
+Wire Wire Line
+ 4450 3650 4450 4200
+Wire Wire Line
+ 4450 4200 4350 4200
+Wire Wire Line
+ 5100 3950 4500 3950
+Wire Wire Line
+ 4500 3950 4500 4300
+Wire Wire Line
+ 4500 4300 4350 4300
+Wire Wire Line
+ 5100 4450 4500 4450
+Wire Wire Line
+ 4500 4450 4500 4400
+Wire Wire Line
+ 4500 4400 4350 4400
+Wire Wire Line
+ 5100 4550 4450 4550
+Wire Wire Line
+ 4450 4550 4450 4500
+Wire Wire Line
+ 4450 4500 4350 4500
+Wire Wire Line
+ 4550 4250 5100 4250
+Wire Wire Line
+ 4550 4250 4550 4600
+Wire Wire Line
+ 4550 4600 4350 4600
+Wire Wire Line
+ 6100 4650 6150 4650
+Wire Wire Line
+ 6150 4650 6150 5000
+Wire Wire Line
+ 6150 5000 4250 5000
+Wire Wire Line
+ 4250 5100 4650 5100
+Wire Wire Line
+ 4650 5100 4650 4350
+Wire Wire Line
+ 4650 4350 5100 4350
+Wire Wire Line
+ 6100 4550 6350 4550
+Wire Wire Line
+ 6350 4550 6350 4150
+Wire Wire Line
+ 6350 4150 6750 4150
+Wire Wire Line
+ 6100 4250 6750 4250
+Wire Wire Line
+ 6100 4350 6750 4350
+Wire Wire Line
+ 6750 4450 6100 4450
+$Comp
+L plot_v1 U2
+U 1 1 5CF261D1
+P 1700 2550
+F 0 "U2" H 1700 3050 60 0000 C CNN
+F 1 "plot_v1" H 1900 2900 60 0000 C CNN
+F 2 "" H 1700 2550 60 0000 C CNN
+F 3 "" H 1700 2550 60 0000 C CNN
+ 1 1700 2550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U3
+U 1 1 5CF262A9
+P 1700 3050
+F 0 "U3" H 1700 3550 60 0000 C CNN
+F 1 "plot_v1" H 1900 3400 60 0000 C CNN
+F 2 "" H 1700 3050 60 0000 C CNN
+F 3 "" H 1700 3050 60 0000 C CNN
+ 1 1700 3050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 5CF262EF
+P 1700 3450
+F 0 "U4" H 1700 3950 60 0000 C CNN
+F 1 "plot_v1" H 1900 3800 60 0000 C CNN
+F 2 "" H 1700 3450 60 0000 C CNN
+F 3 "" H 1700 3450 60 0000 C CNN
+ 1 1700 3450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 5CF2632C
+P 1700 3850
+F 0 "U5" H 1700 4350 60 0000 C CNN
+F 1 "plot_v1" H 1900 4200 60 0000 C CNN
+F 2 "" H 1700 3850 60 0000 C CNN
+F 3 "" H 1700 3850 60 0000 C CNN
+ 1 1700 3850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 5CF26370
+P 1700 4250
+F 0 "U6" H 1700 4750 60 0000 C CNN
+F 1 "plot_v1" H 1900 4600 60 0000 C CNN
+F 2 "" H 1700 4250 60 0000 C CNN
+F 3 "" H 1700 4250 60 0000 C CNN
+ 1 1700 4250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U7
+U 1 1 5CF263B7
+P 1700 4650
+F 0 "U7" H 1700 5150 60 0000 C CNN
+F 1 "plot_v1" H 1900 5000 60 0000 C CNN
+F 2 "" H 1700 4650 60 0000 C CNN
+F 3 "" H 1700 4650 60 0000 C CNN
+ 1 1700 4650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U8
+U 1 1 5CF263FD
+P 1700 5050
+F 0 "U8" H 1700 5550 60 0000 C CNN
+F 1 "plot_v1" H 1900 5400 60 0000 C CNN
+F 2 "" H 1700 5050 60 0000 C CNN
+F 3 "" H 1700 5050 60 0000 C CNN
+ 1 1700 5050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U9
+U 1 1 5CF26446
+P 1700 5500
+F 0 "U9" H 1700 6000 60 0000 C CNN
+F 1 "plot_v1" H 1900 5850 60 0000 C CNN
+F 2 "" H 1700 5500 60 0000 C CNN
+F 3 "" H 1700 5500 60 0000 C CNN
+ 1 1700 5500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U10
+U 1 1 5CF2649A
+P 1700 5900
+F 0 "U10" H 1700 6400 60 0000 C CNN
+F 1 "plot_v1" H 1900 6250 60 0000 C CNN
+F 2 "" H 1700 5900 60 0000 C CNN
+F 3 "" H 1700 5900 60 0000 C CNN
+ 1 1700 5900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 5CF26545
+P 1700 2100
+F 0 "U1" H 1700 2600 60 0000 C CNN
+F 1 "plot_v1" H 1900 2450 60 0000 C CNN
+F 2 "" H 1700 2100 60 0000 C CNN
+F 3 "" H 1700 2100 60 0000 C CNN
+ 1 1700 2100
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 3200 3900 2900 3900
+Wire Wire Line
+ 2900 3900 2900 2100
+Wire Wire Line
+ 2900 2100 1500 2100
+Wire Wire Line
+ 1500 2550 2850 2550
+Wire Wire Line
+ 2850 2550 2850 4000
+Wire Wire Line
+ 2850 4000 3200 4000
+Wire Wire Line
+ 3200 4100 2700 4100
+Wire Wire Line
+ 2700 4100 2700 3050
+Wire Wire Line
+ 2700 3050 1500 3050
+Wire Wire Line
+ 1500 3450 2650 3450
+Wire Wire Line
+ 2650 3450 2650 4200
+Wire Wire Line
+ 2650 4200 3200 4200
+Wire Wire Line
+ 3200 4300 2600 4300
+Wire Wire Line
+ 2600 4300 2600 3850
+Wire Wire Line
+ 2600 3850 1500 3850
+Wire Wire Line
+ 1500 4250 2550 4250
+Wire Wire Line
+ 2550 4250 2550 4400
+Wire Wire Line
+ 2550 4400 3200 4400
+Wire Wire Line
+ 2450 4500 3200 4500
+Wire Wire Line
+ 2450 4500 2450 4650
+Wire Wire Line
+ 2450 4650 1500 4650
+Wire Wire Line
+ 1500 5050 2600 5050
+Wire Wire Line
+ 2600 5050 2600 4600
+Wire Wire Line
+ 2600 4600 3200 4600
+Wire Wire Line
+ 3250 5000 2650 5000
+Wire Wire Line
+ 2650 5000 2650 5500
+Wire Wire Line
+ 2650 5500 1500 5500
+Wire Wire Line
+ 3250 5100 2700 5100
+Wire Wire Line
+ 2700 5100 2700 5900
+Wire Wire Line
+ 2700 5900 1500 5900
+$Comp
+L plot_v1 U16
+U 1 1 5CF26B3C
+P 8600 3250
+F 0 "U16" H 8600 3750 60 0000 C CNN
+F 1 "plot_v1" H 8800 3600 60 0000 C CNN
+F 2 "" H 8600 3250 60 0000 C CNN
+F 3 "" H 8600 3250 60 0000 C CNN
+ 1 8600 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U15
+U 1 1 5CF26C0A
+P 8250 3750
+F 0 "U15" H 8250 4250 60 0000 C CNN
+F 1 "plot_v1" H 8450 4100 60 0000 C CNN
+F 2 "" H 8250 3750 60 0000 C CNN
+F 3 "" H 8250 3750 60 0000 C CNN
+ 1 8250 3750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U14
+U 1 1 5CF26C90
+P 8150 4900
+F 0 "U14" H 8150 5400 60 0000 C CNN
+F 1 "plot_v1" H 8350 5250 60 0000 C CNN
+F 2 "" H 8150 4900 60 0000 C CNN
+F 3 "" H 8150 4900 60 0000 C CNN
+ 1 8150 4900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U17
+U 1 1 5CF26D07
+P 8750 5150
+F 0 "U17" H 8750 5650 60 0000 C CNN
+F 1 "plot_v1" H 8950 5500 60 0000 C CNN
+F 2 "" H 8750 5150 60 0000 C CNN
+F 3 "" H 8750 5150 60 0000 C CNN
+ 1 8750 5150
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 8750 5350 8750 4500
+Connection ~ 8750 4500
+Wire Wire Line
+ 7950 4900 8200 4900
+Connection ~ 8200 4900
+Wire Wire Line
+ 8050 3750 8500 3750
+Connection ~ 8500 3750
+Connection ~ 8600 3950
+Text GLabel 8450 3250 0 60 Input ~ 0
+a1
+Text GLabel 8250 3850 3 60 Input ~ 0
+a0
+Text GLabel 8600 4750 0 60 Input ~ 0
+a2
+Text GLabel 8050 5050 3 60 Input ~ 0
+a3
+Wire Wire Line
+ 8050 5050 8050 4900
+Connection ~ 8050 4900
+Wire Wire Line
+ 8600 4750 8750 4750
+Connection ~ 8750 4750
+Wire Wire Line
+ 8250 3850 8250 3750
+Connection ~ 8250 3750
+Wire Wire Line
+ 8450 3250 8600 3250
+Connection ~ 8600 3250
+NoConn ~ 6100 3950
+NoConn ~ 5100 4650
+Text GLabel 2000 1950 1 60 Output ~ 0
+q0
+Text GLabel 2000 2450 1 60 Output ~ 0
+q1
+Text GLabel 1900 2900 1 60 Output ~ 0
+q2
+Text GLabel 1850 3350 1 60 Output ~ 0
+q3
+Text GLabel 1850 3750 1 60 Output ~ 0
+q4
+Text GLabel 1850 4150 1 60 Output ~ 0
+q5
+Text GLabel 1800 4550 1 60 Output ~ 0
+q6
+Text GLabel 1800 4950 1 60 Output ~ 0
+q7
+Text GLabel 1800 5400 1 60 Output ~ 0
+q8
+Text GLabel 1800 5800 1 60 Output ~ 0
+q9
+Wire Wire Line
+ 1800 5800 1800 5900
+Connection ~ 1800 5900
+Wire Wire Line
+ 1800 5400 1800 5500
+Connection ~ 1800 5500
+Wire Wire Line
+ 1800 4950 1800 5050
+Connection ~ 1800 5050
+Wire Wire Line
+ 1800 4550 1800 4650
+Connection ~ 1800 4650
+Wire Wire Line
+ 1850 4150 1850 4250
+Connection ~ 1850 4250
+Wire Wire Line
+ 1850 3750 1850 3850
+Connection ~ 1850 3850
+Wire Wire Line
+ 1850 3350 1850 3450
+Connection ~ 1850 3450
+Wire Wire Line
+ 1900 2900 1900 3050
+Connection ~ 1900 3050
+Wire Wire Line
+ 2000 2450 2000 2550
+Connection ~ 2000 2550
+Wire Wire Line
+ 2000 1950 2000 2100
+Connection ~ 2000 2100
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test_Previous_Values.xml new file mode 100644 index 00000000..4156779d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4></source><model><u13 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u13><u11 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u11><u12 name="type">dac_bridge<field11 name="Enter value for input load (default=1.0e-12)" /><field12 name="Enter value for out_low (default=0.0)" /><field13 name="Enter value for out_high (default=5.0)" /><field14 name="Enter the Rise Time (default=1.0e-9)" /><field15 name="Enter the Fall Time (default=1.0e-9)" /><field16 name="Enter value for out_undef (default=0.5)" /></u12></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4028</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/analysis b/Examples/Analysis_Of_Digital_IC/4028_test/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro new file mode 100644 index 00000000..0fdf4d25 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro @@ -0,0 +1,44 @@ +update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_PSpice
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib new file mode 100644 index 00000000..e316d596 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir new file mode 100644 index 00000000..7afe79fe --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and
+X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out new file mode 100644 index 00000000..d22d0923 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out @@ -0,0 +1,16 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
+x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro new file mode 100644 index 00000000..7ed8e96e --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro @@ -0,0 +1,43 @@ +update=05/31/19 16:37:06
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch new file mode 100644 index 00000000..ff6d873a --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch @@ -0,0 +1,263 @@ +EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X1
+U 1 1 5CF10AEA
+P 4550 2650
+F 0 "X1" H 4650 2600 60 0000 C CNN
+F 1 "3_and" H 4700 2800 60 0000 C CNN
+F 2 "" H 4550 2650 60 0000 C CNN
+F 3 "" H 4550 2650 60 0000 C CNN
+ 1 4550 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CF10B72
+P 3100 2200
+F 0 "U1" H 3150 2300 30 0000 C CNN
+F 1 "PORT" H 3100 2200 30 0000 C CNN
+F 2 "" H 3100 2200 60 0000 C CNN
+F 3 "" H 3100 2200 60 0000 C CNN
+ 1 3100 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CF10BC9
+P 3100 2500
+F 0 "U1" H 3150 2600 30 0000 C CNN
+F 1 "PORT" H 3100 2500 30 0000 C CNN
+F 2 "" H 3100 2500 60 0000 C CNN
+F 3 "" H 3100 2500 60 0000 C CNN
+ 2 3100 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CF10BEA
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 8 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CF10C10
+P 6200 2600
+F 0 "U1" H 6250 2700 30 0000 C CNN
+F 1 "PORT" H 6200 2600 30 0000 C CNN
+F 2 "" H 6200 2600 60 0000 C CNN
+F 3 "" H 6200 2600 60 0000 C CNN
+ 9 6200 2600
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 5950 2600 5050 2600
+Wire Wire Line
+ 4200 2500 4200 2200
+Wire Wire Line
+ 4200 2200 3350 2200
+Wire Wire Line
+ 3350 2500 3850 2500
+Wire Wire Line
+ 3850 2500 3850 2600
+Wire Wire Line
+ 3850 2600 4200 2600
+Wire Wire Line
+ 4200 2700 4200 2850
+Wire Wire Line
+ 4200 2850 3350 2850
+$Comp
+L 3_and X3
+U 1 1 5CF10DE5
+P 4600 4100
+F 0 "X3" H 4700 4050 60 0000 C CNN
+F 1 "3_and" H 4750 4250 60 0000 C CNN
+F 2 "" H 4600 4100 60 0000 C CNN
+F 3 "" H 4600 4100 60 0000 C CNN
+ 1 4600 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CF10DEB
+P 3150 3650
+F 0 "U1" H 3200 3750 30 0000 C CNN
+F 1 "PORT" H 3150 3650 30 0000 C CNN
+F 2 "" H 3150 3650 60 0000 C CNN
+F 3 "" H 3150 3650 60 0000 C CNN
+ 3 3150 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CF10DF1
+P 3150 3950
+F 0 "U1" H 3200 4050 30 0000 C CNN
+F 1 "PORT" H 3150 3950 30 0000 C CNN
+F 2 "" H 3150 3950 60 0000 C CNN
+F 3 "" H 3150 3950 60 0000 C CNN
+ 4 3150 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CF10DF7
+P 3150 4300
+F 0 "U1" H 3200 4400 30 0000 C CNN
+F 1 "PORT" H 3150 4300 30 0000 C CNN
+F 2 "" H 3150 4300 60 0000 C CNN
+F 3 "" H 3150 4300 60 0000 C CNN
+ 5 3150 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CF10DFD
+P 6250 4050
+F 0 "U1" H 6300 4150 30 0000 C CNN
+F 1 "PORT" H 6250 4050 30 0000 C CNN
+F 2 "" H 6250 4050 60 0000 C CNN
+F 3 "" H 6250 4050 60 0000 C CNN
+ 6 6250 4050
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 6000 4050 5100 4050
+Wire Wire Line
+ 4250 3950 4250 3650
+Wire Wire Line
+ 4250 3650 3400 3650
+Wire Wire Line
+ 3400 3950 3900 3950
+Wire Wire Line
+ 3900 3950 3900 4050
+Wire Wire Line
+ 3900 4050 4250 4050
+Wire Wire Line
+ 4250 4150 4250 4300
+Wire Wire Line
+ 4250 4300 3400 4300
+$Comp
+L 3_and X2
+U 1 1 5CF10E9C
+P 4550 5450
+F 0 "X2" H 4650 5400 60 0000 C CNN
+F 1 "3_and" H 4700 5600 60 0000 C CNN
+F 2 "" H 4550 5450 60 0000 C CNN
+F 3 "" H 4550 5450 60 0000 C CNN
+ 1 4550 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CF10EA2
+P 3100 5000
+F 0 "U1" H 3150 5100 30 0000 C CNN
+F 1 "PORT" H 3100 5000 30 0000 C CNN
+F 2 "" H 3100 5000 60 0000 C CNN
+F 3 "" H 3100 5000 60 0000 C CNN
+ 11 3100 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CF10EA8
+P 3100 5300
+F 0 "U1" H 3150 5400 30 0000 C CNN
+F 1 "PORT" H 3100 5300 30 0000 C CNN
+F 2 "" H 3100 5300 60 0000 C CNN
+F 3 "" H 3100 5300 60 0000 C CNN
+ 12 3100 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CF10EAE
+P 3100 5650
+F 0 "U1" H 3150 5750 30 0000 C CNN
+F 1 "PORT" H 3100 5650 30 0000 C CNN
+F 2 "" H 3100 5650 60 0000 C CNN
+F 3 "" H 3100 5650 60 0000 C CNN
+ 13 3100 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CF10EB4
+P 6200 5400
+F 0 "U1" H 6250 5500 30 0000 C CNN
+F 1 "PORT" H 6200 5400 30 0000 C CNN
+F 2 "" H 6200 5400 60 0000 C CNN
+F 3 "" H 6200 5400 60 0000 C CNN
+ 10 6200 5400
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 5950 5400 5050 5400
+Wire Wire Line
+ 4200 5300 4200 5000
+Wire Wire Line
+ 4200 5000 3350 5000
+Wire Wire Line
+ 3350 5300 3850 5300
+Wire Wire Line
+ 3850 5300 3850 5400
+Wire Wire Line
+ 3850 5400 4200 5400
+Wire Wire Line
+ 4200 5500 4200 5650
+Wire Wire Line
+ 4200 5650 3350 5650
+$Comp
+L PORT U1
+U 7 1 5CF11A2A
+P 7500 4100
+F 0 "U1" H 7550 4200 30 0000 C CNN
+F 1 "PORT" H 7500 4100 30 0000 C CNN
+F 2 "" H 7500 4100 60 0000 C CNN
+F 3 "" H 7500 4100 60 0000 C CNN
+ 7 7500 4100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CF11A8A
+P 7550 4600
+F 0 "U1" H 7600 4700 30 0000 C CNN
+F 1 "PORT" H 7550 4600 30 0000 C CNN
+F 2 "" H 7550 4600 60 0000 C CNN
+F 3 "" H 7550 4600 60 0000 C CNN
+ 14 7550 4600
+ -1 0 0 1
+$EndComp
+NoConn ~ 7250 4100
+NoConn ~ 7300 4600
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub new file mode 100644 index 00000000..b10679cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub @@ -0,0 +1,10 @@ +* Subcircuit 4073
+.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
+x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
+x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
+* Control Statements
+
+.ends 4073
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml new file mode 100644 index 00000000..5acac768 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test-cache.lib new file mode 100644 index 00000000..ed355f9a --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test-cache.lib @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4073 +# +DEF 4073 x 0 40 Y Y 1 F N +F0 "x" 0 -100 60 H V C CNN +F1 "4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# DC-RESCUE-4073_test +# +DEF DC-RESCUE-4073_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4073_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_3 +# +DEF dac_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test-rescue.lib new file mode 100644 index 00000000..8c3e2f6f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test-rescue.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-4073_test +# +DEF DC-RESCUE-4073_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4073_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.cir b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.cir new file mode 100644 index 00000000..e4628b32 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.cir @@ -0,0 +1,36 @@ +* C:\Users\malli\eSim-Workspace\4073_test\4073_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 15:55:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+x1 Net-_U7-Pad4_ Net-_U7-Pad5_ Net-_U8-Pad4_ Net-_U8-Pad5_ Net-_U8-Pad6_ Net-_U9-Pad2_ ? Net-_U7-Pad6_ Net-_U9-Pad1_ Net-_U9-Pad3_ Net-_U10-Pad6_ Net-_U10-Pad5_ Net-_U10-Pad4_ ? 4073
+U8 a2 b2 c2 Net-_U8-Pad4_ Net-_U8-Pad5_ Net-_U8-Pad6_ adc_bridge_3
+U7 a1 b1 c1 Net-_U7-Pad4_ Net-_U7-Pad5_ Net-_U7-Pad6_ adc_bridge_3
+U10 a3 b3 c3 Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U10-Pad6_ adc_bridge_3
+U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U9-Pad3_ q1 q2 q3 dac_bridge_3
+v1 a1 GND DC
+v2 b1 GND DC
+v3 c1 GND DC
+v4 a2 GND DC
+v5 b2 GND DC
+v6 c2 GND DC
+v7 a3 GND DC
+v8 b3 GND DC
+v9 c3 GND DC
+U16 b3 plot_v1
+U12 a3 plot_v1
+U14 c3 plot_v1
+U2 b2 plot_v1
+U5 c2 plot_v1
+U4 a2 plot_v1
+U3 c1 plot_v1
+U6 a1 plot_v1
+U1 b1 plot_v1
+U13 q3 plot_v1
+U15 q2 plot_v1
+U11 q1 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.cir.out b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.cir.out new file mode 100644 index 00000000..e9673cd7 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.cir.out @@ -0,0 +1,62 @@ +* c:\users\malli\esim-workspace\4073_test\4073_test.cir
+
+.include 4073.sub
+x1 net-_u7-pad4_ net-_u7-pad5_ net-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ net-_u9-pad2_ ? net-_u7-pad6_ net-_u9-pad1_ net-_u9-pad3_ net-_u10-pad6_ net-_u10-pad5_ net-_u10-pad4_ ? 4073
+* u8 a2 b2 c2 net-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ adc_bridge_3
+* u7 a1 b1 c1 net-_u7-pad4_ net-_u7-pad5_ net-_u7-pad6_ adc_bridge_3
+* u10 a3 b3 c3 net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ adc_bridge_3
+* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ q1 q2 q3 dac_bridge_3
+v1 a1 gnd dc 5
+v2 b1 gnd dc 5
+v3 c1 gnd dc 5
+v4 a2 gnd dc 5
+v5 b2 gnd dc 5
+v6 c2 gnd dc 5
+v7 a3 gnd dc 5
+v8 b3 gnd dc 5
+v9 c3 gnd dc 5
+* u16 b3 plot_v1
+* u12 a3 plot_v1
+* u14 c3 plot_v1
+* u2 b2 plot_v1
+* u5 c2 plot_v1
+* u4 a2 plot_v1
+* u3 c1 plot_v1
+* u6 a1 plot_v1
+* u1 b1 plot_v1
+* u13 q3 plot_v1
+* u15 q2 plot_v1
+* u11 q1 plot_v1
+a1 [a2 b2 c2 ] [net-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ ] u8
+a2 [a1 b1 c1 ] [net-_u7-pad4_ net-_u7-pad5_ net-_u7-pad6_ ] u7
+a3 [a3 b3 c3 ] [net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ ] u10
+a4 [net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ ] [q1 q2 q3 ] u9
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u8 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u7 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u10 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge
+.model u9 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(b3)
+plot v(a3)
+plot v(c3)
+plot v(b2)
+plot v(c2)
+plot v(a2)
+plot v(c1)
+plot v(a1)
+plot v(b1)
+plot v(q3)
+plot v(q2)
+plot v(q1)
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro new file mode 100644 index 00000000..1ff3178b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro @@ -0,0 +1,46 @@ +update=Wed Aug 14 12:44:12 2019 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../eSim/kicadSchematicLibrary +[eeschema/libraries] +LibName1=4073_test-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_PSpice +LibName11=eSim_Sources +LibName12=eSim_Subckt +LibName13=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.proj b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.proj new file mode 100644 index 00000000..fbf62977 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.proj @@ -0,0 +1 @@ +schematicFile 4073_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.sch b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.sch new file mode 100644 index 00000000..554c9a0a --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.sch @@ -0,0 +1,577 @@ +EESchema Schematic File Version 2 +LIBS:4073_test-rescue +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4073_test-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4073 x1 +U 1 1 5CF2518C +P 5300 3900 +F 0 "x1" H 5300 3800 60 0000 C CNN +F 1 "4073" H 5300 3950 60 0000 C CNN +F 2 "" H 5300 3900 60 0000 C CNN +F 3 "" H 5300 3900 60 0000 C CNN + 1 5300 3900 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U8 +U 1 1 5CF2528E +P 3450 4500 +F 0 "U8" H 3450 4500 60 0000 C CNN +F 1 "adc_bridge_3" H 3450 4650 60 0000 C CNN +F 2 "" H 3450 4500 60 0000 C CNN +F 3 "" H 3450 4500 60 0000 C CNN + 1 3450 4500 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U7 +U 1 1 5CF2528F +P 3400 2850 +F 0 "U7" H 3400 2850 60 0000 C CNN +F 1 "adc_bridge_3" H 3400 3000 60 0000 C CNN +F 2 "" H 3400 2850 60 0000 C CNN +F 3 "" H 3400 2850 60 0000 C CNN + 1 3400 2850 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U10 +U 1 1 5CF25290 +P 7000 3750 +F 0 "U10" H 7000 3750 60 0000 C CNN +F 1 "adc_bridge_3" H 7000 3900 60 0000 C CNN +F 2 "" H 7000 3750 60 0000 C CNN +F 3 "" H 7000 3750 60 0000 C CNN + 1 7000 3750 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_3 U9 +U 1 1 5CF25291 +P 6800 5750 +F 0 "U9" H 6800 5750 60 0000 C CNN +F 1 "dac_bridge_3" H 6800 5900 60 0000 C CNN +F 2 "" H 6800 5750 60 0000 C CNN +F 3 "" H 6800 5750 60 0000 C CNN + 1 6800 5750 + 1 0 0 -1 +$EndComp +$Comp +L DC-RESCUE-4073_test v1 +U 1 1 5CF25292 +P 1700 2350 +F 0 "v1" H 1500 2450 60 0000 C CNN +F 1 "DC" H 1500 2300 60 0000 C CNN +F 2 "R1" H 1400 2350 60 0000 C CNN +F 3 "" H 1700 2350 60 0000 C CNN + 1 1700 2350 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4073_test v2 +U 1 1 5CF25293 +P 1700 2900 +F 0 "v2" H 1500 3000 60 0000 C CNN +F 1 "DC" H 1500 2850 60 0000 C CNN +F 2 "R1" H 1400 2900 60 0000 C CNN +F 3 "" H 1700 2900 60 0000 C CNN + 1 1700 2900 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4073_test v3 +U 1 1 5CF25294 +P 1700 3450 +F 0 "v3" H 1500 3550 60 0000 C CNN +F 1 "DC" H 1500 3400 60 0000 C CNN +F 2 "R1" H 1400 3450 60 0000 C CNN +F 3 "" H 1700 3450 60 0000 C CNN + 1 1700 3450 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4073_test v4 +U 1 1 5CF25295 +P 1750 4000 +F 0 "v4" H 1550 4100 60 0000 C CNN +F 1 "DC" H 1550 3950 60 0000 C CNN +F 2 "R1" H 1450 4000 60 0000 C CNN +F 3 "" H 1750 4000 60 0000 C CNN + 1 1750 4000 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4073_test v5 +U 1 1 5CF25296 +P 1750 4550 +F 0 "v5" H 1550 4650 60 0000 C CNN +F 1 "DC" H 1550 4500 60 0000 C CNN +F 2 "R1" H 1450 4550 60 0000 C CNN +F 3 "" H 1750 4550 60 0000 C CNN + 1 1750 4550 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4073_test v6 +U 1 1 5CF25297 +P 1750 5050 +F 0 "v6" H 1550 5150 60 0000 C CNN +F 1 "DC" H 1550 5000 60 0000 C CNN +F 2 "R1" H 1450 5050 60 0000 C CNN +F 3 "" H 1750 5050 60 0000 C CNN + 1 1750 5050 + 0 1 1 0 +$EndComp +Wire Wire Line + 2800 2800 2800 2350 +Wire Wire Line + 2800 2350 2150 2350 +Wire Wire Line + 2150 2900 2800 2900 +Wire Wire Line + 2150 3450 2800 3450 +Wire Wire Line + 2800 3450 2800 3000 +Wire Wire Line + 2200 4000 2850 4000 +Wire Wire Line + 2850 3900 2850 4450 +Wire Wire Line + 2850 4550 2200 4550 +Wire Wire Line + 2200 5050 2850 5050 +Wire Wire Line + 2850 5050 2850 4650 +Wire Wire Line + 900 5050 1300 5050 +Wire Wire Line + 900 2350 900 5050 +Wire Wire Line + 900 2350 1250 2350 +Wire Wire Line + 1250 2900 900 2900 +Connection ~ 900 2900 +Wire Wire Line + 1250 3450 900 3450 +Connection ~ 900 3450 +Wire Wire Line + 1300 4000 900 4000 +Connection ~ 900 4000 +Wire Wire Line + 1300 4550 900 4550 +Connection ~ 900 4550 +Wire Wire Line + 3950 2800 4500 2800 +Wire Wire Line + 4500 2800 4500 3600 +Wire Wire Line + 4500 3600 4800 3600 +Wire Wire Line + 3950 2900 4400 2900 +Wire Wire Line + 4400 2900 4400 3700 +Wire Wire Line + 4400 3700 4800 3700 +Wire Wire Line + 3950 3000 5900 3000 +Wire Wire Line + 5900 3000 5900 4200 +Wire Wire Line + 5900 4200 5800 4200 +Wire Wire Line + 6450 3900 5800 3900 +Wire Wire Line + 5800 3800 6450 3800 +Wire Wire Line + 6450 3700 5800 3700 +Wire Wire Line + 4000 4450 4000 3800 +Wire Wire Line + 4000 3800 4800 3800 +Wire Wire Line + 4800 3900 4100 3900 +Wire Wire Line + 4100 3900 4100 4550 +Wire Wire Line + 4100 4550 4000 4550 +Wire Wire Line + 4000 4650 4200 4650 +Wire Wire Line + 4200 4650 4200 4000 +Wire Wire Line + 4200 4000 4800 4000 +Wire Wire Line + 4800 4100 4450 4100 +Wire Wire Line + 4450 4100 4450 5800 +Wire Wire Line + 4450 5800 6200 5800 +Wire Wire Line + 5800 4100 5850 4100 +Wire Wire Line + 5850 4100 5850 5700 +Wire Wire Line + 5850 5700 6200 5700 +Wire Wire Line + 5800 4000 5950 4000 +Wire Wire Line + 5950 4000 5950 5900 +Wire Wire Line + 5950 5900 6200 5900 +$Comp +L DC-RESCUE-4073_test v7 +U 1 1 5CF25298 +P 9250 3250 +F 0 "v7" H 9050 3350 60 0000 C CNN +F 1 "DC" H 9050 3200 60 0000 C CNN +F 2 "R1" H 8950 3250 60 0000 C CNN +F 3 "" H 9250 3250 60 0000 C CNN + 1 9250 3250 + 0 -1 1 0 +$EndComp +$Comp +L DC-RESCUE-4073_test v8 +U 1 1 5CF25299 +P 9250 3800 +F 0 "v8" H 9050 3900 60 0000 C CNN +F 1 "DC" H 9050 3750 60 0000 C CNN +F 2 "R1" H 8950 3800 60 0000 C CNN +F 3 "" H 9250 3800 60 0000 C CNN + 1 9250 3800 + 0 -1 1 0 +$EndComp +$Comp +L DC-RESCUE-4073_test v9 +U 1 1 5CF2529A +P 9250 4300 +F 0 "v9" H 9050 4400 60 0000 C CNN +F 1 "DC" H 9050 4250 60 0000 C CNN +F 2 "R1" H 8950 4300 60 0000 C CNN +F 3 "" H 9250 4300 60 0000 C CNN + 1 9250 4300 + 0 -1 1 0 +$EndComp +Wire Wire Line + 7600 3250 8800 3250 +Wire Wire Line + 7600 3800 8800 3800 +Wire Wire Line + 7600 4300 8800 4300 +Wire Wire Line + 10150 4300 9700 4300 +Wire Wire Line + 9700 3250 10150 3250 +Wire Wire Line + 9700 3800 10500 3800 +Wire Wire Line + 7600 3250 7600 3700 +Wire Wire Line + 7600 4300 7600 3900 +Wire Wire Line + 10150 3250 10150 4300 +Connection ~ 10150 3800 +Wire Wire Line + 10500 3800 10500 4050 +NoConn ~ 5800 3600 +NoConn ~ 4800 4200 +$Comp +L plot_v1 U16 +U 1 1 5CF2529B +P 8450 3050 +F 0 "U16" H 8450 3550 60 0000 C CNN +F 1 "plot_v1" H 8650 3400 60 0000 C CNN +F 2 "" H 8450 3050 60 0000 C CNN +F 3 "" H 8450 3050 60 0000 C CNN + 1 8450 3050 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 5CF2529C +P 7750 3100 +F 0 "U12" H 7750 3600 60 0000 C CNN +F 1 "plot_v1" H 7950 3450 60 0000 C CNN +F 2 "" H 7750 3100 60 0000 C CNN +F 3 "" H 7750 3100 60 0000 C CNN + 1 7750 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U14 +U 1 1 5CF2529D +P 8050 4300 +F 0 "U14" H 8050 4800 60 0000 C CNN +F 1 "plot_v1" H 8250 4650 60 0000 C CNN +F 2 "" H 8050 4300 60 0000 C CNN +F 3 "" H 8050 4300 60 0000 C CNN + 1 8050 4300 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 5CF2529E +P 2450 5100 +F 0 "U2" H 2450 5600 60 0000 C CNN +F 1 "plot_v1" H 2650 5450 60 0000 C CNN +F 2 "" H 2450 5100 60 0000 C CNN +F 3 "" H 2450 5100 60 0000 C CNN + 1 2450 5100 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5CF2529F +P 3000 5000 +F 0 "U5" H 3000 5500 60 0000 C CNN +F 1 "plot_v1" H 3200 5350 60 0000 C CNN +F 2 "" H 3000 5000 60 0000 C CNN +F 3 "" H 3000 5000 60 0000 C CNN + 1 3000 5000 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5CF252A0 +P 2950 3900 +F 0 "U4" H 2950 4400 60 0000 C CNN +F 1 "plot_v1" H 3150 4250 60 0000 C CNN +F 2 "" H 2950 3900 60 0000 C CNN +F 3 "" H 2950 3900 60 0000 C CNN + 1 2950 3900 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5CF252A1 +P 2850 3250 +F 0 "U3" H 2850 3750 60 0000 C CNN +F 1 "plot_v1" H 3050 3600 60 0000 C CNN +F 2 "" H 2850 3250 60 0000 C CNN +F 3 "" H 2850 3250 60 0000 C CNN + 1 2850 3250 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5CF252A2 +P 3100 2400 +F 0 "U6" H 3100 2900 60 0000 C CNN +F 1 "plot_v1" H 3300 2750 60 0000 C CNN +F 2 "" H 3100 2400 60 0000 C CNN +F 3 "" H 3100 2400 60 0000 C CNN + 1 3100 2400 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 5CF252A3 +P 2400 2300 +F 0 "U1" H 2400 2800 60 0000 C CNN +F 1 "plot_v1" H 2600 2650 60 0000 C CNN +F 2 "" H 2400 2300 60 0000 C CNN +F 3 "" H 2400 2300 60 0000 C CNN + 1 2400 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 5CF252A4 +P 700 3900 +F 0 "#PWR01" H 700 3650 50 0001 C CNN +F 1 "eSim_GND" H 700 3750 50 0000 C CNN +F 2 "" H 700 3900 50 0001 C CNN +F 3 "" H 700 3900 50 0001 C CNN + 1 700 3900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5CF252A5 +P 700 3700 +F 0 "#FLG02" H 700 3795 50 0001 C CNN +F 1 "PWR_FLAG" H 700 3880 50 0000 C CNN +F 2 "" H 700 3700 50 0000 C CNN +F 3 "" H 700 3700 50 0000 C CNN + 1 700 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 700 3700 700 3900 +Wire Wire Line + 700 3800 900 3800 +Connection ~ 900 3800 +Connection ~ 700 3800 +Wire Wire Line + 3100 2200 3100 2450 +Wire Wire Line + 3100 2450 2800 2450 +Connection ~ 2800 2450 +Wire Wire Line + 2400 2100 2400 2900 +Connection ~ 2400 2900 +Wire Wire Line + 3050 3250 2800 3250 +Connection ~ 2800 3250 +Wire Wire Line + 3150 3900 2850 3900 +Connection ~ 2850 4000 +Wire Wire Line + 3200 5000 2850 5000 +Connection ~ 2850 5000 +Wire Wire Line + 2450 5300 2450 4550 +Connection ~ 2450 4550 +Wire Wire Line + 7750 2900 7750 3250 +Connection ~ 7750 3250 +Wire Wire Line + 8450 2850 8450 3800 +Connection ~ 8450 3800 +Wire Wire Line + 8050 4500 8050 4300 +Connection ~ 8050 4300 +$Comp +L eSim_GND #PWR03 +U 1 1 5CF252A6 +P 10500 4050 +F 0 "#PWR03" H 10500 3800 50 0001 C CNN +F 1 "eSim_GND" H 10500 3900 50 0000 C CNN +F 2 "" H 10500 4050 50 0001 C CNN +F 3 "" H 10500 4050 50 0001 C CNN + 1 10500 4050 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U13 +U 1 1 5CF252A7 +P 7900 6100 +F 0 "U13" H 7900 6600 60 0000 C CNN +F 1 "plot_v1" H 8100 6450 60 0000 C CNN +F 2 "" H 7900 6100 60 0000 C CNN +F 3 "" H 7900 6100 60 0000 C CNN + 1 7900 6100 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U15 +U 1 1 5CF252A8 +P 8250 5700 +F 0 "U15" H 8250 6200 60 0000 C CNN +F 1 "plot_v1" H 8450 6050 60 0000 C CNN +F 2 "" H 8250 5700 60 0000 C CNN +F 3 "" H 8250 5700 60 0000 C CNN + 1 8250 5700 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 5CF252A9 +P 7600 5200 +F 0 "U11" H 7600 5700 60 0000 C CNN +F 1 "plot_v1" H 7800 5550 60 0000 C CNN +F 2 "" H 7600 5200 60 0000 C CNN +F 3 "" H 7600 5200 60 0000 C CNN + 1 7600 5200 + 0 1 1 0 +$EndComp +Wire Wire Line + 7800 5200 7350 5200 +Wire Wire Line + 7350 5200 7350 5700 +Wire Wire Line + 7350 5800 7850 5800 +Wire Wire Line + 7850 5800 7850 5700 +Wire Wire Line + 7850 5700 8450 5700 +Wire Wire Line + 7350 5900 7650 5900 +Wire Wire Line + 7650 5900 7650 6100 +Wire Wire Line + 7450 6100 8100 6100 +Text GLabel 7200 5300 0 60 Input ~ 0 +q1 +Text GLabel 7700 5650 1 60 Input ~ 0 +q2 +Text GLabel 7450 6100 0 60 Input ~ 0 +q3 +Text GLabel 7900 4400 0 60 Input ~ 0 +c3 +Text GLabel 8300 3500 0 60 Input ~ 0 +b3 +Text GLabel 7600 3050 0 60 Input ~ 0 +a3 +Wire Wire Line + 7550 3050 7750 3050 +Connection ~ 7750 3050 +Wire Wire Line + 8300 3500 8450 3500 +Connection ~ 8450 3500 +Wire Wire Line + 7900 4400 8050 4400 +Connection ~ 8050 4400 +Wire Wire Line + 7200 5300 7350 5300 +Connection ~ 7350 5300 +Wire Wire Line + 7700 5650 7700 5800 +Connection ~ 7700 5800 +Connection ~ 7650 6100 +Text GLabel 2350 4750 0 60 Input ~ 0 +b2 +Text GLabel 3050 5150 3 60 Input ~ 0 +c2 +Text GLabel 3000 4000 3 60 Input ~ 0 +a2 +Text GLabel 2950 3400 3 60 Input ~ 0 +c1 +Text GLabel 2250 2650 0 60 Input ~ 0 +b1 +Text GLabel 3000 2300 0 60 Input ~ 0 +a1 +Wire Wire Line + 3000 2300 3100 2300 +Connection ~ 3100 2300 +Wire Wire Line + 2250 2650 2400 2650 +Connection ~ 2400 2650 +Wire Wire Line + 2950 3400 2950 3250 +Connection ~ 2950 3250 +Wire Wire Line + 3000 4000 3000 3900 +Connection ~ 3000 3900 +Wire Wire Line + 2350 4750 2450 4750 +Connection ~ 2450 4750 +Wire Wire Line + 3050 5150 3050 5000 +Connection ~ 3050 5000 +$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test_Previous_Values.xml new file mode 100644 index 00000000..7d4e7303 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v5 name="Source type">dc<field1 name="Value">5</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v7 name="Source type">dc<field1 name="Value">5</field1></v7><v8 name="Source type">dc<field1 name="Value">5</field1></v8><v9 name="Source type">dc<field1 name="Value">0</field1></v9></source><model><u8 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u8><u7 name="type">adc_bridge<field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter value for in_low (default=1.0)" /></u7><u10 name="type">adc_bridge<field9 name="Enter Fall Delay (default=1.0e-9)" /><field10 name="Enter value for in_high (default=2.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter value for in_low (default=1.0)" /></u10><u9 name="type">dac_bridge<field13 name="Enter value for input load (default=1.0e-12)" /><field14 name="Enter value for out_low (default=0.0)" /><field15 name="Enter value for out_high (default=5.0)" /><field16 name="Enter the Rise Time (default=1.0e-9)" /><field17 name="Enter the Fall Time (default=1.0e-9)" /><field18 name="Enter value for out_undef (default=0.5)" /></u9></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4073</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/analysis b/Examples/Analysis_Of_Digital_IC/4073_test/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012-cache.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012-cache.lib new file mode 100644 index 00000000..6e0697ee --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.cir b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.cir new file mode 100644 index 00000000..c81542fc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.cir @@ -0,0 +1,19 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4012\4012.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:11:02
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U8 Net-_U6-Pad3_ Net-_U1-Pad1_ d_inverter
+U9 Net-_U7-Pad3_ Net-_U1-Pad13_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and
+U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_and
+U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_and
+U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_and
+U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and
+U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_and
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.cir.out b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.cir.out new file mode 100644 index 00000000..b34bbe45 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.cir.out @@ -0,0 +1,44 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+
+* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.pro b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.pro new file mode 100644 index 00000000..6ce7d980 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.pro @@ -0,0 +1,44 @@ +update=06/01/19 13:10:32
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_User
+LibName11=eSim_Subckt
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.sch b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.sch new file mode 100644 index 00000000..6b950a1d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.sch @@ -0,0 +1,342 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4012-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 3350 2600 2550 2600
+Wire Wire Line
+ 3350 2700 3150 2700
+Wire Wire Line
+ 3150 2700 3150 2850
+Wire Wire Line
+ 3150 2850 2550 2850
+Wire Wire Line
+ 3350 3200 3150 3200
+Wire Wire Line
+ 3150 3200 3150 3100
+Wire Wire Line
+ 3150 3100 2550 3100
+Wire Wire Line
+ 3350 3300 2550 3300
+Wire Wire Line
+ 5200 2950 5500 2950
+$Comp
+L d_inverter U8
+U 1 1 5CEE55AB
+P 5800 2950
+F 0 "U8" H 5800 2850 60 0000 C CNN
+F 1 "d_inverter" H 5800 3100 60 0000 C CNN
+F 2 "" H 5850 2900 60 0000 C CNN
+F 3 "" H 5850 2900 60 0000 C CNN
+ 1 5800 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6100 2950 6500 2950
+Wire Wire Line
+ 3400 3950 2600 3950
+Wire Wire Line
+ 3400 4050 3200 4050
+Wire Wire Line
+ 3200 4050 3200 4200
+Wire Wire Line
+ 3200 4200 2600 4200
+Wire Wire Line
+ 3400 4550 3200 4550
+Wire Wire Line
+ 3200 4550 3200 4450
+Wire Wire Line
+ 3200 4450 2600 4450
+Wire Wire Line
+ 3400 4650 2600 4650
+Wire Wire Line
+ 5250 4300 5550 4300
+$Comp
+L d_inverter U9
+U 1 1 5CEE5715
+P 5850 4300
+F 0 "U9" H 5850 4200 60 0000 C CNN
+F 1 "d_inverter" H 5850 4450 60 0000 C CNN
+F 2 "" H 5900 4250 60 0000 C CNN
+F 3 "" H 5900 4250 60 0000 C CNN
+ 1 5850 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6150 4300 6550 4300
+$Comp
+L PORT U1
+U 2 1 5CEE57D6
+P 2300 2600
+F 0 "U1" H 2350 2700 30 0000 C CNN
+F 1 "PORT" H 2300 2600 30 0000 C CNN
+F 2 "" H 2300 2600 60 0000 C CNN
+F 3 "" H 2300 2600 60 0000 C CNN
+ 2 2300 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CEE587B
+P 2300 2850
+F 0 "U1" H 2350 2950 30 0000 C CNN
+F 1 "PORT" H 2300 2850 30 0000 C CNN
+F 2 "" H 2300 2850 60 0000 C CNN
+F 3 "" H 2300 2850 60 0000 C CNN
+ 3 2300 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CEE58AF
+P 2300 3100
+F 0 "U1" H 2350 3200 30 0000 C CNN
+F 1 "PORT" H 2300 3100 30 0000 C CNN
+F 2 "" H 2300 3100 60 0000 C CNN
+F 3 "" H 2300 3100 60 0000 C CNN
+ 4 2300 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CEE58E6
+P 6800 4300
+F 0 "U1" H 6850 4400 30 0000 C CNN
+F 1 "PORT" H 6800 4300 30 0000 C CNN
+F 2 "" H 6800 4300 60 0000 C CNN
+F 3 "" H 6800 4300 60 0000 C CNN
+ 13 6800 4300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CEE5922
+P 2300 3300
+AR Path="/5CEE58E6" Ref="U1" Part="1"
+AR Path="/5CEE5922" Ref="U1" Part="5"
+F 0 "U1" H 2350 3400 30 0000 C CNN
+F 1 "PORT" H 2300 3300 30 0000 C CNN
+F 2 "" H 2300 3300 60 0000 C CNN
+F 3 "" H 2300 3300 60 0000 C CNN
+ 5 2300 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CEE596F
+P 2350 3950
+AR Path="/5CEE5922" Ref="U1" Part="5"
+AR Path="/5CEE596F" Ref="U1" Part="9"
+F 0 "U1" H 2400 4050 30 0000 C CNN
+F 1 "PORT" H 2350 3950 30 0000 C CNN
+F 2 "" H 2350 3950 60 0000 C CNN
+F 3 "" H 2350 3950 60 0000 C CNN
+ 9 2350 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE59AF
+P 2350 4200
+AR Path="/5CEE596F" Ref="U1" Part="6"
+AR Path="/5CEE59AF" Ref="U1" Part="10"
+F 0 "U1" H 2400 4300 30 0000 C CNN
+F 1 "PORT" H 2350 4200 30 0000 C CNN
+F 2 "" H 2350 4200 60 0000 C CNN
+F 3 "" H 2350 4200 60 0000 C CNN
+ 10 2350 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE59F6
+P 2350 4450
+AR Path="/5CEE59AF" Ref="U1" Part="7"
+AR Path="/5CEE59F6" Ref="U1" Part="11"
+F 0 "U1" H 2400 4550 30 0000 C CNN
+F 1 "PORT" H 2350 4450 30 0000 C CNN
+F 2 "" H 2350 4450 60 0000 C CNN
+F 3 "" H 2350 4450 60 0000 C CNN
+ 11 2350 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE5A6A
+P 2350 4650
+AR Path="/5CEE59F6" Ref="U1" Part="8"
+AR Path="/5CEE5A6A" Ref="U1" Part="12"
+F 0 "U1" H 2400 4750 30 0000 C CNN
+F 1 "PORT" H 2350 4650 30 0000 C CNN
+F 2 "" H 2350 4650 60 0000 C CNN
+F 3 "" H 2350 4650 60 0000 C CNN
+ 12 2350 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE5BF8
+P 6750 2950
+AR Path="/5CEE5A6A" Ref="U1" Part="9"
+AR Path="/5CEE5BF8" Ref="U1" Part="1"
+F 0 "U1" H 6800 3050 30 0000 C CNN
+F 1 "PORT" H 6750 2950 30 0000 C CNN
+F 2 "" H 6750 2950 60 0000 C CNN
+F 3 "" H 6750 2950 60 0000 C CNN
+ 1 6750 2950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CEE5C72
+P 7850 1450
+F 0 "U1" H 7900 1550 30 0000 C CNN
+F 1 "PORT" H 7850 1450 30 0000 C CNN
+F 2 "" H 7850 1450 60 0000 C CNN
+F 3 "" H 7850 1450 60 0000 C CNN
+ 6 7850 1450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CEE5D23
+P 7850 1700
+F 0 "U1" H 7900 1800 30 0000 C CNN
+F 1 "PORT" H 7850 1700 30 0000 C CNN
+F 2 "" H 7850 1700 60 0000 C CNN
+F 3 "" H 7850 1700 60 0000 C CNN
+ 7 7850 1700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CEE5D75
+P 7850 1950
+F 0 "U1" H 7900 2050 30 0000 C CNN
+F 1 "PORT" H 7850 1950 30 0000 C CNN
+F 2 "" H 7850 1950 60 0000 C CNN
+F 3 "" H 7850 1950 60 0000 C CNN
+ 14 7850 1950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CEE5DCA
+P 7850 2250
+F 0 "U1" H 7900 2350 30 0000 C CNN
+F 1 "PORT" H 7850 2250 30 0000 C CNN
+F 2 "" H 7850 2250 60 0000 C CNN
+F 3 "" H 7850 2250 60 0000 C CNN
+ 8 7850 2250
+ -1 0 0 1
+$EndComp
+NoConn ~ 7600 1450
+NoConn ~ 7600 1700
+NoConn ~ 7600 1950
+NoConn ~ 7600 2250
+$Comp
+L d_and U4
+U 1 1 5CEE56F6
+P 3850 4050
+F 0 "U4" H 3850 4050 60 0000 C CNN
+F 1 "d_and" H 3900 4150 60 0000 C CNN
+F 2 "" H 3850 4050 60 0000 C CNN
+F 3 "" H 3850 4050 60 0000 C CNN
+ 1 3850 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 5CEE56FC
+P 3850 4650
+F 0 "U5" H 3850 4650 60 0000 C CNN
+F 1 "d_and" H 3900 4750 60 0000 C CNN
+F 2 "" H 3850 4650 60 0000 C CNN
+F 3 "" H 3850 4650 60 0000 C CNN
+ 1 3850 4650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4350 4600 4300 4600
+Wire Wire Line
+ 4350 4350 4350 4600
+Wire Wire Line
+ 4350 4000 4350 4250
+Wire Wire Line
+ 4300 4000 4350 4000
+$Comp
+L d_and U7
+U 1 1 5CEE5702
+P 4800 4350
+F 0 "U7" H 4800 4350 60 0000 C CNN
+F 1 "d_and" H 4850 4450 60 0000 C CNN
+F 2 "" H 4800 4350 60 0000 C CNN
+F 3 "" H 4800 4350 60 0000 C CNN
+ 1 4800 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4250 2650 4300 2650
+Wire Wire Line
+ 4300 3250 4250 3250
+Wire Wire Line
+ 4300 2650 4300 2900
+Wire Wire Line
+ 4300 3000 4300 3250
+$Comp
+L d_and U6
+U 1 1 5CEE5432
+P 4750 3000
+F 0 "U6" H 4750 3000 60 0000 C CNN
+F 1 "d_and" H 4800 3100 60 0000 C CNN
+F 2 "" H 4750 3000 60 0000 C CNN
+F 3 "" H 4750 3000 60 0000 C CNN
+ 1 4750 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5CEE540C
+P 3800 3300
+F 0 "U3" H 3800 3300 60 0000 C CNN
+F 1 "d_and" H 3850 3400 60 0000 C CNN
+F 2 "" H 3800 3300 60 0000 C CNN
+F 3 "" H 3800 3300 60 0000 C CNN
+ 1 3800 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5CEE53DC
+P 3800 2700
+F 0 "U2" H 3800 2700 60 0000 C CNN
+F 1 "d_and" H 3850 2800 60 0000 C CNN
+F 2 "" H 3800 2700 60 0000 C CNN
+F 3 "" H 3800 2700 60 0000 C CNN
+ 1 3800 2700
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.sub b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.sub new file mode 100644 index 00000000..a92e83f3 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012.sub @@ -0,0 +1,38 @@ +* Subcircuit 4012
+.subckt 4012 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4012\4012.cir
+* u8 net-_u6-pad3_ net-_u1-pad1_ d_inverter
+* u9 net-_u7-pad3_ net-_u1-pad13_ d_inverter
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_and
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_and
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ d_and
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_and
+a1 net-_u6-pad3_ net-_u1-pad1_ u8
+a2 net-_u7-pad3_ net-_u1-pad13_ u9
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a5 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a7 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4012
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012_Previous_Values.xml new file mode 100644 index 00000000..4e7e73b2 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4012_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u8 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u8><u9 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u9><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u3 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u3><u2 name="type">d_and<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib new file mode 100644 index 00000000..10a35d95 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib @@ -0,0 +1,122 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4012 +# +DEF 4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.cir b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.cir new file mode 100644 index 00000000..89708044 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim-Workspace\4012_test\4012_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 15:21:40
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U7-Pad1_ Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ ? ? ? Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ Net-_U7-Pad2_ ? 4012
+U5 a1 b1 c1 d1 Net-_U5-Pad5_ Net-_U5-Pad6_ Net-_U5-Pad7_ Net-_U5-Pad8_ adc_bridge_4
+v1 a1 GND DC
+v2 b1 GND DC
+v3 c1 GND DC
+v4 d1 GND DC
+U9 a2 b2 d2 c2 Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ adc_bridge_4
+v8 a2 GND DC
+v7 b2 GND DC
+v6 d2 GND DC
+v5 c2 GND DC
+U1 a1 plot_v1
+U3 b1 plot_v1
+U4 c1 plot_v1
+U2 d1 plot_v1
+U11 d2 plot_v1
+U10 c2 plot_v1
+U13 a2 plot_v1
+U12 b2 plot_v1
+U7 Net-_U7-Pad1_ Net-_U7-Pad2_ q1 q2 dac_bridge_2
+U8 q2 plot_v1
+U6 q1 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.cir.out b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.cir.out new file mode 100644 index 00000000..401ab92b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.cir.out @@ -0,0 +1,53 @@ +* c:\users\malli\esim-workspace\4012_test\4012_test.cir + +.include 4012.sub +x1 net-_u7-pad1_ net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ? ? ? net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ net-_u7-pad2_ ? 4012 +* u5 a1 b1 c1 d1 net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ adc_bridge_4 +v1 a1 gnd dc 5 +v2 b1 gnd dc 5 +v3 c1 gnd dc 5 +v4 d1 gnd dc 5 +* u9 a2 b2 d2 c2 net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ adc_bridge_4 +v8 a2 gnd dc 5 +v7 b2 gnd dc 5 +v6 d2 gnd dc 5 +v5 c2 gnd dc 5 +* u1 a1 plot_v1 +* u3 b1 plot_v1 +* u4 c1 plot_v1 +* u2 d1 plot_v1 +* u11 d2 plot_v1 +* u10 c2 plot_v1 +* u13 a2 plot_v1 +* u12 b2 plot_v1 +* u7 net-_u7-pad1_ net-_u7-pad2_ q1 q2 dac_bridge_2 +* u8 q2 plot_v1 +* u6 q1 plot_v1 +a1 [a1 b1 c1 d1 ] [net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ] u5 +a2 [a2 b2 d2 c2 ] [net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] u9 +a3 [net-_u7-pad1_ net-_u7-pad2_ ] [q1 q2 ] u7 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(a1) +plot v(b1) +plot v(c1) +plot v(d1) +plot v(d2) +plot v(c2) +plot v(a2) +plot v(b2) +plot v(q2) +plot v(q1) +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro new file mode 100644 index 00000000..ee32c69b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro @@ -0,0 +1,45 @@ +update=06/01/19 15:09:21
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_User
+LibName12=eSim_Subckt
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.proj b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.proj new file mode 100644 index 00000000..6d5be088 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.proj @@ -0,0 +1 @@ +schematicFile 4012_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch new file mode 100644 index 00000000..55a46f82 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch @@ -0,0 +1,503 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4_Input_NAND_Charcateristics-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4012 X1 +U 1 1 5CF22C85 +P 5050 4050 +F 0 "X1" H 5050 4050 60 0000 C CNN +F 1 "4012" H 5050 4250 60 0000 C CNN +F 2 "" H 5050 4050 60 0000 C CNN +F 3 "" H 5050 4050 60 0000 C CNN + 1 5050 4050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U5 +U 1 1 5CF24801 +P 3600 4050 +F 0 "U5" H 3600 4050 60 0000 C CNN +F 1 "adc_bridge_4" H 3600 4350 60 0000 C CNN +F 2 "" H 3600 4050 60 0000 C CNN +F 3 "" H 3600 4050 60 0000 C CNN + 1 3600 4050 + 1 0 0 -1 +$EndComp +NoConn ~ 4550 4350 +NoConn ~ 5600 3750 +$Comp +L DC v1 +U 1 1 5CF2488C +P 1900 3450 +F 0 "v1" H 1700 3550 60 0000 C CNN +F 1 "DC" H 1700 3400 60 0000 C CNN +F 2 "R1" H 1600 3450 60 0000 C CNN +F 3 "" H 1900 3450 60 0000 C CNN + 1 1900 3450 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 5CF248E2 +P 1900 4000 +F 0 "v2" H 1700 4100 60 0000 C CNN +F 1 "DC" H 1700 3950 60 0000 C CNN +F 2 "R1" H 1600 4000 60 0000 C CNN +F 3 "" H 1900 4000 60 0000 C CNN + 1 1900 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 5CF24906 +P 1900 4550 +F 0 "v3" H 1700 4650 60 0000 C CNN +F 1 "DC" H 1700 4500 60 0000 C CNN +F 2 "R1" H 1600 4550 60 0000 C CNN +F 3 "" H 1900 4550 60 0000 C CNN + 1 1900 4550 + 0 1 1 0 +$EndComp +$Comp +L DC v4 +U 1 1 5CF24935 +P 1900 5100 +F 0 "v4" H 1700 5200 60 0000 C CNN +F 1 "DC" H 1700 5050 60 0000 C CNN +F 2 "R1" H 1600 5100 60 0000 C CNN +F 3 "" H 1900 5100 60 0000 C CNN + 1 1900 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 2350 3450 2800 3450 +Wire Wire Line + 2800 3450 2800 3850 +Wire Wire Line + 2800 3850 3050 3850 +Wire Wire Line + 3050 3950 2350 3950 +Wire Wire Line + 2350 3950 2350 4000 +Wire Wire Line + 2350 4550 2700 4550 +Wire Wire Line + 2700 4550 2700 4050 +Wire Wire Line + 2700 4050 3050 4050 +Wire Wire Line + 3050 4150 3050 5100 +Wire Wire Line + 3050 5100 2350 5100 +Wire Wire Line + 1450 3450 1200 3450 +Wire Wire Line + 1200 3450 1200 5100 +Wire Wire Line + 1200 4000 1450 4000 +Wire Wire Line + 1200 4550 1450 4550 +Connection ~ 1200 4000 +Wire Wire Line + 1200 5100 1450 5100 +Connection ~ 1200 4550 +$Comp +L adc_bridge_4 U9 +U 1 1 5CF24B4A +P 6450 4050 +F 0 "U9" H 6450 4050 60 0000 C CNN +F 1 "adc_bridge_4" H 6450 4350 60 0000 C CNN +F 2 "" H 6450 4050 60 0000 C CNN +F 3 "" H 6450 4050 60 0000 C CNN + 1 6450 4050 + -1 0 0 1 +$EndComp +$Comp +L DC v8 +U 1 1 5CF24B50 +P 8150 4650 +F 0 "v8" H 7950 4750 60 0000 C CNN +F 1 "DC" H 7950 4600 60 0000 C CNN +F 2 "R1" H 7850 4650 60 0000 C CNN +F 3 "" H 8150 4650 60 0000 C CNN + 1 8150 4650 + 0 -1 -1 0 +$EndComp +$Comp +L DC v7 +U 1 1 5CF24B56 +P 8150 4100 +F 0 "v7" H 7950 4200 60 0000 C CNN +F 1 "DC" H 7950 4050 60 0000 C CNN +F 2 "R1" H 7850 4100 60 0000 C CNN +F 3 "" H 8150 4100 60 0000 C CNN + 1 8150 4100 + 0 -1 -1 0 +$EndComp +$Comp +L DC v6 +U 1 1 5CF24B5C +P 8150 3550 +F 0 "v6" H 7950 3650 60 0000 C CNN +F 1 "DC" H 7950 3500 60 0000 C CNN +F 2 "R1" H 7850 3550 60 0000 C CNN +F 3 "" H 8150 3550 60 0000 C CNN + 1 8150 3550 + 0 -1 -1 0 +$EndComp +$Comp +L DC v5 +U 1 1 5CF24B62 +P 8150 3000 +F 0 "v5" H 7950 3100 60 0000 C CNN +F 1 "DC" H 7950 2950 60 0000 C CNN +F 2 "R1" H 7850 3000 60 0000 C CNN +F 3 "" H 8150 3000 60 0000 C CNN + 1 8150 3000 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7700 4650 7250 4650 +Wire Wire Line + 7250 4650 7250 4250 +Wire Wire Line + 7250 4250 7000 4250 +Wire Wire Line + 7000 4150 7700 4150 +Wire Wire Line + 7700 4150 7700 4100 +Wire Wire Line + 7700 3550 7350 3550 +Wire Wire Line + 7350 3400 7350 4050 +Wire Wire Line + 7350 4050 7000 4050 +Wire Wire Line + 7000 3950 7000 3000 +Wire Wire Line + 7000 3000 7700 3000 +Wire Wire Line + 8600 4650 8850 4650 +Wire Wire Line + 8850 4650 8850 3000 +Wire Wire Line + 8850 4100 8600 4100 +Wire Wire Line + 8850 3550 8600 3550 +Connection ~ 8850 4100 +Wire Wire Line + 8850 3000 8600 3000 +Connection ~ 8850 3550 +Wire Wire Line + 5900 3950 5600 3950 +Wire Wire Line + 5600 4050 5900 4050 +Wire Wire Line + 5600 4150 5900 4150 +Wire Wire Line + 5600 4250 5900 4250 +Wire Wire Line + 4550 3850 4150 3850 +Wire Wire Line + 4150 3950 4550 3950 +Wire Wire Line + 4150 4050 4550 4050 +Wire Wire Line + 4550 4150 4150 4150 +$Comp +L plot_v1 U1 +U 1 1 5CF2512D +P 2400 3300 +F 0 "U1" H 2400 3800 60 0000 C CNN +F 1 "plot_v1" H 2600 3650 60 0000 C CNN +F 2 "" H 2400 3300 60 0000 C CNN +F 3 "" H 2400 3300 60 0000 C CNN + 1 2400 3300 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5CF25268 +P 3000 3450 +F 0 "U3" H 3000 3950 60 0000 C CNN +F 1 "plot_v1" H 3200 3800 60 0000 C CNN +F 2 "" H 3000 3450 60 0000 C CNN +F 3 "" H 3000 3450 60 0000 C CNN + 1 3000 3450 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5CF252A7 +P 3050 4600 +F 0 "U4" H 3050 5100 60 0000 C CNN +F 1 "plot_v1" H 3250 4950 60 0000 C CNN +F 2 "" H 3050 4600 60 0000 C CNN +F 3 "" H 3050 4600 60 0000 C CNN + 1 3050 4600 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 5CF25311 +P 2900 5100 +F 0 "U2" H 2900 5600 60 0000 C CNN +F 1 "plot_v1" H 3100 5450 60 0000 C CNN +F 2 "" H 2900 5100 60 0000 C CNN +F 3 "" H 2900 5100 60 0000 C CNN + 1 2900 5100 + -1 0 0 1 +$EndComp +Wire Wire Line + 2400 3100 2400 3450 +Connection ~ 2400 3450 +Wire Wire Line + 3000 3250 3000 3550 +Wire Wire Line + 3000 3550 2700 3550 +Wire Wire Line + 2700 3550 2700 3950 +Connection ~ 2700 3950 +Wire Wire Line + 2700 4450 3250 4450 +Wire Wire Line + 3250 4450 3250 4600 +Connection ~ 2700 4450 +Wire Wire Line + 2900 5100 2900 5300 +Connection ~ 2900 5100 +Wire Wire Line + 1200 4250 850 4250 +Wire Wire Line + 850 4150 850 4500 +Connection ~ 1200 4250 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5CF254BC +P 850 4150 +F 0 "#FLG01" H 850 4245 50 0001 C CNN +F 1 "PWR_FLAG" H 850 4330 50 0000 C CNN +F 2 "" H 850 4150 50 0000 C CNN +F 3 "" H 850 4150 50 0000 C CNN + 1 850 4150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR02 +U 1 1 5CF254EE +P 850 4500 +F 0 "#PWR02" H 850 4250 50 0001 C CNN +F 1 "eSim_GND" H 850 4350 50 0000 C CNN +F 2 "" H 850 4500 50 0001 C CNN +F 3 "" H 850 4500 50 0001 C CNN + 1 850 4500 + 1 0 0 -1 +$EndComp +Connection ~ 850 4250 +Text GLabel 2300 3250 0 60 Input ~ 0 +a1 +Text GLabel 2900 3350 0 60 Input ~ 0 +b1 +Text GLabel 2900 4550 3 60 Input ~ 0 +c1 +Text GLabel 2800 5200 0 60 Input ~ 0 +d1 +Wire Wire Line + 2800 5200 2900 5200 +Connection ~ 2900 5200 +Wire Wire Line + 2900 4450 2900 4550 +Connection ~ 2900 4450 +Wire Wire Line + 2900 3350 3000 3350 +Connection ~ 3000 3350 +Wire Wire Line + 2300 3250 2400 3250 +Connection ~ 2400 3250 +$Comp +L plot_v1 U11 +U 1 1 5CF2581B +P 7200 3000 +F 0 "U11" H 7200 3500 60 0000 C CNN +F 1 "plot_v1" H 7400 3350 60 0000 C CNN +F 2 "" H 7200 3000 60 0000 C CNN +F 3 "" H 7200 3000 60 0000 C CNN + 1 7200 3000 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U10 +U 1 1 5CF25889 +P 6500 3450 +F 0 "U10" H 6500 3950 60 0000 C CNN +F 1 "plot_v1" H 6700 3800 60 0000 C CNN +F 2 "" H 6500 3450 60 0000 C CNN +F 3 "" H 6500 3450 60 0000 C CNN + 1 6500 3450 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U13 +U 1 1 5CF258F2 +P 7550 4750 +F 0 "U13" H 7550 5250 60 0000 C CNN +F 1 "plot_v1" H 7750 5100 60 0000 C CNN +F 2 "" H 7550 4750 60 0000 C CNN +F 3 "" H 7550 4750 60 0000 C CNN + 1 7550 4750 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 5CF2597E +P 7200 4800 +F 0 "U12" H 7200 5300 60 0000 C CNN +F 1 "plot_v1" H 7400 5150 60 0000 C CNN +F 2 "" H 7200 4800 60 0000 C CNN +F 3 "" H 7200 4800 60 0000 C CNN + 1 7200 4800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7550 4950 7550 4650 +Connection ~ 7550 4650 +Wire Wire Line + 7000 4800 7150 4800 +Wire Wire Line + 7150 4800 7150 4150 +Connection ~ 7150 4150 +Wire Wire Line + 7200 2800 7200 3400 +Wire Wire Line + 7200 3400 7350 3400 +Connection ~ 7350 3550 +Wire Wire Line + 6500 3250 6500 3450 +Wire Wire Line + 6500 3450 7000 3450 +Connection ~ 7000 3450 +Wire Wire Line + 8850 3800 9450 3800 +Wire Wire Line + 9450 3800 9450 4150 +Connection ~ 8850 3800 +$Comp +L eSim_GND #PWR03 +U 1 1 5CF25F3B +P 9450 4150 +F 0 "#PWR03" H 9450 3900 50 0001 C CNN +F 1 "eSim_GND" H 9450 4000 50 0000 C CNN +F 2 "" H 9450 4150 50 0001 C CNN +F 3 "" H 9450 4150 50 0001 C CNN + 1 9450 4150 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U7 +U 1 1 5CF26149 +P 5050 2800 +F 0 "U7" H 5050 2800 60 0000 C CNN +F 1 "dac_bridge_2" H 5100 2950 60 0000 C CNN +F 2 "" H 5050 2800 60 0000 C CNN +F 3 "" H 5050 2800 60 0000 C CNN + 1 5050 2800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4550 3250 4550 3750 +Wire Wire Line + 4550 3250 5000 3250 +Wire Wire Line + 5100 3250 5800 3250 +Wire Wire Line + 5800 3250 5800 3850 +Wire Wire Line + 5800 3850 5600 3850 +$Comp +L plot_v1 U8 +U 1 1 5CF263AC +P 5400 2000 +F 0 "U8" H 5400 2500 60 0000 C CNN +F 1 "plot_v1" H 5600 2350 60 0000 C CNN +F 2 "" H 5400 2000 60 0000 C CNN +F 3 "" H 5400 2000 60 0000 C CNN + 1 5400 2000 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5CF26445 +P 4800 2050 +F 0 "U6" H 4800 2550 60 0000 C CNN +F 1 "plot_v1" H 5000 2400 60 0000 C CNN +F 2 "" H 4800 2050 60 0000 C CNN +F 3 "" H 4800 2050 60 0000 C CNN + 1 4800 2050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5000 2250 5000 2050 +Wire Wire Line + 5000 2050 4600 2050 +Wire Wire Line + 5100 2250 5100 2000 +Wire Wire Line + 5100 2000 5600 2000 +Text GLabel 4800 1850 1 60 Output ~ 0 +q1 +Text GLabel 5400 1850 1 60 Output ~ 0 +q2 +Text GLabel 7350 2900 2 60 Input ~ 0 +d2 +Text GLabel 6800 3350 1 60 Input ~ 0 +c2 +Text GLabel 7100 4500 0 60 Input ~ 0 +b2 +Text GLabel 7450 4800 0 60 Input ~ 0 +a2 +Wire Wire Line + 7450 4800 7550 4800 +Connection ~ 7550 4800 +Wire Wire Line + 7100 4500 7150 4500 +Connection ~ 7150 4500 +Wire Wire Line + 6800 3350 6800 3450 +Connection ~ 6800 3450 +Wire Wire Line + 7350 2900 7200 2900 +Connection ~ 7200 2900 +Wire Wire Line + 5400 1850 5400 2000 +Connection ~ 5400 2000 +Wire Wire Line + 4800 1850 4800 2050 +Connection ~ 4800 2050 +Text Notes 4200 5400 0 118 Italic 24 +4012 IC Characteristics +$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics_Previous_Values.xml new file mode 100644 index 00000000..87c47261 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v7 name="Source type">dc<field1 name="Value">0</field1></v7><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v5 name="Source type">dc<field1 name="Value">0</field1></v5></source><model><u5 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u5><u9 name="type">adc_bridge<field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter value for in_low (default=1.0)" /></u9><u7 name="type">dac_bridge<field9 name="Enter value for input load (default=1.0e-12)" /><field10 name="Enter value for out_low (default=0.0)" /><field11 name="Enter value for out_high (default=5.0)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /><field14 name="Enter value for out_undef (default=0.5)" /></u7></model><devicemodel /><subcircuit><x1><field>/home/mallikarjuna/Downloads/eSim-1.1.2/src/SubcircuitLibrary/4012</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/analysis b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002-cache.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002-cache.lib new file mode 100644 index 00000000..dd565db9 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002-cache.lib @@ -0,0 +1,82 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.cir b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.cir new file mode 100644 index 00000000..36ad9450 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.cir @@ -0,0 +1,17 @@ +* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or
+U5 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or
+U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.cir.out b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.cir.out new file mode 100644 index 00000000..ca055749 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.cir.out @@ -0,0 +1,36 @@ +* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.pro b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.pro new file mode 100644 index 00000000..e7859256 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.pro @@ -0,0 +1,44 @@ +update=05/31/19 09:35:41
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
+LibName11=power
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.sch b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.sch new file mode 100644 index 00000000..38f453cd --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.sch @@ -0,0 +1,315 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5CEE059A
+P 4750 2900
+F 0 "U2" H 4750 2900 60 0000 C CNN
+F 1 "d_or" H 4750 3000 60 0000 C CNN
+F 2 "" H 4750 2900 60 0000 C CNN
+F 3 "" H 4750 2900 60 0000 C CNN
+ 1 4750 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5CEE0629
+P 4750 3450
+F 0 "U3" H 4750 3450 60 0000 C CNN
+F 1 "d_or" H 4750 3550 60 0000 C CNN
+F 2 "" H 4750 3450 60 0000 C CNN
+F 3 "" H 4750 3450 60 0000 C CNN
+ 1 4750 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 5CEE0663
+P 6000 3100
+F 0 "U6" H 6000 3100 60 0000 C CNN
+F 1 "d_nor" H 6050 3200 60 0000 C CNN
+F 2 "" H 6000 3100 60 0000 C CNN
+F 3 "" H 6000 3100 60 0000 C CNN
+ 1 6000 3100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5200 2850 5400 2850
+Wire Wire Line
+ 5400 2850 5400 3000
+Wire Wire Line
+ 5400 3000 5550 3000
+Wire Wire Line
+ 5200 3400 5400 3400
+Wire Wire Line
+ 5400 3400 5400 3100
+Wire Wire Line
+ 5400 3100 5550 3100
+Wire Wire Line
+ 5650 5350 6050 5350
+Wire Wire Line
+ 5650 5550 6050 5550
+Wire Wire Line
+ 5650 5800 6050 5800
+Wire Wire Line
+ 5650 6000 6050 6000
+NoConn ~ 5650 5350
+NoConn ~ 5650 5550
+NoConn ~ 5650 5800
+NoConn ~ 5650 6000
+$Comp
+L PORT U1
+U 2 1 5CEE1C41
+P 3850 2800
+F 0 "U1" H 3900 2900 30 0000 C CNN
+F 1 "PORT" H 3850 2800 30 0000 C CNN
+F 2 "" H 3850 2800 60 0000 C CNN
+F 3 "" H 3850 2800 60 0000 C CNN
+ 2 3850 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CEE22EE
+P 3900 3050
+F 0 "U1" H 3950 3150 30 0000 C CNN
+F 1 "PORT" H 3900 3050 30 0000 C CNN
+F 2 "" H 3900 3050 60 0000 C CNN
+F 3 "" H 3900 3050 60 0000 C CNN
+ 3 3900 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CEE2322
+P 3900 3250
+F 0 "U1" H 3950 3350 30 0000 C CNN
+F 1 "PORT" H 3900 3250 30 0000 C CNN
+F 2 "" H 3900 3250 60 0000 C CNN
+F 3 "" H 3900 3250 60 0000 C CNN
+ 5 3900 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CEE2351
+P 3900 3550
+F 0 "U1" H 3950 3650 30 0000 C CNN
+F 1 "PORT" H 3900 3550 30 0000 C CNN
+F 2 "" H 3900 3550 60 0000 C CNN
+F 3 "" H 3900 3550 60 0000 C CNN
+ 4 3900 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE2387
+P 6950 3050
+F 0 "U1" H 7000 3150 30 0000 C CNN
+F 1 "PORT" H 6950 3050 30 0000 C CNN
+F 2 "" H 6950 3050 60 0000 C CNN
+F 3 "" H 6950 3050 60 0000 C CNN
+ 1 6950 3050
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4100 2800 4300 2800
+Wire Wire Line
+ 4150 3050 4150 2900
+Wire Wire Line
+ 4150 2900 4300 2900
+Wire Wire Line
+ 4150 3250 4300 3250
+Wire Wire Line
+ 4300 3250 4300 3350
+Wire Wire Line
+ 4150 3550 4150 3450
+Wire Wire Line
+ 4150 3450 4300 3450
+Wire Wire Line
+ 6700 3050 6450 3050
+$Comp
+L d_or U4
+U 1 1 5CEE4ED7
+P 4900 4100
+F 0 "U4" H 4900 4100 60 0000 C CNN
+F 1 "d_or" H 4900 4200 60 0000 C CNN
+F 2 "" H 4900 4100 60 0000 C CNN
+F 3 "" H 4900 4100 60 0000 C CNN
+ 1 4900 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U5
+U 1 1 5CEE4EDD
+P 4900 4650
+F 0 "U5" H 4900 4650 60 0000 C CNN
+F 1 "d_or" H 4900 4750 60 0000 C CNN
+F 2 "" H 4900 4650 60 0000 C CNN
+F 3 "" H 4900 4650 60 0000 C CNN
+ 1 4900 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 5CEE4EE3
+P 6150 4300
+F 0 "U7" H 6150 4300 60 0000 C CNN
+F 1 "d_nor" H 6200 4400 60 0000 C CNN
+F 2 "" H 6150 4300 60 0000 C CNN
+F 3 "" H 6150 4300 60 0000 C CNN
+ 1 6150 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5350 4050 5550 4050
+Wire Wire Line
+ 5550 4050 5550 4200
+Wire Wire Line
+ 5550 4200 5700 4200
+Wire Wire Line
+ 5350 4600 5550 4600
+Wire Wire Line
+ 5550 4600 5550 4300
+Wire Wire Line
+ 5550 4300 5700 4300
+$Comp
+L PORT U1
+U 9 1 5CEE4EEF
+P 4000 4000
+F 0 "U1" H 4050 4100 30 0000 C CNN
+F 1 "PORT" H 4000 4000 30 0000 C CNN
+F 2 "" H 4000 4000 60 0000 C CNN
+F 3 "" H 4000 4000 60 0000 C CNN
+ 9 4000 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE4EF5
+P 4050 4250
+F 0 "U1" H 4100 4350 30 0000 C CNN
+F 1 "PORT" H 4050 4250 30 0000 C CNN
+F 2 "" H 4050 4250 60 0000 C CNN
+F 3 "" H 4050 4250 60 0000 C CNN
+ 10 4050 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE4EFB
+P 4050 4450
+F 0 "U1" H 4100 4550 30 0000 C CNN
+F 1 "PORT" H 4050 4450 30 0000 C CNN
+F 2 "" H 4050 4450 60 0000 C CNN
+F 3 "" H 4050 4450 60 0000 C CNN
+ 11 4050 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE4F01
+P 4050 4750
+F 0 "U1" H 4100 4850 30 0000 C CNN
+F 1 "PORT" H 4050 4750 30 0000 C CNN
+F 2 "" H 4050 4750 60 0000 C CNN
+F 3 "" H 4050 4750 60 0000 C CNN
+ 12 4050 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CEE4F07
+P 7100 4250
+F 0 "U1" H 7150 4350 30 0000 C CNN
+F 1 "PORT" H 7100 4250 30 0000 C CNN
+F 2 "" H 7100 4250 60 0000 C CNN
+F 3 "" H 7100 4250 60 0000 C CNN
+ 13 7100 4250
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4250 4000 4450 4000
+Wire Wire Line
+ 4300 4250 4300 4100
+Wire Wire Line
+ 4300 4100 4450 4100
+Wire Wire Line
+ 4300 4450 4450 4450
+Wire Wire Line
+ 4450 4450 4450 4550
+Wire Wire Line
+ 4300 4750 4300 4650
+Wire Wire Line
+ 4300 4650 4450 4650
+Wire Wire Line
+ 6850 4250 6600 4250
+$Comp
+L PORT U1
+U 6 1 5CEE51A5
+P 6300 5350
+F 0 "U1" H 6350 5450 30 0000 C CNN
+F 1 "PORT" H 6300 5350 30 0000 C CNN
+F 2 "" H 6300 5350 60 0000 C CNN
+F 3 "" H 6300 5350 60 0000 C CNN
+ 6 6300 5350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CEE522C
+P 6300 5550
+F 0 "U1" H 6350 5650 30 0000 C CNN
+F 1 "PORT" H 6300 5550 30 0000 C CNN
+F 2 "" H 6300 5550 60 0000 C CNN
+F 3 "" H 6300 5550 60 0000 C CNN
+ 7 6300 5550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CEE5276
+P 6300 5800
+F 0 "U1" H 6350 5900 30 0000 C CNN
+F 1 "PORT" H 6300 5800 30 0000 C CNN
+F 2 "" H 6300 5800 60 0000 C CNN
+F 3 "" H 6300 5800 60 0000 C CNN
+ 8 6300 5800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CEE52C5
+P 6300 6000
+F 0 "U1" H 6350 6100 30 0000 C CNN
+F 1 "PORT" H 6300 6000 30 0000 C CNN
+F 2 "" H 6300 6000 60 0000 C CNN
+F 3 "" H 6300 6000 60 0000 C CNN
+ 14 6300 6000
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.sub b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.sub new file mode 100644 index 00000000..522ba7ae --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002.sub @@ -0,0 +1,30 @@ +* Subcircuit 4002
+.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4002
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002_Previous_Values.xml new file mode 100644 index 00000000..75360e5e --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4002_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib new file mode 100644 index 00000000..57f05c24 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib @@ -0,0 +1,140 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.cir b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.cir new file mode 100644 index 00000000..a667c576 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.cir @@ -0,0 +1,42 @@ +* C:\Users\Bhargav\eSim-Workspace\4002_test\4002_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 06:09:49
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U2-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ ? ? ? Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ Net-_U2-Pad2_ ? IC_4002
+U1 Net-_R1-Pad2_ Net-_R2-Pad2_ Net-_R3-Pad2_ Net-_R4-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ adc_bridge_4
+U3 Net-_R10-Pad1_ Net-_R9-Pad1_ Net-_R8-Pad1_ Net-_R7-Pad1_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U3-Pad8_ adc_bridge_4
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ out1 out2 dac_bridge_2
+R5 out1 GND 1k
+R6 out2 GND 1k
+U9 out1 plot_v1
+U8 out2 plot_v1
+U13 v8 plot_v1
+U10 v7 plot_v1
+U11 v6 plot_v1
+U12 v5 plot_v1
+R10 Net-_R10-Pad1_ v8 1k
+R9 Net-_R9-Pad1_ v7 1k
+R8 Net-_R8-Pad1_ v6 1k
+R7 Net-_R7-Pad1_ v5 1k
+v6 v7 GND DC
+v5 v8 GND DC
+v8 v5 GND DC
+v7 v6 GND DC
+U7 v4 plot_v1
+U4 v3 plot_v1
+U6 v2 plot_v1
+U5 v1 plot_v1
+R4 v4 Net-_R4-Pad2_ 1k
+R3 v3 Net-_R3-Pad2_ 1k
+R2 v2 Net-_R2-Pad2_ 1k
+R1 v1 Net-_R1-Pad2_ 1k
+v4 v4 GND DC
+v3 v3 GND DC
+v2 v2 GND DC
+v1 v1 GND DC
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.cir.out b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.cir.out new file mode 100644 index 00000000..2dbfc43b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.cir.out @@ -0,0 +1,63 @@ +* c:\users\bhargav\esim-workspace\4002_test\4002_test.cir
+
+.include 4002.sub
+x1 net-_u2-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ? ? ? net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u2-pad2_ ? 4002
+* u1 net-_r1-pad2_ net-_r2-pad2_ net-_r3-pad2_ net-_r4-pad2_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4
+* u3 net-_r10-pad1_ net-_r9-pad1_ net-_r8-pad1_ net-_r7-pad1_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4
+* u2 net-_u2-pad1_ net-_u2-pad2_ out1 out2 dac_bridge_2
+r5 out1 gnd 1k
+r6 out2 gnd 1k
+* u9 out1 plot_v1
+* u8 out2 plot_v1
+* u13 v8 plot_v1
+* u10 v7 plot_v1
+* u11 v6 plot_v1
+* u12 v5 plot_v1
+r10 net-_r10-pad1_ v8 1k
+r9 net-_r9-pad1_ v7 1k
+r8 net-_r8-pad1_ v6 1k
+r7 net-_r7-pad1_ v5 1k
+v6 v7 gnd dc 0
+v5 v8 gnd dc 0
+v8 v5 gnd dc 0
+v7 v6 gnd dc 5
+* u7 v4 plot_v1
+* u4 v3 plot_v1
+* u6 v2 plot_v1
+* u5 v1 plot_v1
+r4 v4 net-_r4-pad2_ 1k
+r3 v3 net-_r3-pad2_ 1k
+r2 v2 net-_r2-pad2_ 1k
+r1 v1 net-_r1-pad2_ 1k
+v4 v4 gnd dc 0
+v3 v3 gnd dc 0
+v2 v2 gnd dc 0
+v1 v1 gnd dc 0
+a1 [net-_r1-pad2_ net-_r2-pad2_ net-_r3-pad2_ net-_r4-pad2_ ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1
+a2 [net-_r10-pad1_ net-_r9-pad1_ net-_r8-pad1_ net-_r7-pad1_ ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3
+a3 [net-_u2-pad1_ net-_u2-pad2_ ] [out1 out2 ] u2
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u3 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out1)
+plot v(out2)
+plot v(v8)
+plot v(v7)
+plot v(v6)
+plot v(v5)
+plot v(v4)
+plot v(v3)
+plot v(v2)
+plot v(v1)
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro new file mode 100644 index 00000000..43701631 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro @@ -0,0 +1,44 @@ +update=06/01/19 05:45:01
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.proj b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.proj new file mode 100644 index 00000000..e13b6026 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.proj @@ -0,0 +1 @@ +schematicFile 4002_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch new file mode 100644 index 00000000..e07e773f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch @@ -0,0 +1,610 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:4_Input_NOR_Characteristics-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L IC_4002 X1 +U 1 1 5CF1C395 +P 5500 3400 +F 0 "X1" H 5500 3550 60 0000 C CNN +F 1 "IC_4002" H 5500 3400 60 0000 C CNN +F 2 "" H 5550 3250 60 0000 C CNN +F 3 "" H 5550 3250 60 0000 C CNN + 1 5500 3400 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U1 +U 1 1 5CF1C610 +P 4350 3450 +F 0 "U1" H 4350 3450 60 0000 C CNN +F 1 "adc_bridge_4" H 4350 3750 60 0000 C CNN +F 2 "" H 4350 3450 60 0000 C CNN +F 3 "" H 4350 3450 60 0000 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U3 +U 1 1 5CF1C67F +P 6650 3450 +F 0 "U3" H 6650 3450 60 0000 C CNN +F 1 "adc_bridge_4" H 6650 3750 60 0000 C CNN +F 2 "" H 6650 3450 60 0000 C CNN +F 3 "" H 6650 3450 60 0000 C CNN + 1 6650 3450 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_2 U2 +U 1 1 5CF1CADD +P 6200 2350 +F 0 "U2" H 6200 2350 60 0000 C CNN +F 1 "dac_bridge_2" H 6250 2500 60 0000 C CNN +F 2 "" H 6200 2350 60 0000 C CNN +F 3 "" H 6200 2350 60 0000 C CNN + 1 6200 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CF29F39 +P 7000 2350 +F 0 "R5" H 7050 2480 50 0000 C CNN +F 1 "1k" H 7050 2400 50 0000 C CNN +F 2 "" H 7050 2330 30 0000 C CNN +F 3 "" V 7050 2400 30 0000 C CNN + 1 7000 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CF2A627 +P 7000 2450 +F 0 "R6" H 7050 2580 50 0000 C CNN +F 1 "1k" H 7050 2500 50 0000 C CNN +F 2 "" H 7050 2430 30 0000 C CNN +F 3 "" V 7050 2500 30 0000 C CNN + 1 7000 2450 + 1 0 0 -1 +$EndComp +NoConn ~ 5050 3750 +NoConn ~ 5050 3650 +NoConn ~ 5950 3750 +NoConn ~ 5950 3150 +$Comp +L plot_v1 U9 +U 1 1 5CF2F0DA +P 6800 2300 +F 0 "U9" H 6800 2800 60 0000 C CNN +F 1 "plot_v1" H 7000 2650 60 0000 C CNN +F 2 "" H 6800 2300 60 0000 C CNN +F 3 "" H 6800 2300 60 0000 C CNN + 1 6800 2300 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 5CF2FF74 +P 6750 2350 +F 0 "U8" H 6750 2850 60 0000 C CNN +F 1 "plot_v1" H 6950 2700 60 0000 C CNN +F 2 "" H 6750 2350 60 0000 C CNN +F 3 "" H 6750 2350 60 0000 C CNN + 1 6750 2350 + -1 0 0 1 +$EndComp +Text GLabel 6950 2150 2 60 Input ~ 0 +out1 +Text GLabel 6850 2500 2 60 Input ~ 0 +out2 +Wire Wire Line + 3750 3250 3800 3250 +Wire Wire Line + 3750 3350 3800 3350 +Wire Wire Line + 3750 3450 3800 3450 +Wire Wire Line + 3750 3550 3800 3550 +Wire Wire Line + 6100 3350 5950 3350 +Wire Wire Line + 6100 3450 5950 3450 +Wire Wire Line + 6100 3550 5950 3550 +Wire Wire Line + 6100 3650 5950 3650 +Wire Wire Line + 7250 3350 7200 3350 +Wire Wire Line + 7250 3450 7200 3450 +Wire Wire Line + 7250 3550 7200 3550 +Wire Wire Line + 7250 3650 7200 3650 +Wire Wire Line + 8700 4050 8700 2350 +Wire Wire Line + 4900 3250 5050 3250 +Wire Wire Line + 4900 3350 5050 3350 +Wire Wire Line + 4900 3450 5050 3450 +Wire Wire Line + 4900 3550 5050 3550 +Wire Wire Line + 5050 3150 4950 3150 +Wire Wire Line + 4950 3150 4950 2300 +Wire Wire Line + 4950 2300 5750 2300 +Wire Wire Line + 5950 3250 6100 3250 +Wire Wire Line + 6100 3250 6100 3000 +Wire Wire Line + 6100 3000 5150 3000 +Wire Wire Line + 5150 3000 5150 2400 +Wire Wire Line + 5150 2400 5750 2400 +Wire Wire Line + 6900 2300 6750 2300 +Wire Wire Line + 6900 2400 6750 2400 +Wire Wire Line + 7200 2300 7350 2300 +Wire Wire Line + 7350 2300 7350 2400 +Wire Wire Line + 7350 2400 7200 2400 +Wire Wire Line + 8700 2350 7350 2350 +Connection ~ 7350 2350 +Wire Wire Line + 2050 4050 8700 4050 +Wire Wire Line + 6800 2100 6800 2300 +Wire Wire Line + 6750 2450 6750 2550 +Wire Wire Line + 6850 2500 6750 2500 +Connection ~ 6750 2500 +Wire Wire Line + 6950 2150 6800 2150 +Connection ~ 6800 2150 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5CF4D6F1 +P 4750 3950 +F 0 "#FLG01" H 4750 4045 50 0001 C CNN +F 1 "PWR_FLAG" H 4750 4130 50 0000 C CNN +F 2 "" H 4750 3950 50 0000 C CNN +F 3 "" H 4750 3950 50 0000 C CNN + 1 4750 3950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5CF4EA85 +P 4750 4150 +F 0 "#PWR02" H 4750 3900 50 0001 C CNN +F 1 "GND" H 4750 4000 50 0000 C CNN +F 2 "" H 4750 4150 50 0000 C CNN +F 3 "" H 4750 4150 50 0000 C CNN + 1 4750 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4750 3950 4750 4150 +Connection ~ 4750 4050 +Connection ~ 8700 3650 +Wire Wire Line + 8700 3650 8650 3650 +Connection ~ 8700 3550 +Wire Wire Line + 8650 3550 8700 3550 +Connection ~ 8700 3450 +Wire Wire Line + 8650 3450 8700 3450 +Connection ~ 8700 3350 +Wire Wire Line + 8650 3350 8700 3350 +Wire Wire Line + 2050 3550 2050 4050 +Wire Wire Line + 3250 3850 2850 3850 +Connection ~ 7750 3700 +Wire Wire Line + 7800 3700 7750 3700 +Wire Wire Line + 7800 3750 7850 3750 +Wire Wire Line + 7800 3700 7800 3750 +Connection ~ 7700 3550 +Wire Wire Line + 7700 3800 7700 3550 +Wire Wire Line + 7500 3800 7700 3800 +Wire Wire Line + 7900 3300 7700 3300 +Wire Wire Line + 7900 3050 7900 3300 +Connection ~ 7650 3450 +Wire Wire Line + 7650 3200 7650 3450 +Wire Wire Line + 7400 3200 7650 3200 +Wire Wire Line + 7750 3750 7750 3650 +Connection ~ 7600 3550 +Wire Wire Line + 7600 3600 7600 3550 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3400 7600 3450 +Connection ~ 7700 3350 +Wire Wire Line + 7700 3300 7700 3350 +Wire Wire Line + 7750 3650 7550 3650 +Wire Wire Line + 7550 3550 7750 3550 +Wire Wire Line + 7750 3450 7550 3450 +Wire Wire Line + 7750 3350 7550 3350 +Text GLabel 7900 3050 2 60 Input ~ 0 +v5 +Text GLabel 7400 3200 0 60 Input ~ 0 +v6 +Text GLabel 7500 3800 0 60 Input ~ 0 +v7 +Text GLabel 7850 3750 2 60 Input ~ 0 +v8 +$Comp +L plot_v1 U13 +U 1 1 5CF460B3 +P 7750 3550 +F 0 "U13" H 7750 4050 60 0000 C CNN +F 1 "plot_v1" H 7950 3900 60 0000 C CNN +F 2 "" H 7750 3550 60 0000 C CNN +F 3 "" H 7750 3550 60 0000 C CNN + 1 7750 3550 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U10 +U 1 1 5CF46008 +P 7600 3400 +F 0 "U10" H 7600 3900 60 0000 C CNN +F 1 "plot_v1" H 7800 3750 60 0000 C CNN +F 2 "" H 7600 3400 60 0000 C CNN +F 3 "" H 7600 3400 60 0000 C CNN + 1 7600 3400 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 5CF45F98 +P 7600 3600 +F 0 "U11" H 7600 4100 60 0000 C CNN +F 1 "plot_v1" H 7800 3950 60 0000 C CNN +F 2 "" H 7600 3600 60 0000 C CNN +F 3 "" H 7600 3600 60 0000 C CNN + 1 7600 3600 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 5CF45618 +P 7700 3500 +F 0 "U12" H 7700 4000 60 0000 C CNN +F 1 "plot_v1" H 7900 3850 60 0000 C CNN +F 2 "" H 7700 3500 60 0000 C CNN +F 3 "" H 7700 3500 60 0000 C CNN + 1 7700 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CF232CD +P 7350 3700 +F 0 "R10" H 7400 3830 50 0000 C CNN +F 1 "1k" H 7400 3750 50 0000 C CNN +F 2 "" H 7400 3680 30 0000 C CNN +F 3 "" V 7400 3750 30 0000 C CNN + 1 7350 3700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CF232C7 +P 7350 3600 +F 0 "R9" H 7400 3730 50 0000 C CNN +F 1 "1k" H 7400 3650 50 0000 C CNN +F 2 "" H 7400 3580 30 0000 C CNN +F 3 "" V 7400 3650 30 0000 C CNN + 1 7350 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CF232C1 +P 7350 3500 +F 0 "R8" H 7400 3630 50 0000 C CNN +F 1 "1k" H 7400 3550 50 0000 C CNN +F 2 "" H 7400 3480 30 0000 C CNN +F 3 "" V 7400 3550 30 0000 C CNN + 1 7350 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CF232BB +P 7350 3400 +F 0 "R7" H 7400 3530 50 0000 C CNN +F 1 "1k" H 7400 3450 50 0000 C CNN +F 2 "" H 7400 3380 30 0000 C CNN +F 3 "" V 7400 3450 30 0000 C CNN + 1 7350 3400 + 1 0 0 -1 +$EndComp +$Comp +L DC v6 +U 1 1 5CF1E4C8 +P 8200 3550 +F 0 "v6" H 8000 3650 60 0000 C CNN +F 1 "DC" H 8000 3500 60 0000 C CNN +F 2 "R1" H 7900 3550 60 0000 C CNN +F 3 "" H 8200 3550 60 0000 C CNN + 1 8200 3550 + 0 -1 1 0 +$EndComp +$Comp +L DC v5 +U 1 1 5CF1E4C2 +P 8200 3650 +F 0 "v5" H 8000 3750 60 0000 C CNN +F 1 "DC" H 8000 3600 60 0000 C CNN +F 2 "R1" H 7900 3650 60 0000 C CNN +F 3 "" H 8200 3650 60 0000 C CNN + 1 8200 3650 + 0 -1 1 0 +$EndComp +$Comp +L DC v8 +U 1 1 5CF1E4BC +P 8200 3350 +F 0 "v8" H 8000 3450 60 0000 C CNN +F 1 "DC" H 8000 3300 60 0000 C CNN +F 2 "R1" H 7900 3350 60 0000 C CNN +F 3 "" H 8200 3350 60 0000 C CNN + 1 8200 3350 + 0 -1 1 0 +$EndComp +$Comp +L DC v7 +U 1 1 5CF1E4B6 +P 8200 3450 +F 0 "v7" H 8000 3550 60 0000 C CNN +F 1 "DC" H 8000 3400 60 0000 C CNN +F 2 "R1" H 7900 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 1 8200 3450 + 0 -1 1 0 +$EndComp +Connection ~ 3300 3350 +Wire Wire Line + 3300 3150 3300 3350 +Wire Wire Line + 3100 3150 3300 3150 +Connection ~ 3350 3250 +Wire Wire Line + 3350 3100 3350 3250 +Wire Wire Line + 3500 3100 3350 3100 +Connection ~ 3400 3600 +Wire Wire Line + 3500 3600 3400 3600 +Wire Wire Line + 3500 3750 3500 3600 +Connection ~ 3250 3700 +Wire Wire Line + 3050 3700 3250 3700 +Wire Wire Line + 3250 3600 3250 3850 +Connection ~ 3400 3550 +Wire Wire Line + 3400 3550 3400 3650 +Connection ~ 2200 3550 +Wire Wire Line + 3250 3600 3200 3450 +Connection ~ 3250 3350 +Wire Wire Line + 3250 3300 3250 3350 +Connection ~ 3200 3250 +Wire Wire Line + 3200 3200 3200 3250 +Connection ~ 2200 3350 +Wire Wire Line + 2250 3350 2200 3350 +Connection ~ 2200 3450 +Wire Wire Line + 2300 3450 2200 3450 +Wire Wire Line + 2050 3550 2300 3550 +Wire Wire Line + 2200 3250 2200 3550 +Wire Wire Line + 2250 3250 2200 3250 +Wire Wire Line + 3200 3550 3450 3550 +Wire Wire Line + 3200 3450 3450 3450 +Wire Wire Line + 3150 3350 3450 3350 +Wire Wire Line + 3150 3250 3450 3250 +Text GLabel 3500 3750 2 60 Input ~ 0 +v4 +Text GLabel 3050 3700 0 60 Input ~ 0 +v3 +Text GLabel 3100 3150 0 60 Input ~ 0 +v2 +Text GLabel 3500 3100 2 60 Input ~ 0 +v1 +$Comp +L plot_v1 U7 +U 1 1 5CF31477 +P 3400 3450 +F 0 "U7" H 3400 3950 60 0000 C CNN +F 1 "plot_v1" H 3600 3800 60 0000 C CNN +F 2 "" H 3400 3450 60 0000 C CNN +F 3 "" H 3400 3450 60 0000 C CNN + 1 3400 3450 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5CF31400 +P 3050 3850 +F 0 "U4" H 3050 4350 60 0000 C CNN +F 1 "plot_v1" H 3250 4200 60 0000 C CNN +F 2 "" H 3050 3850 60 0000 C CNN +F 3 "" H 3050 3850 60 0000 C CNN + 1 3050 3850 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5CF313A0 +P 3250 3500 +F 0 "U6" H 3250 4000 60 0000 C CNN +F 1 "plot_v1" H 3450 3850 60 0000 C CNN +F 2 "" H 3250 3500 60 0000 C CNN +F 3 "" H 3250 3500 60 0000 C CNN + 1 3250 3500 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5CF303CA +P 3200 3400 +F 0 "U5" H 3200 3900 60 0000 C CNN +F 1 "plot_v1" H 3400 3750 60 0000 C CNN +F 2 "" H 3200 3400 60 0000 C CNN +F 3 "" H 3200 3400 60 0000 C CNN + 1 3200 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CF1FDB5 +P 3550 3600 +F 0 "R4" H 3600 3730 50 0000 C CNN +F 1 "1k" H 3600 3650 50 0000 C CNN +F 2 "" H 3600 3580 30 0000 C CNN +F 3 "" V 3600 3650 30 0000 C CNN + 1 3550 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CF1FD69 +P 3550 3500 +F 0 "R3" H 3600 3630 50 0000 C CNN +F 1 "1k" H 3600 3550 50 0000 C CNN +F 2 "" H 3600 3480 30 0000 C CNN +F 3 "" V 3600 3550 30 0000 C CNN + 1 3550 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CF1FD21 +P 3550 3400 +F 0 "R2" H 3600 3530 50 0000 C CNN +F 1 "1k" H 3600 3450 50 0000 C CNN +F 2 "" H 3600 3380 30 0000 C CNN +F 3 "" V 3600 3450 30 0000 C CNN + 1 3550 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CF1FCC6 +P 3550 3300 +F 0 "R1" H 3600 3430 50 0000 C CNN +F 1 "1k" H 3600 3350 50 0000 C CNN +F 2 "" H 3600 3280 30 0000 C CNN +F 3 "" V 3600 3350 30 0000 C CNN + 1 3550 3300 + 1 0 0 -1 +$EndComp +$Comp +L DC v4 +U 1 1 5CF1D11E +P 2750 3550 +F 0 "v4" H 2550 3650 60 0000 C CNN +F 1 "DC" H 2550 3500 60 0000 C CNN +F 2 "R1" H 2450 3550 60 0000 C CNN +F 3 "" H 2750 3550 60 0000 C CNN + 1 2750 3550 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 5CF1D0EF +P 2750 3450 +F 0 "v3" H 2550 3550 60 0000 C CNN +F 1 "DC" H 2550 3400 60 0000 C CNN +F 2 "R1" H 2450 3450 60 0000 C CNN +F 3 "" H 2750 3450 60 0000 C CNN + 1 2750 3450 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 5CF1D0C3 +P 2700 3350 +F 0 "v2" H 2500 3450 60 0000 C CNN +F 1 "DC" H 2500 3300 60 0000 C CNN +F 2 "R1" H 2400 3350 60 0000 C CNN +F 3 "" H 2700 3350 60 0000 C CNN + 1 2700 3350 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5CF1CE2E +P 2700 3250 +F 0 "v1" H 2500 3350 60 0000 C CNN +F 1 "DC" H 2500 3200 60 0000 C CNN +F 2 "R1" H 2400 3250 60 0000 C CNN +F 3 "" H 2700 3250 60 0000 C CNN + 1 2700 3250 + 0 1 1 0 +$EndComp +Connection ~ 6800 2300 +Wire Wire Line + 6750 2450 6800 2450 +Wire Wire Line + 6800 2450 6800 2400 +Connection ~ 6800 2400 +Text Notes 4550 4900 0 118 Italic 24 +IC 4002 Characteristics +$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics_Previous_Values.xml new file mode 100644 index 00000000..9d4b9450 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4><v7 name="Source type">dc<field1 name="Value">5</field1></v7><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6></source><model><u1 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u1><u3 name="type">adc_bridge<field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter value for in_low (default=1.0)" /></u3><u2 name="type">dac_bridge<field9 name="Enter value for input load (default=1.0e-12)" /><field10 name="Enter value for out_low (default=0.0)" /><field11 name="Enter value for out_high (default=5.0)" /><field12 name="Enter the Rise Time (default=1.0e-9)" /><field13 name="Enter the Fall Time (default=1.0e-9)" /><field14 name="Enter value for out_undef (default=0.5)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/analysis b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028-cache.lib b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028-cache.lib new file mode 100644 index 00000000..4ba19fb8 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.cir b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.cir new file mode 100644 index 00000000..c13da65d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U9 Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor
+U10 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor
+U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor
+U6 Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor
+U7 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor
+U8 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor
+U2 Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter
+U3 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter
+U4 Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter
+U5 Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter
+U15 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and
+U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and
+U17 Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and
+U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and
+U19 Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and
+U20 Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and
+U21 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and
+U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT
+U22 Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.cir.out b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.cir.out new file mode 100644 index 00000000..93e14b93 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.cir.out @@ -0,0 +1,96 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
+
+* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
+* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
+* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
+* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
+* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter
+* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter
+* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter
+* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
+* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
+* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
+* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
+* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
+* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
+* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
+* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
+a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
+a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
+a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
+a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
+a8 net-_u1-pad10_ net-_u11-pad1_ u2
+a9 net-_u1-pad13_ net-_u10-pad2_ u3
+a10 net-_u1-pad12_ net-_u4-pad2_ u4
+a11 net-_u1-pad11_ net-_u5-pad2_ u5
+a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
+a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
+a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
+a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
+a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
+a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
+a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
+a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
+a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.pro b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.pro new file mode 100644 index 00000000..6f7acdde --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:43:40
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.sch b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.sch new file mode 100644 index 00000000..a487c693 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.sch @@ -0,0 +1,628 @@ +EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nor U9
+U 1 1 5CF0FE64
+P 3750 2500
+F 0 "U9" H 3750 2500 60 0000 C CNN
+F 1 "d_nor" H 3800 2600 60 0000 C CNN
+F 2 "" H 3750 2500 60 0000 C CNN
+F 3 "" H 3750 2500 60 0000 C CNN
+ 1 3750 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U10
+U 1 1 5CF0FEA4
+P 3750 3050
+F 0 "U10" H 3750 3050 60 0000 C CNN
+F 1 "d_nor" H 3800 3150 60 0000 C CNN
+F 2 "" H 3750 3050 60 0000 C CNN
+F 3 "" H 3750 3050 60 0000 C CNN
+ 1 3750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U11
+U 1 1 5CF0FECC
+P 3750 3550
+F 0 "U11" H 3750 3550 60 0000 C CNN
+F 1 "d_nor" H 3800 3650 60 0000 C CNN
+F 2 "" H 3750 3550 60 0000 C CNN
+F 3 "" H 3750 3550 60 0000 C CNN
+ 1 3750 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U12
+U 1 1 5CF0FEF5
+P 3750 4150
+F 0 "U12" H 3750 4150 60 0000 C CNN
+F 1 "d_nor" H 3800 4250 60 0000 C CNN
+F 2 "" H 3750 4150 60 0000 C CNN
+F 3 "" H 3750 4150 60 0000 C CNN
+ 1 3750 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 5CF0FF23
+P 3700 4750
+F 0 "U6" H 3700 4750 60 0000 C CNN
+F 1 "d_nor" H 3750 4850 60 0000 C CNN
+F 2 "" H 3700 4750 60 0000 C CNN
+F 3 "" H 3700 4750 60 0000 C CNN
+ 1 3700 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 5CF0FF59
+P 3700 5250
+F 0 "U7" H 3700 5250 60 0000 C CNN
+F 1 "d_nor" H 3750 5350 60 0000 C CNN
+F 2 "" H 3700 5250 60 0000 C CNN
+F 3 "" H 3700 5250 60 0000 C CNN
+ 1 3700 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U8
+U 1 1 5CF0FFA9
+P 3750 2000
+F 0 "U8" H 3750 2000 60 0000 C CNN
+F 1 "d_nor" H 3800 2100 60 0000 C CNN
+F 2 "" H 3750 2000 60 0000 C CNN
+F 3 "" H 3750 2000 60 0000 C CNN
+ 1 3750 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 5CF1003A
+P 2150 2400
+F 0 "U2" H 2150 2300 60 0000 C CNN
+F 1 "d_inverter" H 2150 2550 60 0000 C CNN
+F 2 "" H 2200 2350 60 0000 C CNN
+F 3 "" H 2200 2350 60 0000 C CNN
+ 1 2150 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 5CF1007F
+P 2150 3300
+F 0 "U3" H 2150 3200 60 0000 C CNN
+F 1 "d_inverter" H 2150 3450 60 0000 C CNN
+F 2 "" H 2200 3250 60 0000 C CNN
+F 3 "" H 2200 3250 60 0000 C CNN
+ 1 2150 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 5CF100CC
+P 2150 4150
+F 0 "U4" H 2150 4050 60 0000 C CNN
+F 1 "d_inverter" H 2150 4300 60 0000 C CNN
+F 2 "" H 2200 4100 60 0000 C CNN
+F 3 "" H 2200 4100 60 0000 C CNN
+ 1 2150 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 5CF10114
+P 2150 4900
+F 0 "U5" H 2150 4800 60 0000 C CNN
+F 1 "d_inverter" H 2150 5050 60 0000 C CNN
+F 2 "" H 2200 4850 60 0000 C CNN
+F 3 "" H 2200 4850 60 0000 C CNN
+ 1 2150 4900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1400 2400 1850 2400
+Wire Wire Line
+ 1400 3300 1850 3300
+Wire Wire Line
+ 1450 4150 1850 4150
+Wire Wire Line
+ 1450 4900 1850 4900
+Wire Wire Line
+ 2450 4900 2500 4900
+Wire Wire Line
+ 2500 4900 2500 5250
+Wire Wire Line
+ 2500 5250 3250 5250
+Wire Wire Line
+ 2450 4150 2550 4150
+Wire Wire Line
+ 2550 4150 2550 4650
+Wire Wire Line
+ 2550 4650 3250 4650
+Wire Wire Line
+ 2450 3300 2550 3300
+Wire Wire Line
+ 2550 3300 2550 3550
+Wire Wire Line
+ 2550 3550 3300 3550
+Wire Wire Line
+ 2450 2400 2450 2500
+Wire Wire Line
+ 2450 2500 3300 2500
+Wire Wire Line
+ 2800 2500 2800 3450
+Wire Wire Line
+ 2800 3450 3300 3450
+Connection ~ 2800 2500
+Wire Wire Line
+ 1650 2400 1650 1900
+Wire Wire Line
+ 1650 1900 3300 1900
+Connection ~ 1650 2400
+Wire Wire Line
+ 3300 2000 2850 2000
+Wire Wire Line
+ 2850 2000 2850 3000
+Wire Wire Line
+ 2850 3000 1650 3000
+Wire Wire Line
+ 1650 3000 1650 3300
+Connection ~ 1650 3300
+Wire Wire Line
+ 2850 2400 3300 2400
+Connection ~ 2850 2400
+Wire Wire Line
+ 2950 1900 2950 2950
+Wire Wire Line
+ 2950 2950 3300 2950
+Connection ~ 2950 1900
+Wire Wire Line
+ 3100 3550 3100 3050
+Wire Wire Line
+ 3100 3050 3300 3050
+Connection ~ 3100 3550
+Wire Wire Line
+ 1650 3900 1650 4150
+Wire Wire Line
+ 1650 3900 3050 3900
+Wire Wire Line
+ 3050 3900 3050 5150
+Wire Wire Line
+ 3050 4050 3300 4050
+Connection ~ 1650 4150
+Wire Wire Line
+ 1750 4900 1750 5150
+Wire Wire Line
+ 1750 5150 2750 5150
+Connection ~ 1750 4900
+Wire Wire Line
+ 2750 5150 2750 4150
+Wire Wire Line
+ 2750 4150 3300 4150
+Wire Wire Line
+ 2750 4750 3250 4750
+Connection ~ 2750 4750
+Wire Wire Line
+ 3050 5150 3250 5150
+Connection ~ 3050 4050
+$Comp
+L d_and U15
+U 1 1 5CF106B1
+P 6600 1850
+F 0 "U15" H 6600 1850 60 0000 C CNN
+F 1 "d_and" H 6650 1950 60 0000 C CNN
+F 2 "" H 6600 1850 60 0000 C CNN
+F 3 "" H 6600 1850 60 0000 C CNN
+ 1 6600 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U16
+U 1 1 5CF10756
+P 6600 2350
+F 0 "U16" H 6600 2350 60 0000 C CNN
+F 1 "d_and" H 6650 2450 60 0000 C CNN
+F 2 "" H 6600 2350 60 0000 C CNN
+F 3 "" H 6600 2350 60 0000 C CNN
+ 1 6600 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U17
+U 1 1 5CF107A1
+P 6600 2800
+F 0 "U17" H 6600 2800 60 0000 C CNN
+F 1 "d_and" H 6650 2900 60 0000 C CNN
+F 2 "" H 6600 2800 60 0000 C CNN
+F 3 "" H 6600 2800 60 0000 C CNN
+ 1 6600 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U18
+U 1 1 5CF107E9
+P 6600 3200
+F 0 "U18" H 6600 3200 60 0000 C CNN
+F 1 "d_and" H 6650 3300 60 0000 C CNN
+F 2 "" H 6600 3200 60 0000 C CNN
+F 3 "" H 6600 3200 60 0000 C CNN
+ 1 6600 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U19
+U 1 1 5CF10834
+P 6600 3650
+F 0 "U19" H 6600 3650 60 0000 C CNN
+F 1 "d_and" H 6650 3750 60 0000 C CNN
+F 2 "" H 6600 3650 60 0000 C CNN
+F 3 "" H 6600 3650 60 0000 C CNN
+ 1 6600 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U20
+U 1 1 5CF1087E
+P 6600 4050
+F 0 "U20" H 6600 4050 60 0000 C CNN
+F 1 "d_and" H 6650 4150 60 0000 C CNN
+F 2 "" H 6600 4050 60 0000 C CNN
+F 3 "" H 6600 4050 60 0000 C CNN
+ 1 6600 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U21
+U 1 1 5CF108F9
+P 6600 4450
+F 0 "U21" H 6600 4450 60 0000 C CNN
+F 1 "d_and" H 6650 4550 60 0000 C CNN
+F 2 "" H 6600 4450 60 0000 C CNN
+F 3 "" H 6600 4450 60 0000 C CNN
+ 1 6600 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 5CF1094D
+P 6550 4900
+F 0 "U13" H 6550 4900 60 0000 C CNN
+F 1 "d_and" H 6600 5000 60 0000 C CNN
+F 2 "" H 6550 4900 60 0000 C CNN
+F 3 "" H 6550 4900 60 0000 C CNN
+ 1 6550 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 5CF109A6
+P 6550 5350
+F 0 "U14" H 6550 5350 60 0000 C CNN
+F 1 "d_and" H 6600 5450 60 0000 C CNN
+F 2 "" H 6550 5350 60 0000 C CNN
+F 3 "" H 6550 5350 60 0000 C CNN
+ 1 6550 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CF11966
+P 1150 2400
+F 0 "U1" H 1200 2500 30 0000 C CNN
+F 1 "PORT" H 1150 2400 30 0000 C CNN
+F 2 "" H 1150 2400 60 0000 C CNN
+F 3 "" H 1150 2400 60 0000 C CNN
+ 10 1150 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CF119D4
+P 1150 3300
+F 0 "U1" H 1200 3400 30 0000 C CNN
+F 1 "PORT" H 1150 3300 30 0000 C CNN
+F 2 "" H 1150 3300 60 0000 C CNN
+F 3 "" H 1150 3300 60 0000 C CNN
+ 13 1150 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CF11AFC
+P 1200 4150
+F 0 "U1" H 1250 4250 30 0000 C CNN
+F 1 "PORT" H 1200 4150 30 0000 C CNN
+F 2 "" H 1200 4150 60 0000 C CNN
+F 3 "" H 1200 4150 60 0000 C CNN
+ 12 1200 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CF11B6B
+P 1200 4900
+F 0 "U1" H 1250 5000 30 0000 C CNN
+F 1 "PORT" H 1200 4900 30 0000 C CNN
+F 2 "" H 1200 4900 60 0000 C CNN
+F 3 "" H 1200 4900 60 0000 C CNN
+ 11 1200 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CF11BDB
+P 8000 1800
+F 0 "U1" H 8050 1900 30 0000 C CNN
+F 1 "PORT" H 8000 1800 30 0000 C CNN
+F 2 "" H 8000 1800 60 0000 C CNN
+F 3 "" H 8000 1800 60 0000 C CNN
+ 3 8000 1800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CF11F59
+P 8000 2300
+F 0 "U1" H 8050 2400 30 0000 C CNN
+F 1 "PORT" H 8000 2300 30 0000 C CNN
+F 2 "" H 8000 2300 60 0000 C CNN
+F 3 "" H 8000 2300 60 0000 C CNN
+ 14 8000 2300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CF11FC5
+P 8000 2750
+F 0 "U1" H 8050 2850 30 0000 C CNN
+F 1 "PORT" H 8000 2750 30 0000 C CNN
+F 2 "" H 8000 2750 60 0000 C CNN
+F 3 "" H 8000 2750 60 0000 C CNN
+ 2 8000 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 5CF1204F
+P 8000 3150
+F 0 "U1" H 8050 3250 30 0000 C CNN
+F 1 "PORT" H 8000 3150 30 0000 C CNN
+F 2 "" H 8000 3150 60 0000 C CNN
+F 3 "" H 8000 3150 60 0000 C CNN
+ 15 8000 3150
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CF120C5
+P 7950 3600
+F 0 "U1" H 8000 3700 30 0000 C CNN
+F 1 "PORT" H 7950 3600 30 0000 C CNN
+F 2 "" H 7950 3600 60 0000 C CNN
+F 3 "" H 7950 3600 60 0000 C CNN
+ 1 7950 3600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CF1213C
+P 7950 4000
+F 0 "U1" H 8000 4100 30 0000 C CNN
+F 1 "PORT" H 7950 4000 30 0000 C CNN
+F 2 "" H 7950 4000 60 0000 C CNN
+F 3 "" H 7950 4000 60 0000 C CNN
+ 6 7950 4000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CF121B2
+P 7900 4400
+F 0 "U1" H 7950 4500 30 0000 C CNN
+F 1 "PORT" H 7900 4400 30 0000 C CNN
+F 2 "" H 7900 4400 60 0000 C CNN
+F 3 "" H 7900 4400 60 0000 C CNN
+ 7 7900 4400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CF1223D
+P 7900 4850
+F 0 "U1" H 7950 4950 30 0000 C CNN
+F 1 "PORT" H 7900 4850 30 0000 C CNN
+F 2 "" H 7900 4850 60 0000 C CNN
+F 3 "" H 7900 4850 60 0000 C CNN
+ 4 7900 4850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CF1237B
+P 7900 5300
+F 0 "U1" H 7950 5400 30 0000 C CNN
+F 1 "PORT" H 7900 5300 30 0000 C CNN
+F 2 "" H 7900 5300 60 0000 C CNN
+F 3 "" H 7900 5300 60 0000 C CNN
+ 9 7900 5300
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7750 1800 7050 1800
+Wire Wire Line
+ 7050 2300 7750 2300
+Wire Wire Line
+ 7750 2750 7050 2750
+Wire Wire Line
+ 7050 3150 7750 3150
+Wire Wire Line
+ 7700 3600 7050 3600
+Wire Wire Line
+ 7050 4000 7700 4000
+Wire Wire Line
+ 7650 4400 7050 4400
+Wire Wire Line
+ 7000 4850 7650 4850
+Wire Wire Line
+ 7650 5300 7000 5300
+$Comp
+L d_and U22
+U 1 1 5CF14904
+P 6550 5800
+F 0 "U22" H 6550 5800 60 0000 C CNN
+F 1 "d_and" H 6600 5900 60 0000 C CNN
+F 2 "" H 6550 5800 60 0000 C CNN
+F 3 "" H 6550 5800 60 0000 C CNN
+ 1 6550 5800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4200 1950 4600 1950
+Wire Wire Line
+ 4600 1750 4600 5250
+Wire Wire Line
+ 4600 1750 6150 1750
+Wire Wire Line
+ 4600 5250 6100 5250
+Connection ~ 4600 1950
+Wire Wire Line
+ 6100 5800 5900 5800
+Wire Wire Line
+ 5900 5800 5900 5350
+Wire Wire Line
+ 5900 5350 6100 5350
+Wire Wire Line
+ 5850 4900 6100 4900
+Wire Wire Line
+ 5850 3650 5850 4900
+Wire Wire Line
+ 5850 4450 6150 4450
+Wire Wire Line
+ 5850 4050 6150 4050
+Connection ~ 5850 4450
+Wire Wire Line
+ 5850 3650 6150 3650
+Connection ~ 5850 4050
+Wire Wire Line
+ 5050 3200 6150 3200
+Wire Wire Line
+ 5850 1850 5850 3200
+Wire Wire Line
+ 5850 2800 6150 2800
+Wire Wire Line
+ 5850 2350 6150 2350
+Connection ~ 5850 2800
+Wire Wire Line
+ 5850 1850 6150 1850
+Connection ~ 5850 2350
+Wire Wire Line
+ 4200 2450 4700 2450
+Wire Wire Line
+ 4700 2250 4700 5700
+Wire Wire Line
+ 4700 2250 6150 2250
+Wire Wire Line
+ 4200 3000 4800 3000
+Wire Wire Line
+ 4800 2700 4800 4350
+Wire Wire Line
+ 4800 2700 6150 2700
+Wire Wire Line
+ 4700 5700 6100 5700
+Connection ~ 4700 2450
+Wire Wire Line
+ 6150 3550 4600 3550
+Connection ~ 4600 3550
+Wire Wire Line
+ 6150 3950 4700 3950
+Connection ~ 4700 3950
+Wire Wire Line
+ 4800 4350 6150 4350
+Connection ~ 4800 3000
+Wire Wire Line
+ 4200 3500 4900 3500
+Wire Wire Line
+ 4900 3100 4900 4800
+Wire Wire Line
+ 4900 3100 6150 3100
+Wire Wire Line
+ 4900 4800 6100 4800
+Connection ~ 4900 3500
+Wire Wire Line
+ 4200 4100 5050 4100
+Wire Wire Line
+ 5050 4100 5050 3200
+Connection ~ 5850 3200
+Wire Wire Line
+ 4150 4700 5850 4700
+Connection ~ 5850 4700
+Wire Wire Line
+ 4150 5200 4500 5200
+Wire Wire Line
+ 4500 5200 4500 5550
+Wire Wire Line
+ 4500 5550 5900 5550
+Connection ~ 5900 5550
+$Comp
+L PORT U1
+U 5 1 5CF1563E
+P 7950 5750
+F 0 "U1" H 8000 5850 30 0000 C CNN
+F 1 "PORT" H 7950 5750 30 0000 C CNN
+F 2 "" H 7950 5750 60 0000 C CNN
+F 3 "" H 7950 5750 60 0000 C CNN
+ 5 7950 5750
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7700 5750 7000 5750
+$Comp
+L PORT U1
+U 8 1 5CF15953
+P 9550 4800
+F 0 "U1" H 9600 4900 30 0000 C CNN
+F 1 "PORT" H 9550 4800 30 0000 C CNN
+F 2 "" H 9550 4800 60 0000 C CNN
+F 3 "" H 9550 4800 60 0000 C CNN
+ 8 9550 4800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 5CF15A07
+P 9550 5250
+F 0 "U1" H 9600 5350 30 0000 C CNN
+F 1 "PORT" H 9550 5250 30 0000 C CNN
+F 2 "" H 9550 5250 60 0000 C CNN
+F 3 "" H 9550 5250 60 0000 C CNN
+ 16 9550 5250
+ -1 0 0 1
+$EndComp
+NoConn ~ 9300 4800
+NoConn ~ 9300 5250
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.sub b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.sub new file mode 100644 index 00000000..5f9f3cf8 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028.sub @@ -0,0 +1,90 @@ +* Subcircuit 4028
+.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
+* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
+* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
+* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
+* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
+* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter
+* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter
+* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter
+* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
+* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
+* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
+* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
+* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
+* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
+* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
+* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
+a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
+a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
+a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
+a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
+a8 net-_u1-pad10_ net-_u11-pad1_ u2
+a9 net-_u1-pad13_ net-_u10-pad2_ u3
+a10 net-_u1-pad12_ net-_u4-pad2_ u4
+a11 net-_u1-pad11_ net-_u5-pad2_ u5
+a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
+a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
+a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
+a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
+a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
+a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
+a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
+a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
+a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4028
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028_Previous_Values.xml new file mode 100644 index 00000000..189fb200 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/4028_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib new file mode 100644 index 00000000..e21eb0f8 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib @@ -0,0 +1,152 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4028 +# +DEF 4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.cir b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.cir new file mode 100644 index 00000000..66fe8e03 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim-Workspace\4028_test\4028_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 16:27:32
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U11-Pad5_ Net-_U11-Pad3_ Net-_U11-Pad1_ Net-_U11-Pad8_ Net-_U12-Pad2_ Net-_U11-Pad6_ Net-_U11-Pad7_ ? Net-_U12-Pad1_ Net-_U13-Pad5_ Net-_U13-Pad8_ Net-_U13-Pad7_ Net-_U13-Pad6_ Net-_U11-Pad2_ Net-_U11-Pad4_ ? 4028
+U13 a0 a1 a2 a3 Net-_U13-Pad5_ Net-_U13-Pad6_ Net-_U13-Pad7_ Net-_U13-Pad8_ adc_bridge_4
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ q0 q1 q2 q3 q4 q5 q6 q7 dac_bridge_8
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ q8 q9 dac_bridge_2
+v2 a1 GND DC
+v1 a0 GND DC
+v3 a2 GND DC
+v4 a3 GND DC
+U2 q1 plot_v1
+U3 q2 plot_v1
+U4 q3 plot_v1
+U5 q4 plot_v1
+U6 q5 plot_v1
+U7 q6 plot_v1
+U8 q7 plot_v1
+U9 q8 plot_v1
+U10 q9 plot_v1
+U1 q0 plot_v1
+U16 a1 plot_v1
+U15 a0 plot_v1
+U14 a3 plot_v1
+U17 a2 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.cir.out b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.cir.out new file mode 100644 index 00000000..567621cf --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.cir.out @@ -0,0 +1,57 @@ +* c:\users\malli\esim-workspace\4028_test\4028_test.cir + +.include 4028.sub +x1 net-_u11-pad5_ net-_u11-pad3_ net-_u11-pad1_ net-_u11-pad8_ net-_u12-pad2_ net-_u11-pad6_ net-_u11-pad7_ ? net-_u12-pad1_ net-_u13-pad5_ net-_u13-pad8_ net-_u13-pad7_ net-_u13-pad6_ net-_u11-pad2_ net-_u11-pad4_ ? 4028 +* u13 a0 a1 a2 a3 net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ adc_bridge_4 +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ q0 q1 q2 q3 q4 q5 q6 q7 dac_bridge_8 +* u12 net-_u12-pad1_ net-_u12-pad2_ q8 q9 dac_bridge_2 +v2 a1 gnd dc 5 +v1 a0 gnd dc 0 +v3 a2 gnd dc 0 +v4 a3 gnd dc 0 +* u2 q1 plot_v1 +* u3 q2 plot_v1 +* u4 q3 plot_v1 +* u5 q4 plot_v1 +* u6 q5 plot_v1 +* u7 q6 plot_v1 +* u8 q7 plot_v1 +* u9 q8 plot_v1 +* u10 q9 plot_v1 +* u1 q0 plot_v1 +* u16 a1 plot_v1 +* u15 a0 plot_v1 +* u14 a3 plot_v1 +* u17 a2 plot_v1 +a1 [a0 a1 a2 a3 ] [net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ ] u13 +a2 [net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ ] [q0 q1 q2 q3 q4 q5 q6 q7 ] u11 +a3 [net-_u12-pad1_ net-_u12-pad2_ ] [q8 q9 ] u12 +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u13 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u11 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(q1) +plot v(q2) +plot v(q3) +plot v(q4) +plot v(q5) +plot v(q6) +plot v(q7) +plot v(q8) +plot v(q9) +plot v(q0) +plot v(a1) +plot v(a0) +plot v(a3) +plot v(a2) +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro new file mode 100644 index 00000000..dc708582 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro @@ -0,0 +1,44 @@ +update=06/01/19 16:07:13
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.proj b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.proj new file mode 100644 index 00000000..fa2ce0cd --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.proj @@ -0,0 +1 @@ +schematicFile 4028_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch new file mode 100644 index 00000000..e4c093fd --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch @@ -0,0 +1,554 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:BCDToDecimalDecoder-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4028 X1 +U 1 1 5CF25569 +P 5600 4300 +F 0 "X1" H 5600 4200 60 0000 C CNN +F 1 "4028" H 5600 4350 60 0000 C CNN +F 2 "" H 5600 4300 60 0000 C CNN +F 3 "" H 5600 4300 60 0000 C CNN + 1 5600 4300 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U13 +U 1 1 5CF25781 +P 7300 4350 +F 0 "U13" H 7300 4350 60 0000 C CNN +F 1 "adc_bridge_4" H 7300 4650 60 0000 C CNN +F 2 "" H 7300 4350 60 0000 C CNN +F 3 "" H 7300 4350 60 0000 C CNN + 1 7300 4350 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_8 U11 +U 1 1 5CF257F0 +P 3750 3950 +F 0 "U11" H 3750 3950 60 0000 C CNN +F 1 "dac_bridge_8" H 3750 4100 60 0000 C CNN +F 2 "" H 3750 3950 60 0000 C CNN +F 3 "" H 3750 3950 60 0000 C CNN + 1 3750 3950 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U12 +U 1 1 5CF258CD +P 3800 5050 +F 0 "U12" H 3800 5050 60 0000 C CNN +F 1 "dac_bridge_2" H 3850 5200 60 0000 C CNN +F 2 "" H 3800 5050 60 0000 C CNN +F 3 "" H 3800 5050 60 0000 C CNN + 1 3800 5050 + -1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 5CF25946 +P 9400 3950 +F 0 "v2" H 9200 4050 60 0000 C CNN +F 1 "DC" H 9200 3900 60 0000 C CNN +F 2 "R1" H 9100 3950 60 0000 C CNN +F 3 "" H 9400 3950 60 0000 C CNN + 1 9400 3950 + 0 -1 -1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5CF259A4 +P 9400 3400 +F 0 "v1" H 9200 3500 60 0000 C CNN +F 1 "DC" H 9200 3350 60 0000 C CNN +F 2 "R1" H 9100 3400 60 0000 C CNN +F 3 "" H 9400 3400 60 0000 C CNN + 1 9400 3400 + 0 -1 -1 0 +$EndComp +$Comp +L DC v3 +U 1 1 5CF259F8 +P 9400 4500 +F 0 "v3" H 9200 4600 60 0000 C CNN +F 1 "DC" H 9200 4450 60 0000 C CNN +F 2 "R1" H 9100 4500 60 0000 C CNN +F 3 "" H 9400 4500 60 0000 C CNN + 1 9400 4500 + 0 -1 -1 0 +$EndComp +$Comp +L DC v4 +U 1 1 5CF25A37 +P 9450 5000 +F 0 "v4" H 9250 5100 60 0000 C CNN +F 1 "DC" H 9250 4950 60 0000 C CNN +F 2 "R1" H 9150 5000 60 0000 C CNN +F 3 "" H 9450 5000 60 0000 C CNN + 1 9450 5000 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 5CF25C11 +P 10200 4450 +F 0 "#PWR01" H 10200 4200 50 0001 C CNN +F 1 "eSim_GND" H 10200 4300 50 0000 C CNN +F 2 "" H 10200 4450 50 0001 C CNN +F 3 "" H 10200 4450 50 0001 C CNN + 1 10200 4450 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5CF25C75 +P 10200 4100 +F 0 "#FLG02" H 10200 4195 50 0001 C CNN +F 1 "PWR_FLAG" H 10200 4280 50 0000 C CNN +F 2 "" H 10200 4100 50 0000 C CNN +F 3 "" H 10200 4100 50 0000 C CNN + 1 10200 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8950 3400 8500 3400 +Wire Wire Line + 8500 3400 8500 4150 +Wire Wire Line + 8500 4150 7850 4150 +Wire Wire Line + 8600 4250 7850 4250 +Wire Wire Line + 8600 3050 8600 4250 +Wire Wire Line + 8600 3950 8950 3950 +Wire Wire Line + 8950 4500 8500 4500 +Wire Wire Line + 8500 4500 8500 4350 +Wire Wire Line + 8500 4350 7850 4350 +Wire Wire Line + 7850 4450 8200 4450 +Wire Wire Line + 8200 4450 8200 5000 +Wire Wire Line + 8200 5000 9000 5000 +Wire Wire Line + 9900 3400 9900 5000 +Wire Wire Line + 9900 3400 9850 3400 +Wire Wire Line + 9850 3950 9900 3950 +Connection ~ 9900 3950 +Wire Wire Line + 9850 4500 9900 4500 +Connection ~ 9900 4500 +Wire Wire Line + 9900 4200 10200 4200 +Wire Wire Line + 10200 4100 10200 4450 +Connection ~ 9900 4200 +Connection ~ 10200 4200 +Wire Wire Line + 5100 4150 4750 4150 +Wire Wire Line + 4750 4150 4750 3900 +Wire Wire Line + 4750 3900 4350 3900 +Wire Wire Line + 6100 4150 6200 4150 +Wire Wire Line + 6200 4150 6200 3700 +Wire Wire Line + 6200 3700 4400 3700 +Wire Wire Line + 4400 3700 4400 4000 +Wire Wire Line + 4400 4000 4350 4000 +Wire Wire Line + 4350 4050 5100 4050 +Wire Wire Line + 4350 4050 4350 4100 +Wire Wire Line + 6100 4050 6250 4050 +Wire Wire Line + 6250 4050 6250 3650 +Wire Wire Line + 6250 3650 4450 3650 +Wire Wire Line + 4450 3650 4450 4200 +Wire Wire Line + 4450 4200 4350 4200 +Wire Wire Line + 5100 3950 4500 3950 +Wire Wire Line + 4500 3950 4500 4300 +Wire Wire Line + 4500 4300 4350 4300 +Wire Wire Line + 5100 4450 4500 4450 +Wire Wire Line + 4500 4450 4500 4400 +Wire Wire Line + 4500 4400 4350 4400 +Wire Wire Line + 5100 4550 4450 4550 +Wire Wire Line + 4450 4550 4450 4500 +Wire Wire Line + 4450 4500 4350 4500 +Wire Wire Line + 4550 4250 5100 4250 +Wire Wire Line + 4550 4250 4550 4600 +Wire Wire Line + 4550 4600 4350 4600 +Wire Wire Line + 6100 4650 6150 4650 +Wire Wire Line + 6150 4650 6150 5000 +Wire Wire Line + 6150 5000 4250 5000 +Wire Wire Line + 4250 5100 4650 5100 +Wire Wire Line + 4650 5100 4650 4350 +Wire Wire Line + 4650 4350 5100 4350 +Wire Wire Line + 6100 4550 6350 4550 +Wire Wire Line + 6350 4550 6350 4150 +Wire Wire Line + 6350 4150 6750 4150 +Wire Wire Line + 6100 4250 6750 4250 +Wire Wire Line + 6100 4350 6750 4350 +Wire Wire Line + 6750 4450 6100 4450 +$Comp +L plot_v1 U2 +U 1 1 5CF261D1 +P 1700 2550 +F 0 "U2" H 1700 3050 60 0000 C CNN +F 1 "plot_v1" H 1900 2900 60 0000 C CNN +F 2 "" H 1700 2550 60 0000 C CNN +F 3 "" H 1700 2550 60 0000 C CNN + 1 1700 2550 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5CF262A9 +P 1700 3050 +F 0 "U3" H 1700 3550 60 0000 C CNN +F 1 "plot_v1" H 1900 3400 60 0000 C CNN +F 2 "" H 1700 3050 60 0000 C CNN +F 3 "" H 1700 3050 60 0000 C CNN + 1 1700 3050 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5CF262EF +P 1700 3450 +F 0 "U4" H 1700 3950 60 0000 C CNN +F 1 "plot_v1" H 1900 3800 60 0000 C CNN +F 2 "" H 1700 3450 60 0000 C CNN +F 3 "" H 1700 3450 60 0000 C CNN + 1 1700 3450 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5CF2632C +P 1700 3850 +F 0 "U5" H 1700 4350 60 0000 C CNN +F 1 "plot_v1" H 1900 4200 60 0000 C CNN +F 2 "" H 1700 3850 60 0000 C CNN +F 3 "" H 1700 3850 60 0000 C CNN + 1 1700 3850 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5CF26370 +P 1700 4250 +F 0 "U6" H 1700 4750 60 0000 C CNN +F 1 "plot_v1" H 1900 4600 60 0000 C CNN +F 2 "" H 1700 4250 60 0000 C CNN +F 3 "" H 1700 4250 60 0000 C CNN + 1 1700 4250 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 5CF263B7 +P 1700 4650 +F 0 "U7" H 1700 5150 60 0000 C CNN +F 1 "plot_v1" H 1900 5000 60 0000 C CNN +F 2 "" H 1700 4650 60 0000 C CNN +F 3 "" H 1700 4650 60 0000 C CNN + 1 1700 4650 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 5CF263FD +P 1700 5050 +F 0 "U8" H 1700 5550 60 0000 C CNN +F 1 "plot_v1" H 1900 5400 60 0000 C CNN +F 2 "" H 1700 5050 60 0000 C CNN +F 3 "" H 1700 5050 60 0000 C CNN + 1 1700 5050 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U9 +U 1 1 5CF26446 +P 1700 5500 +F 0 "U9" H 1700 6000 60 0000 C CNN +F 1 "plot_v1" H 1900 5850 60 0000 C CNN +F 2 "" H 1700 5500 60 0000 C CNN +F 3 "" H 1700 5500 60 0000 C CNN + 1 1700 5500 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U10 +U 1 1 5CF2649A +P 1700 5900 +F 0 "U10" H 1700 6400 60 0000 C CNN +F 1 "plot_v1" H 1900 6250 60 0000 C CNN +F 2 "" H 1700 5900 60 0000 C CNN +F 3 "" H 1700 5900 60 0000 C CNN + 1 1700 5900 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 5CF26545 +P 1700 2100 +F 0 "U1" H 1700 2600 60 0000 C CNN +F 1 "plot_v1" H 1900 2450 60 0000 C CNN +F 2 "" H 1700 2100 60 0000 C CNN +F 3 "" H 1700 2100 60 0000 C CNN + 1 1700 2100 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3200 3900 2900 3900 +Wire Wire Line + 2900 3900 2900 2100 +Wire Wire Line + 2900 2100 1500 2100 +Wire Wire Line + 1500 2550 2850 2550 +Wire Wire Line + 2850 2550 2850 4000 +Wire Wire Line + 2850 4000 3200 4000 +Wire Wire Line + 3200 4100 2700 4100 +Wire Wire Line + 2700 4100 2700 3050 +Wire Wire Line + 2700 3050 1500 3050 +Wire Wire Line + 1500 3450 2650 3450 +Wire Wire Line + 2650 3450 2650 4200 +Wire Wire Line + 2650 4200 3200 4200 +Wire Wire Line + 3200 4300 2600 4300 +Wire Wire Line + 2600 4300 2600 3850 +Wire Wire Line + 2600 3850 1500 3850 +Wire Wire Line + 1500 4250 2550 4250 +Wire Wire Line + 2550 4250 2550 4400 +Wire Wire Line + 2550 4400 3200 4400 +Wire Wire Line + 2450 4500 3200 4500 +Wire Wire Line + 2450 4500 2450 4650 +Wire Wire Line + 2450 4650 1500 4650 +Wire Wire Line + 1500 5050 2600 5050 +Wire Wire Line + 2600 5050 2600 4600 +Wire Wire Line + 2600 4600 3200 4600 +Wire Wire Line + 3250 5000 2650 5000 +Wire Wire Line + 2650 5000 2650 5500 +Wire Wire Line + 2650 5500 1500 5500 +Wire Wire Line + 3250 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5900 +Wire Wire Line + 2700 5900 1500 5900 +$Comp +L plot_v1 U16 +U 1 1 5CF26B3C +P 8600 3250 +F 0 "U16" H 8600 3750 60 0000 C CNN +F 1 "plot_v1" H 8800 3600 60 0000 C CNN +F 2 "" H 8600 3250 60 0000 C CNN +F 3 "" H 8600 3250 60 0000 C CNN + 1 8600 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U15 +U 1 1 5CF26C0A +P 8250 3750 +F 0 "U15" H 8250 4250 60 0000 C CNN +F 1 "plot_v1" H 8450 4100 60 0000 C CNN +F 2 "" H 8250 3750 60 0000 C CNN +F 3 "" H 8250 3750 60 0000 C CNN + 1 8250 3750 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U14 +U 1 1 5CF26C90 +P 8150 4900 +F 0 "U14" H 8150 5400 60 0000 C CNN +F 1 "plot_v1" H 8350 5250 60 0000 C CNN +F 2 "" H 8150 4900 60 0000 C CNN +F 3 "" H 8150 4900 60 0000 C CNN + 1 8150 4900 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U17 +U 1 1 5CF26D07 +P 8750 5150 +F 0 "U17" H 8750 5650 60 0000 C CNN +F 1 "plot_v1" H 8950 5500 60 0000 C CNN +F 2 "" H 8750 5150 60 0000 C CNN +F 3 "" H 8750 5150 60 0000 C CNN + 1 8750 5150 + -1 0 0 1 +$EndComp +Wire Wire Line + 8750 5350 8750 4500 +Connection ~ 8750 4500 +Wire Wire Line + 7950 4900 8200 4900 +Connection ~ 8200 4900 +Wire Wire Line + 8050 3750 8500 3750 +Connection ~ 8500 3750 +Connection ~ 8600 3950 +Text GLabel 8450 3250 0 60 Input ~ 0 +a1 +Text GLabel 8250 3850 3 60 Input ~ 0 +a0 +Text GLabel 8600 4750 0 60 Input ~ 0 +a2 +Text GLabel 8050 5050 3 60 Input ~ 0 +a3 +Wire Wire Line + 8050 5050 8050 4900 +Connection ~ 8050 4900 +Wire Wire Line + 8600 4750 8750 4750 +Connection ~ 8750 4750 +Wire Wire Line + 8250 3850 8250 3750 +Connection ~ 8250 3750 +Wire Wire Line + 8450 3250 8600 3250 +Connection ~ 8600 3250 +NoConn ~ 6100 3950 +NoConn ~ 5100 4650 +Text GLabel 2000 1950 1 60 Output ~ 0 +q0 +Text GLabel 2000 2450 1 60 Output ~ 0 +q1 +Text GLabel 1900 2900 1 60 Output ~ 0 +q2 +Text GLabel 1850 3350 1 60 Output ~ 0 +q3 +Text GLabel 1850 3750 1 60 Output ~ 0 +q4 +Text GLabel 1850 4150 1 60 Output ~ 0 +q5 +Text GLabel 1800 4550 1 60 Output ~ 0 +q6 +Text GLabel 1800 4950 1 60 Output ~ 0 +q7 +Text GLabel 1800 5400 1 60 Output ~ 0 +q8 +Text GLabel 1800 5800 1 60 Output ~ 0 +q9 +Wire Wire Line + 1800 5800 1800 5900 +Connection ~ 1800 5900 +Wire Wire Line + 1800 5400 1800 5500 +Connection ~ 1800 5500 +Wire Wire Line + 1800 4950 1800 5050 +Connection ~ 1800 5050 +Wire Wire Line + 1800 4550 1800 4650 +Connection ~ 1800 4650 +Wire Wire Line + 1850 4150 1850 4250 +Connection ~ 1850 4250 +Wire Wire Line + 1850 3750 1850 3850 +Connection ~ 1850 3850 +Wire Wire Line + 1850 3350 1850 3450 +Connection ~ 1850 3450 +Wire Wire Line + 1900 2900 1900 3050 +Connection ~ 1900 3050 +Wire Wire Line + 2000 2450 2000 2550 +Connection ~ 2000 2550 +Wire Wire Line + 2000 1950 2000 2100 +Connection ~ 2000 2100 +Text Notes 5150 5650 0 118 Italic 24 +4028 IC Characteristics +$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder_Previous_Values.xml new file mode 100644 index 00000000..aa61ad5f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4></source><model><u13 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u13><u11 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u11><u12 name="type">dac_bridge<field11 name="Enter value for input load (default=1.0e-12)" /><field12 name="Enter value for out_low (default=0.0)" /><field13 name="Enter value for out_high (default=5.0)" /><field14 name="Enter the Rise Time (default=1.0e-9)" /><field15 name="Enter the Fall Time (default=1.0e-9)" /><field16 name="Enter value for out_undef (default=0.5)" /></u12></model><devicemodel /><subcircuit><x1><field>/home/saurabh/Pilot_Related/New_Installer/eSim-1.1.2/src/SubcircuitLibrary/4028</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/analysis b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file |