cleanup part2

29 files changed, 703 insertions, 0 deletions

diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~HEAD
index 0a3ccf7f..0a3ccf7f 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~fellowship2019-python3
new file mode 100644
index 00000000..af058641
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~fellowship2019-python3
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~HEAD
index e3c96645..e3c96645 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~fellowship2019-python3
new file mode 100644
index 00000000..d7cf79a0
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~fellowship2019-python3
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~HEAD
index 15f8954d..15f8954d 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3
new file mode 100644
index 00000000..ba296cf0
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and		
+U3  Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT		
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~HEAD
index 0fdf4d25..0fdf4d25 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~fellowship2019-python3
new file mode 100644
index 00000000..2c9ac554
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~fellowship2019-python3
@@ -0,0 +1,58 @@
+update=03/26/19 18:40:23
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_PSpice
+LibName23=eSim_Sources
+LibName24=eSim_Subckt
+LibName25=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~HEAD
index c853bf49..c853bf49 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~fellowship2019-python3
new file mode 100644
index 00000000..86be0215
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~fellowship2019-python3
@@ -0,0 +1,121 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60  0000 C CNN
+F 1 "d_and" H 4300 2800 60  0000 C CNN
+F 2 "" H 4250 2700 60  0000 C CNN
+F 3 "" H 4250 2700 60  0000 C CNN
+	1    4250 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60  0000 C CNN
+F 1 "d_and" H 5200 3000 60  0000 C CNN
+F 2 "" H 5150 2900 60  0000 C CNN
+F 3 "" H 5150 2900 60  0000 C CNN
+	1    5150 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30  0000 C CNN
+F 1 "PORT" H 3050 2600 30  0000 C CNN
+F 2 "" H 3050 2600 60  0000 C CNN
+F 3 "" H 3050 2600 60  0000 C CNN
+	1    3050 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30  0000 C CNN
+F 1 "PORT" H 3050 2800 30  0000 C CNN
+F 2 "" H 3050 2800 60  0000 C CNN
+F 3 "" H 3050 2800 60  0000 C CNN
+	2    3050 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30  0000 C CNN
+F 1 "PORT" H 3050 3100 30  0000 C CNN
+F 2 "" H 3050 3100 60  0000 C CNN
+F 3 "" H 3050 3100 60  0000 C CNN
+	3    3050 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30  0000 C CNN
+F 1 "PORT" H 6900 2850 30  0000 C CNN
+F 2 "" H 6900 2850 60  0000 C CNN
+F 3 "" H 6900 2850 60  0000 C CNN
+	4    6900 2850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4700 2650 4700 2800
+Wire Wire Line
+	5600 2850 6650 2850
+Wire Wire Line
+	3800 2600 3300 2600
+Wire Wire Line
+	3800 2700 3300 2700
+Wire Wire Line
+	3300 2700 3300 2800
+Wire Wire Line
+	3300 3100 4700 3100
+Wire Wire Line
+	4700 3100 4700 2900
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~HEAD
index b949ae4f..b949ae4f 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~fellowship2019-python3
new file mode 100644
index 00000000..3d9120bb
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~fellowship2019-python3
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ 
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2  net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3  net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~HEAD
index abc5faaa..abc5faaa 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~fellowship2019-python3
new file mode 100644
index 00000000..abc5faaa
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~fellowship2019-python3
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~HEAD
index e316d596..e316d596 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~fellowship2019-python3
new file mode 100644
index 00000000..4ee605a2
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~fellowship2019-python3
@@ -0,0 +1,62 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0  -150 200  200 200 N
+P 3 0 1 0  -150 200  -150 -100  200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~HEAD
index d22d0923..d22d0923 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~fellowship2019-python3
new file mode 100644
index 00000000..b25337cd
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~fellowship2019-python3
@@ -0,0 +1,16 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
+x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~HEAD
index 7afe79fe..7afe79fe 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~fellowship2019-python3
new file mode 100644
index 00000000..e159f055
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~fellowship2019-python3
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
+X3  Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and		
+X2  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and		
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~HEAD
index 7ed8e96e..7ed8e96e 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~fellowship2019-python3
new file mode 100644
index 00000000..94cd9bd4
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~fellowship2019-python3
@@ -0,0 +1,43 @@
+update=05/31/19 16:37:06
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~HEAD
index ff6d873a..ff6d873a 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~fellowship2019-python3
new file mode 100644
index 00000000..045208e6
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~fellowship2019-python3
@@ -0,0 +1,263 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X1
+U 1 1 5CF10AEA
+P 4550 2650
+F 0 "X1" H 4650 2600 60  0000 C CNN
+F 1 "3_and" H 4700 2800 60  0000 C CNN
+F 2 "" H 4550 2650 60  0000 C CNN
+F 3 "" H 4550 2650 60  0000 C CNN
+	1    4550 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CF10B72
+P 3100 2200
+F 0 "U1" H 3150 2300 30  0000 C CNN
+F 1 "PORT" H 3100 2200 30  0000 C CNN
+F 2 "" H 3100 2200 60  0000 C CNN
+F 3 "" H 3100 2200 60  0000 C CNN
+	1    3100 2200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CF10BC9
+P 3100 2500
+F 0 "U1" H 3150 2600 30  0000 C CNN
+F 1 "PORT" H 3100 2500 30  0000 C CNN
+F 2 "" H 3100 2500 60  0000 C CNN
+F 3 "" H 3100 2500 60  0000 C CNN
+	2    3100 2500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CF10BEA
+P 3100 2850
+F 0 "U1" H 3150 2950 30  0000 C CNN
+F 1 "PORT" H 3100 2850 30  0000 C CNN
+F 2 "" H 3100 2850 60  0000 C CNN
+F 3 "" H 3100 2850 60  0000 C CNN
+	8    3100 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CF10C10
+P 6200 2600
+F 0 "U1" H 6250 2700 30  0000 C CNN
+F 1 "PORT" H 6200 2600 30  0000 C CNN
+F 2 "" H 6200 2600 60  0000 C CNN
+F 3 "" H 6200 2600 60  0000 C CNN
+	9    6200 2600
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	5950 2600 5050 2600
+Wire Wire Line
+	4200 2500 4200 2200
+Wire Wire Line
+	4200 2200 3350 2200
+Wire Wire Line
+	3350 2500 3850 2500
+Wire Wire Line
+	3850 2500 3850 2600
+Wire Wire Line
+	3850 2600 4200 2600
+Wire Wire Line
+	4200 2700 4200 2850
+Wire Wire Line
+	4200 2850 3350 2850
+$Comp
+L 3_and X3
+U 1 1 5CF10DE5
+P 4600 4100
+F 0 "X3" H 4700 4050 60  0000 C CNN
+F 1 "3_and" H 4750 4250 60  0000 C CNN
+F 2 "" H 4600 4100 60  0000 C CNN
+F 3 "" H 4600 4100 60  0000 C CNN
+	1    4600 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CF10DEB
+P 3150 3650
+F 0 "U1" H 3200 3750 30  0000 C CNN
+F 1 "PORT" H 3150 3650 30  0000 C CNN
+F 2 "" H 3150 3650 60  0000 C CNN
+F 3 "" H 3150 3650 60  0000 C CNN
+	3    3150 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CF10DF1
+P 3150 3950
+F 0 "U1" H 3200 4050 30  0000 C CNN
+F 1 "PORT" H 3150 3950 30  0000 C CNN
+F 2 "" H 3150 3950 60  0000 C CNN
+F 3 "" H 3150 3950 60  0000 C CNN
+	4    3150 3950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CF10DF7
+P 3150 4300
+F 0 "U1" H 3200 4400 30  0000 C CNN
+F 1 "PORT" H 3150 4300 30  0000 C CNN
+F 2 "" H 3150 4300 60  0000 C CNN
+F 3 "" H 3150 4300 60  0000 C CNN
+	5    3150 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CF10DFD
+P 6250 4050
+F 0 "U1" H 6300 4150 30  0000 C CNN
+F 1 "PORT" H 6250 4050 30  0000 C CNN
+F 2 "" H 6250 4050 60  0000 C CNN
+F 3 "" H 6250 4050 60  0000 C CNN
+	6    6250 4050
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	6000 4050 5100 4050
+Wire Wire Line
+	4250 3950 4250 3650
+Wire Wire Line
+	4250 3650 3400 3650
+Wire Wire Line
+	3400 3950 3900 3950
+Wire Wire Line
+	3900 3950 3900 4050
+Wire Wire Line
+	3900 4050 4250 4050
+Wire Wire Line
+	4250 4150 4250 4300
+Wire Wire Line
+	4250 4300 3400 4300
+$Comp
+L 3_and X2
+U 1 1 5CF10E9C
+P 4550 5450
+F 0 "X2" H 4650 5400 60  0000 C CNN
+F 1 "3_and" H 4700 5600 60  0000 C CNN
+F 2 "" H 4550 5450 60  0000 C CNN
+F 3 "" H 4550 5450 60  0000 C CNN
+	1    4550 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CF10EA2
+P 3100 5000
+F 0 "U1" H 3150 5100 30  0000 C CNN
+F 1 "PORT" H 3100 5000 30  0000 C CNN
+F 2 "" H 3100 5000 60  0000 C CNN
+F 3 "" H 3100 5000 60  0000 C CNN
+	11   3100 5000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CF10EA8
+P 3100 5300
+F 0 "U1" H 3150 5400 30  0000 C CNN
+F 1 "PORT" H 3100 5300 30  0000 C CNN
+F 2 "" H 3100 5300 60  0000 C CNN
+F 3 "" H 3100 5300 60  0000 C CNN
+	12   3100 5300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CF10EAE
+P 3100 5650
+F 0 "U1" H 3150 5750 30  0000 C CNN
+F 1 "PORT" H 3100 5650 30  0000 C CNN
+F 2 "" H 3100 5650 60  0000 C CNN
+F 3 "" H 3100 5650 60  0000 C CNN
+	13   3100 5650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CF10EB4
+P 6200 5400
+F 0 "U1" H 6250 5500 30  0000 C CNN
+F 1 "PORT" H 6200 5400 30  0000 C CNN
+F 2 "" H 6200 5400 60  0000 C CNN
+F 3 "" H 6200 5400 60  0000 C CNN
+	10   6200 5400
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	5950 5400 5050 5400
+Wire Wire Line
+	4200 5300 4200 5000
+Wire Wire Line
+	4200 5000 3350 5000
+Wire Wire Line
+	3350 5300 3850 5300
+Wire Wire Line
+	3850 5300 3850 5400
+Wire Wire Line
+	3850 5400 4200 5400
+Wire Wire Line
+	4200 5500 4200 5650
+Wire Wire Line
+	4200 5650 3350 5650
+$Comp
+L PORT U1
+U 7 1 5CF11A2A
+P 7500 4100
+F 0 "U1" H 7550 4200 30  0000 C CNN
+F 1 "PORT" H 7500 4100 30  0000 C CNN
+F 2 "" H 7500 4100 60  0000 C CNN
+F 3 "" H 7500 4100 60  0000 C CNN
+	7    7500 4100
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CF11A8A
+P 7550 4600
+F 0 "U1" H 7600 4700 30  0000 C CNN
+F 1 "PORT" H 7550 4600 30  0000 C CNN
+F 2 "" H 7550 4600 60  0000 C CNN
+F 3 "" H 7550 4600 60  0000 C CNN
+	14   7550 4600
+	-1   0    0    1   
+$EndComp
+NoConn ~ 7250 4100
+NoConn ~ 7300 4600
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~HEAD
index b10679cc..b10679cc 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~fellowship2019-python3
new file mode 100644
index 00000000..15208169
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~fellowship2019-python3
@@ -0,0 +1,10 @@
+* Subcircuit 4073
+.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
+* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and
+x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and
+x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and
+* Control Statements
+
+.ends 4073
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~HEAD
index 5acac768..5acac768 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~fellowship2019-python3
new file mode 100644
index 00000000..5acac768
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~fellowship2019-python3
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file
diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro
index 1ff3178b..a356f8bb 100644
--- a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro
+++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro
@@ -40,7 +40,13 @@ LibName6=eSim_Hybrid
 LibName7=eSim_Miscellaneous
 LibName8=eSim_Plot
 LibName9=eSim_Power
+<<<<<<< HEAD
 LibName10=eSim_PSpice
 LibName11=eSim_Sources
 LibName12=eSim_Subckt
 LibName13=eSim_User
+=======
+LibName10=eSim_User
+LibName11=eSim_Sources
+LibName12=eSim_Subckt
+>>>>>>> fellowship2019-python3