cleanup part2

4 files changed, 780 insertions, 0 deletions

diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib
index 43241731..cd34331d 100644
--- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib
+++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 EESchema-LIBRARY Version 2.3

 #encoding utf-8

 #

@@ -150,3 +151,157 @@ ENDDRAW
 ENDDEF

 #

 #End Library

+=======
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4028
+#
+DEF 4028 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "4028" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X Q4 1 -500 350 200 R 50 50 1 1 O
+X Q2 2 -500 250 200 R 50 50 1 1 O
+X Q0 3 -500 150 200 R 50 50 1 1 O
+X Q7 4 -500 50 200 R 50 50 1 1 O
+X Q9 5 -500 -50 200 R 50 50 1 1 O
+X Q5 6 -500 -150 200 R 50 50 1 1 O
+X Q6 7 -500 -250 200 R 50 50 1 1 O
+X Vss 8 -500 -350 200 R 50 50 1 1 I
+X Q8 9 500 -350 200 L 50 50 1 1 O
+X A0 10 500 -250 200 L 50 50 1 1 I
+X A3 11 500 -150 200 L 50 50 1 1 I
+X A2 12 500 -50 200 L 50 50 1 1 I
+X A1 13 500 50 200 L 50 50 1 1 I
+X Q1 14 500 150 200 L 50 50 1 1 O
+X Q3 15 500 250 200 L 50 50 1 1 O
+X Vdd 16 500 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# DC-RESCUE-4028_test
+#
+DEF DC-RESCUE-4028_test v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC-RESCUE-4028_test" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-rescue.lib
new file mode 100644
index 00000000..214f1f4c
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-rescue.lib
@@ -0,0 +1,21 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC-RESCUE-4028_test
+#
+DEF DC-RESCUE-4028_test v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC-RESCUE-4028_test" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro
index dc708582..170c38f4 100644
--- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro
+++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 update=06/01/19 16:07:13

 version=1

 last_client=eeschema

@@ -42,3 +43,50 @@ LibName8=eSim_Power
 LibName9=eSim_Sources

 LibName10=eSim_Subckt

 LibName11=eSim_User

+=======
+update=Wed Mar 11 12:51:14 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4028_test-rescue
+LibName2=power
+LibName3=eSim_Analog
+LibName4=eSim_Devices
+LibName5=eSim_Digital
+LibName6=eSim_Hybrid
+LibName7=eSim_Miscellaneous
+LibName8=eSim_Plot
+LibName9=eSim_Power
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch
index 53226145..ba22945c 100644
--- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch
+++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 EESchema Schematic File Version 2

 LIBS:power

 LIBS:eSim_Analog

@@ -549,3 +550,558 @@ Wire Wire Line
 	2000 1950 2000 2100

 Connection ~ 2000 2100

 $EndSCHEMATC

+=======
+EESchema Schematic File Version 2
+LIBS:4028_test-rescue
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4028_test-cache
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+EELAYER END
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+$EndComp
+$Comp
+L plot_v1 U14
+U 1 1 5CF26C90
+P 8150 4900
+F 0 "U14" H 8150 5400 60  0000 C CNN
+F 1 "plot_v1" H 8350 5250 60  0000 C CNN
+F 2 "" H 8150 4900 60  0000 C CNN
+F 3 "" H 8150 4900 60  0000 C CNN
+	1    8150 4900
+	0    -1   -1   0   
+$EndComp
+$Comp
+L plot_v1 U17
+U 1 1 5CF26D07
+P 8750 5150
+F 0 "U17" H 8750 5650 60  0000 C CNN
+F 1 "plot_v1" H 8950 5500 60  0000 C CNN
+F 2 "" H 8750 5150 60  0000 C CNN
+F 3 "" H 8750 5150 60  0000 C CNN
+	1    8750 5150
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	8750 5350 8750 4500
+Connection ~ 8750 4500
+Wire Wire Line
+	7950 4900 8200 4900
+Connection ~ 8200 4900
+Wire Wire Line
+	8050 3750 8500 3750
+Connection ~ 8500 3750
+Connection ~ 8600 3950
+Text GLabel 8450 3250 0    60   Input ~ 0
+a1
+Text GLabel 8250 3850 3    60   Input ~ 0
+a0
+Text GLabel 8600 4750 0    60   Input ~ 0
+a2
+Text GLabel 8050 5050 3    60   Input ~ 0
+a3
+Wire Wire Line
+	8050 5050 8050 4900
+Connection ~ 8050 4900
+Wire Wire Line
+	8600 4750 8750 4750
+Connection ~ 8750 4750
+Wire Wire Line
+	8250 3850 8250 3750
+Connection ~ 8250 3750
+Wire Wire Line
+	8450 3250 8600 3250
+Connection ~ 8600 3250
+NoConn ~ 6100 3950
+NoConn ~ 5100 4650
+Text GLabel 2000 1950 1    60   Output ~ 0
+q0
+Text GLabel 2000 2450 1    60   Output ~ 0
+q1
+Text GLabel 1900 2900 1    60   Output ~ 0
+q2
+Text GLabel 1850 3350 1    60   Output ~ 0
+q3
+Text GLabel 1850 3750 1    60   Output ~ 0
+q4
+Text GLabel 1850 4150 1    60   Output ~ 0
+q5
+Text GLabel 1800 4550 1    60   Output ~ 0
+q6
+Text GLabel 1800 4950 1    60   Output ~ 0
+q7
+Text GLabel 1800 5400 1    60   Output ~ 0
+q8
+Text GLabel 1800 5800 1    60   Output ~ 0
+q9
+Wire Wire Line
+	1800 5800 1800 5900
+Connection ~ 1800 5900
+Wire Wire Line
+	1800 5400 1800 5500
+Connection ~ 1800 5500
+Wire Wire Line
+	1800 4950 1800 5050
+Connection ~ 1800 5050
+Wire Wire Line
+	1800 4550 1800 4650
+Connection ~ 1800 4650
+Wire Wire Line
+	1850 4150 1850 4250
+Connection ~ 1850 4250
+Wire Wire Line
+	1850 3750 1850 3850
+Connection ~ 1850 3850
+Wire Wire Line
+	1850 3350 1850 3450
+Connection ~ 1850 3450
+Wire Wire Line
+	1900 2900 1900 3050
+Connection ~ 1900 3050
+Wire Wire Line
+	2000 2450 2000 2550
+Connection ~ 2000 2550
+Wire Wire Line
+	2000 1950 2000 2100
+Connection ~ 2000 2100
+$EndSCHEMATC
+>>>>>>> fellowship2019-python3