cleanup part2

6 files changed, 699 insertions, 0 deletions

diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib
index b58b86b5..b21dbef3 100644
--- a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib
+++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 EESchema-LIBRARY Version 2.3

 #encoding utf-8

 #

@@ -120,3 +121,127 @@ ENDDRAW
 ENDDEF

 #

 #End Library

+=======
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4012
+#
+DEF 4012 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "4012" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 350 -400 0 1 0 N
+X Q1 1 -500 300 200 R 50 50 1 1 O
+X A1 2 -500 200 200 R 50 50 1 1 I
+X B1 3 -500 100 200 R 50 50 1 1 I
+X C1 4 -500 0 200 R 50 50 1 1 I
+X D1 5 -500 -100 200 R 50 50 1 1 I
+X NC 6 -500 -200 200 R 50 50 1 1 N
+X VSS 7 -500 -300 200 R 50 50 1 1 I
+X NC 8 550 -300 200 L 50 50 1 1 N
+X A2 9 550 -200 200 L 50 50 1 1 I
+X B2 10 550 -100 200 L 50 50 1 1 I
+X C2 11 550 0 200 L 50 50 1 1 I
+X D2 12 550 100 200 L 50 50 1 1 I
+X Q2 13 550 200 200 L 50 50 1 1 O
+X VDD 14 550 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DC-RESCUE-4012_test
+#
+DEF DC-RESCUE-4012_test v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC-RESCUE-4012_test" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-rescue.lib
new file mode 100644
index 00000000..5e7dc5c4
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-rescue.lib
@@ -0,0 +1,21 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC-RESCUE-4012_test
+#
+DEF DC-RESCUE-4012_test v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC-RESCUE-4012_test" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro
index ee32c69b..8af698d3 100644
--- a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro
+++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 update=06/01/19 15:09:21

 version=1

 last_client=eeschema

@@ -43,3 +44,50 @@ LibName9=eSim_PSpice
 LibName10=eSim_Sources

 LibName11=eSim_User

 LibName12=eSim_Subckt

+=======
+update=Wed Mar 11 12:50:15 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4012_test-rescue
+LibName2=power
+LibName3=eSim_Analog
+LibName4=eSim_Devices
+LibName5=eSim_Digital
+LibName6=eSim_Hybrid
+LibName7=eSim_Miscellaneous
+LibName8=eSim_Plot
+LibName9=eSim_Power
+LibName10=eSim_Subckt
+LibName11=eSim_Sources
+LibName12=eSim_User
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch
index 1380bb1d..28de6099 100644
--- a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch
+++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
 EESchema Schematic File Version 2

 LIBS:power

 LIBS:eSim_Analog

@@ -499,3 +500,506 @@ Wire Wire Line
 	4800 1850 4800 2050

 Connection ~ 4800 2050

 $EndSCHEMATC

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+EESchema Schematic File Version 2
+LIBS:4012_test-rescue
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:4012_test-cache
+EELAYER 25 0
+EELAYER END
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+encoding utf-8
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+a2
+Wire Wire Line
+	7450 4800 7550 4800
+Connection ~ 7550 4800
+Wire Wire Line
+	7100 4500 7150 4500
+Connection ~ 7150 4500
+Wire Wire Line
+	6800 3350 6800 3450
+Connection ~ 6800 3450
+Wire Wire Line
+	7350 2900 7200 2900
+Connection ~ 7200 2900
+Wire Wire Line
+	5400 1850 5400 2000
+Connection ~ 5400 2000
+Wire Wire Line
+	4800 1850 4800 2050
+Connection ~ 4800 2050
+$EndSCHEMATC
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/analysis b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~HEAD
index 660a46cc..660a46cc 100644
--- a/Examples/Analysis_Of_Digital_IC/4012_test/analysis
+++ b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/analysis~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~fellowship2019-python3
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~fellowship2019-python3
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03
\ No newline at end of file