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authorsaurabhb172020-03-11 14:59:48 +0530
committersaurabhb172020-03-11 14:59:48 +0530
commitdc61eab5251234f02c0377ea328b929340b3604c (patch)
treef1bf080150f8e19788b2dc56eeb10021a44b2c2f /Examples/Analysis_Of_Digital_IC/4002_test
parent6ebbcc31ea0ce5c78c94718e2e46d87592c5d22b (diff)
downloadeSim-dc61eab5251234f02c0377ea328b929340b3604c.tar.gz
eSim-dc61eab5251234f02c0377ea328b929340b3604c.tar.bz2
eSim-dc61eab5251234f02c0377ea328b929340b3604c.zip
cleanup part2
Diffstat (limited to 'Examples/Analysis_Of_Digital_IC/4002_test')
-rw-r--r--Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib144
-rw-r--r--Examples/Analysis_Of_Digital_IC/4002_test/4002_test-rescue.lib21
-rw-r--r--Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro48
-rw-r--r--Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch622
-rw-r--r--Examples/Analysis_Of_Digital_IC/4002_test/analysis~HEAD (renamed from Examples/Analysis_Of_Digital_IC/4002_test/analysis)0
-rw-r--r--Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python31
6 files changed, 836 insertions, 0 deletions
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib
index 53c89e01..13935dc6 100644
--- a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
@@ -138,3 +139,146 @@ ENDDRAW
ENDDEF
#
#End Library
+=======
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC-RESCUE-4002_test
+#
+DEF DC-RESCUE-4002_test v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC-RESCUE-4002_test" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# IC_4002
+#
+DEF IC_4002 X 0 40 Y Y 1 F N
+F0 "X" 0 150 60 H V C CNN
+F1 "IC_4002" 0 0 60 H V C CNN
+F2 "" 50 -150 60 H V C CNN
+F3 "" 50 -150 60 H V C CNN
+DRAW
+S -250 350 250 -400 0 1 0 N
+X 1Y 1 -450 250 200 R 50 50 1 1 O
+X 1A 2 -450 150 200 R 50 50 1 1 I
+X 1B 3 -450 50 200 R 50 50 1 1 I
+X 1C 4 -450 -50 200 R 50 50 1 1 I
+X 1D 5 -450 -150 200 R 50 50 1 1 I
+X NC 6 -450 -250 200 R 50 50 1 1 I
+X GND 7 -450 -350 200 R 50 50 1 1 I
+X NC 8 450 -350 200 L 50 50 1 1 I
+X 2A 9 450 -250 200 L 50 50 1 1 I
+X 2B 10 450 -150 200 L 50 50 1 1 I
+X 2C 11 450 -50 200 L 50 50 1 1 I
+X 2D 12 450 50 200 L 50 50 1 1 I
+X 2Y 13 450 150 200 L 50 50 1 1 O
+X VCC 14 450 250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-rescue.lib
new file mode 100644
index 00000000..1009327f
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-rescue.lib
@@ -0,0 +1,21 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC-RESCUE-4002_test
+#
+DEF DC-RESCUE-4002_test v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC-RESCUE-4002_test" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro
index 43701631..9632c383 100644
--- a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
update=06/01/19 05:45:01
version=1
last_client=eeschema
@@ -42,3 +43,50 @@ LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
+=======
+update=Wed Mar 11 12:49:35 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=4002_test-rescue
+LibName2=power
+LibName3=eSim_Devices
+LibName4=eSim_User
+LibName5=eSim_Subckt
+LibName6=eSim_Sources
+LibName7=eSim_Power
+LibName8=eSim_Plot
+LibName9=eSim_Miscellaneous
+LibName10=eSim_Hybrid
+LibName11=eSim_Digital
+LibName12=eSim_Analog
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch
index 1cce0878..963cc36a 100644
--- a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch
@@ -1,3 +1,4 @@
+<<<<<<< HEAD
EESchema Schematic File Version 2
LIBS:power
LIBS:eSim_Analog
@@ -615,3 +616,624 @@ Wire Wire Line
6800 2450 6800 2400
Connection ~ 6800 2400
$EndSCHEMATC
+=======
+EESchema Schematic File Version 2
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+LIBS:power
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+LIBS:eSim_User
+LIBS:eSim_Subckt
+LIBS:eSim_Sources
+LIBS:eSim_Power
+LIBS:eSim_Plot
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Hybrid
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+LIBS:eSim_Analog
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+Connection ~ 2200 3550
+Wire Wire Line
+ 3250 3600 3200 3450
+Connection ~ 3250 3350
+Wire Wire Line
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+Connection ~ 3200 3250
+Wire Wire Line
+ 3200 3200 3200 3250
+Connection ~ 2200 3350
+Wire Wire Line
+ 2250 3350 2200 3350
+Connection ~ 2200 3450
+Wire Wire Line
+ 2300 3450 2200 3450
+Wire Wire Line
+ 2050 3550 2300 3550
+Wire Wire Line
+ 2200 3250 2200 3550
+Wire Wire Line
+ 2250 3250 2200 3250
+Wire Wire Line
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+Wire Wire Line
+ 3200 3450 3450 3450
+Wire Wire Line
+ 3150 3350 3450 3350
+Wire Wire Line
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+Text GLabel 3500 3750 2 60 Input ~ 0
+v4
+Text GLabel 3050 3700 0 60 Input ~ 0
+v3
+Text GLabel 3100 3150 0 60 Input ~ 0
+v2
+Text GLabel 3500 3100 2 60 Input ~ 0
+v1
+$Comp
+L plot_v1 U7
+U 1 1 5CF31477
+P 3400 3450
+F 0 "U7" H 3400 3950 60 0000 C CNN
+F 1 "plot_v1" H 3600 3800 60 0000 C CNN
+F 2 "" H 3400 3450 60 0000 C CNN
+F 3 "" H 3400 3450 60 0000 C CNN
+ 1 3400 3450
+ -1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 5CF31400
+P 3050 3850
+F 0 "U4" H 3050 4350 60 0000 C CNN
+F 1 "plot_v1" H 3250 4200 60 0000 C CNN
+F 2 "" H 3050 3850 60 0000 C CNN
+F 3 "" H 3050 3850 60 0000 C CNN
+ 1 3050 3850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 5CF313A0
+P 3250 3500
+F 0 "U6" H 3250 4000 60 0000 C CNN
+F 1 "plot_v1" H 3450 3850 60 0000 C CNN
+F 2 "" H 3250 3500 60 0000 C CNN
+F 3 "" H 3250 3500 60 0000 C CNN
+ 1 3250 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 5CF303CA
+P 3200 3400
+F 0 "U5" H 3200 3900 60 0000 C CNN
+F 1 "plot_v1" H 3400 3750 60 0000 C CNN
+F 2 "" H 3200 3400 60 0000 C CNN
+F 3 "" H 3200 3400 60 0000 C CNN
+ 1 3200 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R4
+U 1 1 5CF1FDB5
+P 3550 3600
+F 0 "R4" H 3600 3730 50 0000 C CNN
+F 1 "1k" H 3600 3650 50 0000 C CNN
+F 2 "" H 3600 3580 30 0000 C CNN
+F 3 "" V 3600 3650 30 0000 C CNN
+ 1 3550 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R3
+U 1 1 5CF1FD69
+P 3550 3500
+F 0 "R3" H 3600 3630 50 0000 C CNN
+F 1 "1k" H 3600 3550 50 0000 C CNN
+F 2 "" H 3600 3480 30 0000 C CNN
+F 3 "" V 3600 3550 30 0000 C CNN
+ 1 3550 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R2
+U 1 1 5CF1FD21
+P 3550 3400
+F 0 "R2" H 3600 3530 50 0000 C CNN
+F 1 "1k" H 3600 3450 50 0000 C CNN
+F 2 "" H 3600 3380 30 0000 C CNN
+F 3 "" V 3600 3450 30 0000 C CNN
+ 1 3550 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_R R1
+U 1 1 5CF1FCC6
+P 3550 3300
+F 0 "R1" H 3600 3430 50 0000 C CNN
+F 1 "1k" H 3600 3350 50 0000 C CNN
+F 2 "" H 3600 3280 30 0000 C CNN
+F 3 "" V 3600 3350 30 0000 C CNN
+ 1 3550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC-RESCUE-4002_test v4
+U 1 1 5CF1D11E
+P 2750 3550
+F 0 "v4" H 2550 3650 60 0000 C CNN
+F 1 "DC" H 2550 3500 60 0000 C CNN
+F 2 "R1" H 2450 3550 60 0000 C CNN
+F 3 "" H 2750 3550 60 0000 C CNN
+ 1 2750 3550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC-RESCUE-4002_test v3
+U 1 1 5CF1D0EF
+P 2750 3450
+F 0 "v3" H 2550 3550 60 0000 C CNN
+F 1 "DC" H 2550 3400 60 0000 C CNN
+F 2 "R1" H 2450 3450 60 0000 C CNN
+F 3 "" H 2750 3450 60 0000 C CNN
+ 1 2750 3450
+ 0 1 1 0
+$EndComp
+$Comp
+L DC-RESCUE-4002_test v2
+U 1 1 5CF1D0C3
+P 2700 3350
+F 0 "v2" H 2500 3450 60 0000 C CNN
+F 1 "DC" H 2500 3300 60 0000 C CNN
+F 2 "R1" H 2400 3350 60 0000 C CNN
+F 3 "" H 2700 3350 60 0000 C CNN
+ 1 2700 3350
+ 0 1 1 0
+$EndComp
+$Comp
+L DC-RESCUE-4002_test v1
+U 1 1 5CF1CE2E
+P 2700 3250
+F 0 "v1" H 2500 3350 60 0000 C CNN
+F 1 "DC" H 2500 3200 60 0000 C CNN
+F 2 "R1" H 2400 3250 60 0000 C CNN
+F 3 "" H 2700 3250 60 0000 C CNN
+ 1 2700 3250
+ 0 1 1 0
+$EndComp
+Connection ~ 6800 2300
+Wire Wire Line
+ 6750 2450 6800 2450
+Wire Wire Line
+ 6800 2450 6800 2400
+Connection ~ 6800 2400
+$EndSCHEMATC
+>>>>>>> fellowship2019-python3
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/analysis b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~HEAD
index 660a46cc..660a46cc 100644
--- a/Examples/Analysis_Of_Digital_IC/4002_test/analysis
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~HEAD
diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03 \ No newline at end of file