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| author | rahulp13 | 2020-02-14 15:16:35 +0530 |
|---|---|---|
| committer | rahulp13 | 2020-02-14 15:16:35 +0530 |
| commit | cb55e59de7ee4383c04edfae7c39ad9ae9552b36 (patch) | |
| tree | de1b292a10e8196689bf1a208fe6fe32f4618846 /Examples/4_Input_OR_Characteristics/4072.cir.out | |
| parent | 08d4a0336550a0e610709970a0c5d366e109fe82 (diff) | |
| download | eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.gz eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.tar.bz2 eSim-cb55e59de7ee4383c04edfae7c39ad9ae9552b36.zip | |
common code for Win and Linux, merged py2 changes
Diffstat (limited to 'Examples/4_Input_OR_Characteristics/4072.cir.out')
| -rw-r--r-- | Examples/4_Input_OR_Characteristics/4072.cir.out | 36 |
1 files changed, 0 insertions, 36 deletions
diff --git a/Examples/4_Input_OR_Characteristics/4072.cir.out b/Examples/4_Input_OR_Characteristics/4072.cir.out deleted file mode 100644 index 61e8e949..00000000 --- a/Examples/4_Input_OR_Characteristics/4072.cir.out +++ /dev/null @@ -1,36 +0,0 @@ -* c:\users\bhargav\esim\src\subcircuitlibrary\4072\4072.cir
-
-* u2 net-_u1-pad5_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
-* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
-* u5 net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
-* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_or
-* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_or
-a1 [net-_u1-pad5_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
-a4 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
-a5 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
-a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
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