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author | Rahul P | 2022-02-10 03:20:46 +0530 |
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committer | GitHub | 2022-02-10 03:20:46 +0530 |
commit | 5e5971c04fc18bb46fcc5f5bc53491b6b0e05157 (patch) | |
tree | ce7fd5a8b6b2d45212dbfdac1f2b2179ad045cca | |
parent | a76d4c8ca1366b777dd8dff9802d793672abee38 (diff) | |
parent | 8012d6d4be3af0fc6b9e7bafbed2e497bc4d539e (diff) | |
download | eSim-5e5971c04fc18bb46fcc5f5bc53491b6b0e05157.tar.gz eSim-5e5971c04fc18bb46fcc5f5bc53491b6b0e05157.tar.bz2 eSim-5e5971c04fc18bb46fcc5f5bc53491b6b0e05157.zip |
Merge pull request #188 from rahulp13/master
Resolves extern issue with gcc version above 9
-rwxr-xr-x | src/maker/ModelGeneration.py | 51 |
1 files changed, 30 insertions, 21 deletions
diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index bc79e443..caafe3c8 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -254,8 +254,8 @@ class ModelGeneration(QtWidgets.QWidget): cfunc = open(self.modelpath + 'cfunc.mod', 'w') print("Building content for cfunc.mod file") - comment = '''/* This is cfunc.mod file auto generated by gen_con_info.py - Developed by Sumanto Kar at IIT Bombay */\n + comment = '''/* This cfunc.mod file auto generated by gen_con_info.py + Developed by Sumanto, Rahul at IIT Bombay */\n ''' header = ''' @@ -287,15 +287,16 @@ class ModelGeneration(QtWidgets.QWidget): { inst_count++; PARAM(instance_id)=inst_count; - foo''' + self.fname.split('.')[0] + '''(0,inst_count); + foo_''' + self.fname.split('.')[0] + '''(0,inst_count); /* Allocate storage for output ports \ and set the load for input ports */ ''' port_init = [] for i, item in enumerate(self.input_port + self.output_port): - port_init.append(''' - port_''' + item.split(':')[0] + '''=PORT_SIZE(''' + item.split(':')[0] + '''); + port_init.append(self.fname.split('.')[0] + '''_port_''' + + item.split(':')[0] + '''=PORT_SIZE(''' + + item.split(':')[0] + '''); ''') cm_event_alloc = [] @@ -351,11 +352,13 @@ and set the load for input ports */ {\n\ if( INPUT_STATE(" + item.split(':')[0] + "[Ii])==ZERO )\n\ {\n\ - temp_" + item.split(':')[0] + "[Ii]=0;\ + " + self.fname.split('.')[0] + + "_temp_" + item.split(':')[0] + "[Ii]=0;\ }\n\ else\n\ {\n\ - temp_" + item.split(':')[0] + "[Ii]=1;\n\ + " + self.fname.split('.')[0] + + "_temp_" + item.split(':')[0] + "[Ii]=1;\n\ }\n\ }\n") @@ -367,11 +370,13 @@ and set the load for input ports */ "\t/* Scheduling event and processing them */\n\ for(Ii=0;Ii<PORT_SIZE(" + item.split(':')[0] + ");Ii++)\n\ {\n\ - if(temp_" + item.split(':')[0] + "[Ii]==0)\n\ + if(" + self.fname.split('.')[0] + "_temp_" + + item.split(':')[0] + "[Ii]==0)\n\ {\n\ _op_" + item.split(':')[0] + "[Ii]=ZERO;\n\ }\n\ - else if(temp_" + item.split(':')[0] + "[Ii]==1)\n\ + else if(" + self.fname.split('.')[0] + + "_temp_" + item.split(':')[0] + "[Ii]==1)\n\ {\n\ _op_" + item.split(':')[0] + "[Ii]=ONE;\n\ }\n\ @@ -472,7 +477,7 @@ and set the load for input ports */ for item in assign_data_to_input: cfunc.write(item) - cfunc.write("\tfoo" + self.fname.split('.')[0] + "(1,count);\n\n") + cfunc.write("\tfoo_" + self.fname.split('.')[0] + "(1,count);\n\n") for item in sch_output_event: cfunc.write(item) @@ -604,12 +609,14 @@ and set the load for input ports */ 'w') print("Building content for sim_main_" + self.fname.split('.')[0] + ".h file") - simh.write("int foo" + self.fname.split('.')[0] + "(int,int);") + simh.write("int foo_" + self.fname.split('.')[0] + "(int,int);") extern_var = [] for i, item in enumerate(self.input_port + self.output_port): extern_var.append(''' - int temp_''' + item.split(':')[0] + '''[1024]; - int port_''' + item.split(':')[0] + ''';''') + int ''' + self.fname.split('.')[0] + '''_temp_''' + + item.split(':')[0] + '''[1024]; + int ''' + self.fname.split('.')[0] + '''_port_''' + + item.split(':')[0] + ''';''') for item in extern_var: simh.write(item) simh.close() @@ -653,11 +660,13 @@ and set the load for input ports */ extern_var = [] for i, item in enumerate(self.input_port + self.output_port): extern_var.append(''' - extern "C" int temp_''' + item.split(':')[0] + '''[1024]; - extern "C" int port_''' + item.split(':')[0] + ''';''') + extern "C" int ''' + self.fname.split('.')[0] + + '''_temp_''' + item.split(':')[0] + '''[1024]; + extern "C" int ''' + self.fname.split('.')[0] + + '''_port_''' + item.split(':')[0] + ''';''') extern_var.append(''' - extern "C" int foo''' + self.fname.split('.')[0] + '''(int,int); + extern "C" int foo_''' + self.fname.split('.')[0] + '''(int,int); ''') convert_func = ''' void int2arr''' + self.fname.split('.')[0] + '''(int num, int array[], int n) @@ -677,7 +686,7 @@ and set the load for input ports */ } ''' foo_func = ''' - int foo''' + self.fname.split('.')[0] + '''(int init,int count) + int foo_''' + self.fname.split('.')[0] + '''(int init,int count) { static VerilatedContext* contextp = new VerilatedContext; static V''' + self.fname.split('.')[0] + "* " + self.fname.split('.')[0] + '''[1024]; @@ -715,9 +724,9 @@ and set the load for input ports */ item.split(':')[0] + ''' = arr2int''' + self.fname.split('.')[0] + - '''(temp_''' + + '''(''' + self.fname.split('.')[0] + '''_temp_''' + item.split(':')[0] + - ", port_" + + ''', ''' + self.fname.split('.')[0] + '''_port_''' + item.split(':')[0] + ''');\n''') before_eval.append( @@ -745,9 +754,9 @@ and set the load for input ports */ self.fname.split('.')[0] + '''[count] -> ''' + item.split(':')[0] + - ''', temp_''' + + ''', ''' + self.fname.split('.')[0] + '''_temp_''' + item.split(':')[0] + - ''', port_''' + + ''', ''' + self.fname.split('.')[0] + '''_port_''' + item.split(':')[0] + ''');\n''') after_eval.append(''' |