CD4001 is NOR gate IC.

11 files changed, 920 insertions, 0 deletions

diff --git a/library/SubcircuitLibrary/CD4001/CD4001-cache.lib b/library/SubcircuitLibrary/CD4001/CD4001-cache.lib
new file mode 100644
index 00000000..6c512720
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/CD4001-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4001/CD4001.cir b/library/SubcircuitLibrary/CD4001/CD4001.cir
new file mode 100644
index 00000000..17bf85e4
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/CD4001.cir
@@ -0,0 +1,27 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4001\CD4001.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/22 15:17:26
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M5  Net-_M5-Pad1_ Net-_M2-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M2  Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M6  Net-_M2-Pad1_ Net-_M6-Pad2_ Net-_M5-Pad1_ Net-_M5-Pad1_ eSim_MOS_P		
+M8  Net-_M2-Pad1_ Net-_M6-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M13  Net-_M13-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M10  Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M14  Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M13-Pad1_ Net-_M13-Pad1_ eSim_MOS_P		
+M16  Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M3  Net-_M3-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M4  Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M3-Pad1_ Net-_M3-Pad1_ eSim_MOS_P		
+M7  Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M11  Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M9  Net-_M12-Pad1_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M12  Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M11-Pad1_ Net-_M11-Pad1_ eSim_MOS_P		
+M15  Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+U1  Net-_M2-Pad2_ Net-_M6-Pad2_ Net-_M2-Pad1_ Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M14-Pad2_ Net-_M1-Pad3_ Net-_M11-Pad2_ Net-_M12-Pad2_ Net-_M12-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M4-Pad2_ Net-_M11-Pad3_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/CD4001/CD4001.cir.out b/library/SubcircuitLibrary/CD4001/CD4001.cir.out
new file mode 100644
index 00000000..169eff19
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/CD4001.cir.out
@@ -0,0 +1,30 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4001\cd4001.cir
+
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+m5 net-_m5-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m6 net-_m2-pad1_ net-_m6-pad2_ net-_m5-pad1_ net-_m5-pad1_ CMOSP W=100u L=100u M=1
+m8 net-_m2-pad1_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m14 net-_m10-pad1_ net-_m14-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1
+m16 net-_m10-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m1-pad1_ net-_m4-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1
+m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1
+m9 net-_m12-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m12 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m15 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+* u1  net-_m2-pad2_ net-_m6-pad2_ net-_m2-pad1_ net-_m10-pad1_ net-_m10-pad2_ net-_m14-pad2_ net-_m1-pad3_ net-_m11-pad2_ net-_m12-pad2_ net-_m12-pad1_ net-_m1-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m11-pad3_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4001/CD4001.pro b/library/SubcircuitLibrary/CD4001/CD4001.pro
new file mode 100644
index 00000000..d7f78c3b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/CD4001.pro
@@ -0,0 +1,71 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
diff --git a/library/SubcircuitLibrary/CD4001/CD4001.sch b/library/SubcircuitLibrary/CD4001/CD4001.sch
new file mode 100644
index 00000000..9fc9cff3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/CD4001.sch
@@ -0,0 +1,616 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:CD4001-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+U 1 1 628DC1F6
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+F 1 "eSim_MOS_P" H 5000 3900 50  0000 R CNN
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+F 3 "" H 5000 3750 60  0000 C CNN
+	1    4950 3750
+	1    0    0    1   
+$EndComp
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+$EndComp
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+$EndComp
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+F 3 "" H 7250 3750 60  0000 C CNN
+	1    7200 3750
+	1    0    0    1   
+$EndComp
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+F 2 "" H 7100 4450 29  0000 C CNN
+F 3 "" H 6900 4550 60  0000 C CNN
+	1    6800 4750
+	1    0    0    -1  
+$EndComp
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+F 3 "" H 7250 4250 60  0000 C CNN
+	1    7200 4250
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+$EndComp
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+$EndComp
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+	1    4900 1850
+	1    0    0    1   
+$EndComp
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+F 2 "" H 4800 2550 29  0000 C CNN
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+$EndComp
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+F 2 "" H 5150 2450 29  0000 C CNN
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+	1    4900 2350
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+$EndComp
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+	1    5500 2850
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+$EndComp
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+F 2 "" H 7450 1950 29  0000 C CNN
+F 3 "" H 7250 1850 60  0000 C CNN
+	1    7200 1850
+	1    0    0    1   
+$EndComp
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+F 2 "" H 7100 2550 29  0000 C CNN
+F 3 "" H 6900 2650 60  0000 C CNN
+	1    6800 2850
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+$EndComp
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+F 2 "" H 7450 2450 29  0000 C CNN
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+F 2 "" H 8100 2550 29  0000 C CNN
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+	1    7800 2850
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+	7050 3750 6650 3750
+Wire Wire Line
+	6650 3750 6650 4950
+Wire Wire Line
+	6650 4950 6700 4950
+Wire Wire Line
+	7050 4250 6950 4250
+Wire Wire Line
+	6950 4250 6950 4800
+Wire Wire Line
+	6950 4800 7900 4800
+Wire Wire Line
+	7900 4800 7900 4950
+Wire Wire Line
+	7350 4500 7850 4500
+Connection ~ 7350 4500
+Wire Wire Line
+	6650 4250 6400 4250
+Connection ~ 6650 4250
+Wire Wire Line
+	6950 4450 6400 4450
+Connection ~ 6950 4450
+Wire Wire Line
+	5050 2050 5050 2150
+Wire Wire Line
+	4700 2850 4700 2750
+Wire Wire Line
+	4700 2750 5300 2750
+Wire Wire Line
+	5300 2750 5300 2850
+Wire Wire Line
+	4700 3250 4700 3300
+Wire Wire Line
+	4700 3300 7600 3300
+Wire Wire Line
+	5300 3300 5300 3250
+Wire Wire Line
+	5200 3200 5200 3300
+Connection ~ 5200 3300
+Wire Wire Line
+	4800 3200 4800 3300
+Connection ~ 4800 3300
+Wire Wire Line
+	5050 2550 5050 2750
+Connection ~ 5050 2750
+Wire Wire Line
+	5150 2200 5150 2100
+Wire Wire Line
+	5150 2100 5050 2100
+Connection ~ 5050 2100
+Wire Wire Line
+	5150 1700 5150 1650
+Wire Wire Line
+	5050 1650 7450 1650
+Wire Wire Line
+	4750 1850 4350 1850
+Wire Wire Line
+	4350 1850 4350 3050
+Wire Wire Line
+	4350 3050 4400 3050
+Wire Wire Line
+	4750 2350 4650 2350
+Wire Wire Line
+	4650 2350 4650 2900
+Wire Wire Line
+	4650 2900 5600 2900
+Wire Wire Line
+	5600 2900 5600 3050
+Wire Wire Line
+	5050 2600 5550 2600
+Connection ~ 5050 2600
+Wire Wire Line
+	4350 2350 4100 2350
+Connection ~ 4350 2350
+Wire Wire Line
+	4650 2550 4100 2550
+Connection ~ 4650 2550
+Wire Wire Line
+	7350 2050 7350 2150
+Wire Wire Line
+	7000 2850 7000 2750
+Wire Wire Line
+	7000 2750 7600 2750
+Wire Wire Line
+	7600 2750 7600 2850
+Wire Wire Line
+	7000 3300 7000 3250
+Wire Wire Line
+	7600 3300 7600 3250
+Wire Wire Line
+	7500 3200 7500 3300
+Connection ~ 7500 3300
+Wire Wire Line
+	7100 3200 7100 3300
+Connection ~ 7100 3300
+Wire Wire Line
+	7350 2550 7350 2750
+Connection ~ 7350 2750
+Wire Wire Line
+	7450 2200 7450 2100
+Wire Wire Line
+	7450 2100 7350 2100
+Connection ~ 7350 2100
+Wire Wire Line
+	7450 1650 7450 1700
+Wire Wire Line
+	7050 1850 6650 1850
+Wire Wire Line
+	6650 1850 6650 3050
+Wire Wire Line
+	6650 3050 6700 3050
+Wire Wire Line
+	7050 2350 6950 2350
+Wire Wire Line
+	6950 2350 6950 2900
+Wire Wire Line
+	6950 2900 7900 2900
+Wire Wire Line
+	7900 2900 7900 3050
+Wire Wire Line
+	7350 2600 7850 2600
+Connection ~ 7350 2600
+Wire Wire Line
+	6650 2350 6400 2350
+Connection ~ 6650 2350
+Wire Wire Line
+	6950 2550 6400 2550
+Connection ~ 6950 2550
+Connection ~ 7350 3550
+Connection ~ 5200 3550
+Connection ~ 7350 1650
+Connection ~ 5150 1650
+Connection ~ 7000 3300
+Connection ~ 5300 3300
+Connection ~ 7000 5200
+Connection ~ 5350 5200
+Wire Wire Line
+	5800 3300 5800 5200
+Connection ~ 5800 5200
+Connection ~ 5800 3300
+Connection ~ 6050 1650
+Wire Wire Line
+	6300 5400 6300 5200
+Connection ~ 6300 5200
+$Comp
+L PORT U1
+U 1 1 628E3C82
+P 3900 4250
+F 0 "U1" H 3950 4350 30  0000 C CNN
+F 1 "PORT" H 3900 4250 30  0000 C CNN
+F 2 "" H 3900 4250 60  0000 C CNN
+F 3 "" H 3900 4250 60  0000 C CNN
+	1    3900 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 628E3D0D
+P 3900 4450
+F 0 "U1" H 3950 4550 30  0000 C CNN
+F 1 "PORT" H 3900 4450 30  0000 C CNN
+F 2 "" H 3900 4450 60  0000 C CNN
+F 3 "" H 3900 4450 60  0000 C CNN
+	2    3900 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 628E3D80
+P 5850 4500
+F 0 "U1" H 5900 4600 30  0000 C CNN
+F 1 "PORT" H 5850 4500 30  0000 C CNN
+F 2 "" H 5850 4500 60  0000 C CNN
+F 3 "" H 5850 4500 60  0000 C CNN
+	3    5850 4500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 4 1 628E3DE3
+P 8100 4500
+F 0 "U1" H 8150 4600 30  0000 C CNN
+F 1 "PORT" H 8100 4500 30  0000 C CNN
+F 2 "" H 8100 4500 60  0000 C CNN
+F 3 "" H 8100 4500 60  0000 C CNN
+	4    8100 4500
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 628E3EA4
+P 6150 4250
+F 0 "U1" H 6200 4350 30  0000 C CNN
+F 1 "PORT" H 6150 4250 30  0000 C CNN
+F 2 "" H 6150 4250 60  0000 C CNN
+F 3 "" H 6150 4250 60  0000 C CNN
+	5    6150 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 628E3F07
+P 6150 4450
+F 0 "U1" H 6200 4550 30  0000 C CNN
+F 1 "PORT" H 6150 4450 30  0000 C CNN
+F 2 "" H 6150 4450 60  0000 C CNN
+F 3 "" H 6150 4450 60  0000 C CNN
+	6    6150 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 628E4017
+P 6050 5400
+F 0 "U1" H 6100 5500 30  0000 C CNN
+F 1 "PORT" H 6050 5400 30  0000 C CNN
+F 2 "" H 6050 5400 60  0000 C CNN
+F 3 "" H 6050 5400 60  0000 C CNN
+	7    6050 5400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 628E4565
+P 6150 2350
+F 0 "U1" H 6200 2450 30  0000 C CNN
+F 1 "PORT" H 6150 2350 30  0000 C CNN
+F 2 "" H 6150 2350 60  0000 C CNN
+F 3 "" H 6150 2350 60  0000 C CNN
+	8    6150 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 628E45D8
+P 6150 2550
+F 0 "U1" H 6200 2650 30  0000 C CNN
+F 1 "PORT" H 6150 2550 30  0000 C CNN
+F 2 "" H 6150 2550 60  0000 C CNN
+F 3 "" H 6150 2550 60  0000 C CNN
+	9    6150 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 628E463D
+P 8100 2600
+F 0 "U1" H 8150 2700 30  0000 C CNN
+F 1 "PORT" H 8100 2600 30  0000 C CNN
+F 2 "" H 8100 2600 60  0000 C CNN
+F 3 "" H 8100 2600 60  0000 C CNN
+	10   8100 2600
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 11 1 628E473E
+P 5800 2600
+F 0 "U1" H 5850 2700 30  0000 C CNN
+F 1 "PORT" H 5800 2600 30  0000 C CNN
+F 2 "" H 5800 2600 60  0000 C CNN
+F 3 "" H 5800 2600 60  0000 C CNN
+	11   5800 2600
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 12 1 628E47DD
+P 3850 2350
+F 0 "U1" H 3900 2450 30  0000 C CNN
+F 1 "PORT" H 3850 2350 30  0000 C CNN
+F 2 "" H 3850 2350 60  0000 C CNN
+F 3 "" H 3850 2350 60  0000 C CNN
+	12   3850 2350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 628E484A
+P 3850 2550
+F 0 "U1" H 3900 2650 30  0000 C CNN
+F 1 "PORT" H 3850 2550 30  0000 C CNN
+F 2 "" H 3850 2550 60  0000 C CNN
+F 3 "" H 3850 2550 60  0000 C CNN
+	13   3850 2550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 628E4934
+P 5800 1350
+F 0 "U1" H 5850 1450 30  0000 C CNN
+F 1 "PORT" H 5800 1350 30  0000 C CNN
+F 2 "" H 5800 1350 60  0000 C CNN
+F 3 "" H 5800 1350 60  0000 C CNN
+	14   5800 1350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6050 1350 6050 3550
+Connection ~ 6050 3550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4001/CD4001.sub b/library/SubcircuitLibrary/CD4001/CD4001.sub
new file mode 100644
index 00000000..9371c24e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/CD4001.sub
@@ -0,0 +1,24 @@
+* Subcircuit CD4001
+.subckt CD4001 net-_m2-pad2_ net-_m6-pad2_ net-_m2-pad1_ net-_m10-pad1_ net-_m10-pad2_ net-_m14-pad2_ net-_m1-pad3_ net-_m11-pad2_ net-_m12-pad2_ net-_m12-pad1_ net-_m1-pad1_ net-_m1-pad2_ net-_m4-pad2_ net-_m11-pad3_ 
+* c:\fossee\esim\library\subcircuitlibrary\cd4001\cd4001.cir
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+m5 net-_m5-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m6 net-_m2-pad1_ net-_m6-pad2_ net-_m5-pad1_ net-_m5-pad1_ CMOSP W=100u L=100u M=1
+m8 net-_m2-pad1_ net-_m6-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m14 net-_m10-pad1_ net-_m14-pad2_ net-_m13-pad1_ net-_m13-pad1_ CMOSP W=100u L=100u M=1
+m16 net-_m10-pad1_ net-_m14-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m3 net-_m3-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m1-pad1_ net-_m4-pad2_ net-_m3-pad1_ net-_m3-pad1_ CMOSP W=100u L=100u M=1
+m7 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m11-pad2_ net-_m11-pad3_ net-_m11-pad3_ CMOSP W=100u L=100u M=1
+m9 net-_m12-pad1_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m12 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m15 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+* Control Statements
+
+.ends CD4001
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4001/CD4001_Previous_Values.xml b/library/SubcircuitLibrary/CD4001/CD4001_Previous_Values.xml
new file mode 100644
index 00000000..f4515cf9
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/CD4001_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m5><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m8><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m13><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m10><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m14><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m16><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m7><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m11><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m9><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m12><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m15></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4001/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4001/NMOS-180nm.lib
new file mode 100644
index 00000000..51e9b119
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/CD4001/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4001/PMOS-180nm.lib
new file mode 100644
index 00000000..032b5b95
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/CD4001/README.md b/library/SubcircuitLibrary/CD4001/README.md
new file mode 100644
index 00000000..db436fdf
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/README.md
@@ -0,0 +1,26 @@
+
+# CD4001 IC
+
+It is 2-input NOR Gate IC. CD4001 IC is designed with 180nm CMOS technology in eSim consisting four NOR Gates. When both the inputs are LOW then only output is HIGH, otherwise LOW. It is also called inverted OR Gate, a type of Universal Gate.
+
+
+## Usage/Examples
+
+The IC can be used for Noise Removing.
+
+Also used in devices such as PCs and notebooks.
+
+## Documentation
+
+To know the details of CD4001 IC please go through with the documentation : [CD4001_datasheet](https://www.ti.com/lit/gpn/cd4001b)
+
+## Comments/Notes
+
+Please note this is a complete digital IC. It works fine at the time of simulation.
+
+## Contributer
+
+Name: Ankush Mondal
+Email: mondalankush369@gmail.com
+Year: 2022
+Position: FOSSEE Summer Fellow 2022
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4001/analysis b/library/SubcircuitLibrary/CD4001/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4001/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file