diff options
| author | Rahul P | 2022-02-03 23:35:59 +0530 |
|---|---|---|
| committer | GitHub | 2022-02-03 23:35:59 +0530 |
| commit | c28c426d72c72ef2327021f1fe8d7a7d97a76aa1 (patch) | |
| tree | d99b097fb58aa40bef9a69f37ded99c9601e0f47 | |
| parent | 253b978cbdb5dd74df9a46488b05da3da8c50d48 (diff) | |
| parent | 1d5cdb7e19c6efca598a6e7529b2969dfc18a450 (diff) | |
| download | eSim-c28c426d72c72ef2327021f1fe8d7a7d97a76aa1.tar.gz eSim-c28c426d72c72ef2327021f1fe8d7a7d97a76aa1.tar.bz2 eSim-c28c426d72c72ef2327021f1fe8d7a7d97a76aa1.zip | |
Merge pull request #181 from Charaan27/master
Disable creation of verilator dependency files
| -rwxr-xr-x | src/maker/ModelGeneration.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/maker/ModelGeneration.py b/src/maker/ModelGeneration.py index 71edad85..bc79e443 100755 --- a/src/maker/ModelGeneration.py +++ b/src/maker/ModelGeneration.py @@ -792,7 +792,7 @@ and set the load for input ports */ # print(self.modelpath) self.cmd = "verilator -Wall " + wno + "\ - --cc --exe --Mdir . -CFLAGS -fPIC sim_main_" + \ + --cc --exe --no-MMD --Mdir . -CFLAGS -fPIC sim_main_" + \ self.fname.split('.')[0] + ".cpp " + self.fname self.process = QtCore.QProcess(self) self.process.readyReadStandardOutput.connect(self.readAllStandard) |