diff options
| author | saurabhb17 | 2020-03-11 14:59:48 +0530 |
|---|---|---|
| committer | saurabhb17 | 2020-03-11 14:59:48 +0530 |
| commit | dc61eab5251234f02c0377ea328b929340b3604c (patch) | |
| tree | f1bf080150f8e19788b2dc56eeb10021a44b2c2f | |
| parent | 6ebbcc31ea0ce5c78c94718e2e46d87592c5d22b (diff) | |
| download | eSim-dc61eab5251234f02c0377ea328b929340b3604c.tar.gz eSim-dc61eab5251234f02c0377ea328b929340b3604c.tar.bz2 eSim-dc61eab5251234f02c0377ea328b929340b3604c.zip | |
cleanup part2
132 files changed, 6872 insertions, 18 deletions
diff --git a/Examples/4_bit_JK_ff/4_bit_JK_ff.pro b/Examples/4_bit_JK_ff/4_bit_JK_ff.pro index 04158b1f..7222ecc7 100644 --- a/Examples/4_bit_JK_ff/4_bit_JK_ff.pro +++ b/Examples/4_bit_JK_ff/4_bit_JK_ff.pro @@ -43,17 +43,17 @@ LibName9=eSim_Sources LibName10=eSim_Subckt LibName11=eSim_User LibName12=power -LibName13=device +LibName13=contrib LibName14=transistors LibName15=conn -LibName16=linear +LibName16=valves LibName17=regul LibName18=74xx LibName19=cmos4000 LibName20=adc-dac LibName21=memory LibName22=xilinx -LibName23=special +LibName23=atmel LibName24=microcontrollers LibName25=dsp LibName26=microchip @@ -69,6 +69,3 @@ LibName35=display LibName36=cypress LibName37=siliconi LibName38=opto -LibName39=atmel -LibName40=contrib -LibName41=valves diff --git a/Examples/7805VoltageRegulator/7805VoltageRegulator.pro b/Examples/7805VoltageRegulator/7805VoltageRegulator.pro index bc7e8b79..181fb7a8 100644 --- a/Examples/7805VoltageRegulator/7805VoltageRegulator.pro +++ b/Examples/7805VoltageRegulator/7805VoltageRegulator.pro @@ -52,10 +52,17 @@ LibName18=opto LibName19=atmel LibName20=contrib LibName21=power +<<<<<<< HEAD LibName22=device LibName23=transistors LibName24=conn LibName25=linear +======= +LibName22=eSim_Subckt +LibName23=transistors +LibName24=conn +LibName25=eSim_Plot +>>>>>>> fellowship2019-python3 LibName26=regul LibName27=74xx LibName28=cmos4000 @@ -67,6 +74,9 @@ LibName33=eSim_Miscellaneous LibName34=eSim_Power LibName35=eSim_Sources LibName36=eSim_User +<<<<<<< HEAD LibName37=eSim_Plot LibName38=eSim_Subckt +======= +>>>>>>> fellowship2019-python3 diff --git a/Examples/7805VoltageRegulator/D.lib b/Examples/7805VoltageRegulator/D.lib~HEAD index 8a7fb4da..8a7fb4da 100644 --- a/Examples/7805VoltageRegulator/D.lib +++ b/Examples/7805VoltageRegulator/D.lib~HEAD diff --git a/Examples/7805VoltageRegulator/D.lib~fellowship2019-python3 b/Examples/7805VoltageRegulator/D.lib~fellowship2019-python3 new file mode 100644 index 00000000..8a7fb4da --- /dev/null +++ b/Examples/7805VoltageRegulator/D.lib~fellowship2019-python3 @@ -0,0 +1,2 @@ +.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/Examples/7805VoltageRegulator/NPN.lib b/Examples/7805VoltageRegulator/NPN.lib~HEAD index 6509fe7a..6509fe7a 100644 --- a/Examples/7805VoltageRegulator/NPN.lib +++ b/Examples/7805VoltageRegulator/NPN.lib~HEAD diff --git a/Examples/7812VoltageRegulator/NPN.lib b/Examples/7805VoltageRegulator/NPN.lib~fellowship2019-python3 index 6509fe7a..6509fe7a 100644 --- a/Examples/7812VoltageRegulator/NPN.lib +++ b/Examples/7805VoltageRegulator/NPN.lib~fellowship2019-python3 diff --git a/Examples/7812VoltageRegulator/7812VoltageRegulator.pro b/Examples/7812VoltageRegulator/7812VoltageRegulator.pro index f295ecfd..86307015 100644 --- a/Examples/7812VoltageRegulator/7812VoltageRegulator.pro +++ b/Examples/7812VoltageRegulator/7812VoltageRegulator.pro @@ -52,10 +52,17 @@ LibName18=opto LibName19=atmel
LibName20=contrib
LibName21=power
+<<<<<<< HEAD LibName22=device
LibName23=transistors
LibName24=conn
LibName25=linear
+======= +LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+>>>>>>> fellowship2019-python3 LibName26=regul
LibName27=74xx
LibName28=cmos4000
@@ -67,7 +74,10 @@ LibName33=eSim_Miscellaneous LibName34=eSim_Power
LibName35=eSim_Sources
LibName36=eSim_Subckt
+<<<<<<< HEAD LibName37=eSim_User
LibName38=eSim_Plot
LibName39=eSim_PSpice
+======= +>>>>>>> fellowship2019-python3 diff --git a/Examples/7812VoltageRegulator/NPN.lib~HEAD b/Examples/7812VoltageRegulator/NPN.lib~HEAD new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/Examples/7812VoltageRegulator/NPN.lib~HEAD @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Examples/7812VoltageRegulator/NPN.lib~fellowship2019-python3 b/Examples/7812VoltageRegulator/NPN.lib~fellowship2019-python3 new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/Examples/7812VoltageRegulator/NPN.lib~fellowship2019-python3 @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib index 3c64b7f9..6eee1a53 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-cache.lib @@ -27,11 +27,19 @@ X Vdd 14 500 300 200 L 50 50 1 1 I ENDDRAW ENDDEF # +<<<<<<< HEAD # DC # DEF DC v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN F1 "DC" -200 -50 60 H V C CNN +======= +# DC-RESCUE-3_Input_NAND_Characteristics +# +DEF DC-RESCUE-3_Input_NAND_Characteristics v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-3_Input_NAND_Characteristics" -200 -50 60 H V C CNN +>>>>>>> fellowship2019-python3 F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-rescue.lib b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-rescue.lib new file mode 100644 index 00000000..ea79a75f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics-rescue.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-3_Input_NAND_Characteristics +# +DEF DC-RESCUE-3_Input_NAND_Characteristics v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-3_Input_NAND_Characteristics" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro index e4c3c722..4d64f7c3 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.pro @@ -1,3 +1,4 @@ +<<<<<<< HEAD update=06/01/19 15:31:12
version=1
last_client=eeschema
@@ -43,3 +44,50 @@ LibName9=eSim_PSpice LibName10=eSim_Sources
LibName11=eSim_Subckt
LibName12=eSim_User
+======= +update=Wed Mar 11 12:47:11 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../eSim/kicadSchematicLibrary +[eeschema/libraries] +LibName1=3_Input_NAND_Characteristics-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_User +LibName11=eSim_Sources +LibName12=eSim_Subckt +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch index e8be1afc..fe74ae2d 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_Input_NAND_Characteristics.sch @@ -1,4 +1,8 @@ EESchema Schematic File Version 2 +<<<<<<< HEAD +======= +LIBS:3_Input_NAND_Characteristics-rescue +>>>>>>> fellowship2019-python3 LIBS:power LIBS:eSim_Analog LIBS:eSim_Devices @@ -7,10 +11,16 @@ LIBS:eSim_Hybrid LIBS:eSim_Miscellaneous LIBS:eSim_Plot LIBS:eSim_Power +<<<<<<< HEAD LIBS:eSim_PSpice LIBS:eSim_Sources LIBS:eSim_Subckt LIBS:eSim_User +======= +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +>>>>>>> fellowship2019-python3 LIBS:3_Input_NAND_Characteristics-cache EELAYER 25 0 EELAYER END @@ -82,7 +92,11 @@ F 3 "" H 6800 5750 60 0000 C CNN 1 0 0 -1 $EndComp $Comp +<<<<<<< HEAD L DC v1 +======= +L DC-RESCUE-3_Input_NAND_Characteristics v1 +>>>>>>> fellowship2019-python3 U 1 1 5CF24F1F P 1700 2350 F 0 "v1" H 1500 2450 60 0000 C CNN @@ -93,7 +107,11 @@ F 3 "" H 1700 2350 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v2 +======= +L DC-RESCUE-3_Input_NAND_Characteristics v2 +>>>>>>> fellowship2019-python3 U 1 1 5CF24F90 P 1700 2900 F 0 "v2" H 1500 3000 60 0000 C CNN @@ -104,7 +122,11 @@ F 3 "" H 1700 2900 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v3 +======= +L DC-RESCUE-3_Input_NAND_Characteristics v3 +>>>>>>> fellowship2019-python3 U 1 1 5CF24FC7 P 1700 3450 F 0 "v3" H 1500 3550 60 0000 C CNN @@ -115,7 +137,11 @@ F 3 "" H 1700 3450 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v4 +======= +L DC-RESCUE-3_Input_NAND_Characteristics v4 +>>>>>>> fellowship2019-python3 U 1 1 5CF25001 P 1750 4000 F 0 "v4" H 1550 4100 60 0000 C CNN @@ -126,7 +152,11 @@ F 3 "" H 1750 4000 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v5 +======= +L DC-RESCUE-3_Input_NAND_Characteristics v5 +>>>>>>> fellowship2019-python3 U 1 1 5CF25044 P 1750 4550 F 0 "v5" H 1550 4650 60 0000 C CNN @@ -137,7 +167,11 @@ F 3 "" H 1750 4550 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v6 +======= +L DC-RESCUE-3_Input_NAND_Characteristics v6 +>>>>>>> fellowship2019-python3 U 1 1 5CF25082 P 1750 5050 F 0 "v6" H 1550 5150 60 0000 C CNN @@ -244,7 +278,11 @@ Wire Wire Line Wire Wire Line 5950 5900 6200 5900 $Comp +<<<<<<< HEAD L DC v7 +======= +L DC-RESCUE-3_Input_NAND_Characteristics v7 +>>>>>>> fellowship2019-python3 U 1 1 5CF25804 P 9250 3250 F 0 "v7" H 9050 3350 60 0000 C CNN @@ -255,7 +293,11 @@ F 3 "" H 9250 3250 60 0000 C CNN 0 -1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v8 +======= +L DC-RESCUE-3_Input_NAND_Characteristics v8 +>>>>>>> fellowship2019-python3 U 1 1 5CF2580A P 9250 3800 F 0 "v8" H 9050 3900 60 0000 C CNN @@ -266,7 +308,11 @@ F 3 "" H 9250 3800 60 0000 C CNN 0 -1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v9 +======= +L DC-RESCUE-3_Input_NAND_Characteristics v9 +>>>>>>> fellowship2019-python3 U 1 1 5CF25810 P 9250 4300 F 0 "v9" H 9050 4400 60 0000 C CNN diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~HEAD index 0a3ccf7f..0a3ccf7f 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~fellowship2019-python3 new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and-cache.lib~fellowship2019-python3 @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~HEAD index e3c96645..e3c96645 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~fellowship2019-python3 new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir.out~fellowship2019-python3 @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~HEAD index 15f8954d..15f8954d 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~fellowship2019-python3 new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.cir~fellowship2019-python3 @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro~HEAD index 0fdf4d25..0fdf4d25 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro~fellowship2019-python3 new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.pro~fellowship2019-python3 @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~HEAD index c853bf49..c853bf49 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~fellowship2019-python3 new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sch~fellowship2019-python3 @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~HEAD index b949ae4f..b949ae4f 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~fellowship2019-python3 new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and.sub~fellowship2019-python3 @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml~HEAD index abc5faaa..abc5faaa 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml~fellowship2019-python3 index abc5faaa..abc5faaa 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/3_and_Previous_Values.xml~fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis~HEAD index 660a46cc..660a46cc 100644 --- a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/analysis b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis~fellowship2019-python3 index 660a46cc..660a46cc 100644 --- a/Examples/Analysis_Of_Digital_IC/4002_test/analysis +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/analysis~fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_i.txt b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_i.txt new file mode 100644 index 00000000..4112f610 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_i.txt @@ -0,0 +1,271 @@ + * c:\users\malli\esim-workspace\4023_test\4023_test.cir + Transient Analysis Fri Jan 31 12:34:52 2020 +-------------------------------------------------------------------------------- +Index time a4#branch_1_0 a4#branch_1_1 a4#branch_1_2 +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +11 6.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +12 8.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +14 1.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +15 1.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +16 1.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +17 1.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +18 2.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +19 2.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +20 2.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +21 2.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +22 2.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +23 3.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +24 3.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +25 3.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +26 3.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +27 3.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +28 4.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +32 4.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +33 5.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +34 5.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +35 5.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +36 5.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +37 5.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +38 6.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +39 6.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +40 6.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +41 6.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +42 6.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +43 7.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +44 7.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +45 7.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +46 7.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +47 7.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +48 8.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +49 8.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +50 8.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time a4#branch_1_0 a4#branch_1_1 a4#branch_1_2 +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 + + * c:\users\malli\esim-workspace\4023_test\4023_test.cir + Transient Analysis Fri Jan 31 12:34:52 2020 +-------------------------------------------------------------------------------- +Index time v1#branch v2#branch v3#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +11 6.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +12 8.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +14 1.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +15 1.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +16 1.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +17 1.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +18 2.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +19 2.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +20 2.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +21 2.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +22 2.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +23 3.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +24 3.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +25 3.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +26 3.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +27 3.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +28 4.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +32 4.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +33 5.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +34 5.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +35 5.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +36 5.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +37 5.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +38 6.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +39 6.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +40 6.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +41 6.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +42 6.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +43 7.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +44 7.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +45 7.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +46 7.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +47 7.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +48 8.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +49 8.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +50 8.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time v1#branch v2#branch v3#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 + + * c:\users\malli\esim-workspace\4023_test\4023_test.cir + Transient Analysis Fri Jan 31 12:34:52 2020 +-------------------------------------------------------------------------------- +Index time v4#branch v5#branch v6#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +11 6.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +12 8.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +14 1.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +15 1.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +16 1.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +17 1.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +18 2.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +19 2.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +20 2.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +21 2.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +22 2.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +23 3.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +24 3.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +25 3.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +26 3.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +27 3.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +28 4.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +32 4.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +33 5.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +34 5.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +35 5.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +36 5.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +37 5.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +38 6.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +39 6.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +40 6.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +41 6.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +42 6.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +43 7.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +44 7.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +45 7.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +46 7.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +47 7.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +48 8.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +49 8.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +50 8.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time v4#branch v5#branch v6#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 + + * c:\users\malli\esim-workspace\4023_test\4023_test.cir + Transient Analysis Fri Jan 31 12:34:52 2020 +-------------------------------------------------------------------------------- +Index time v7#branch v8#branch v9#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +11 6.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +12 8.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +14 1.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +15 1.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +16 1.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +17 1.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +18 2.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +19 2.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +20 2.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +21 2.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +22 2.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +23 3.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +24 3.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +25 3.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +26 3.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +27 3.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +28 4.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +32 4.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +33 5.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +34 5.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +35 5.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +36 5.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +37 5.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +38 6.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +39 6.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +40 6.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +41 6.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +42 6.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +43 7.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +44 7.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +45 7.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +46 7.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +47 7.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +48 8.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +49 8.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +50 8.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time v7#branch v8#branch v9#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 diff --git a/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_v.txt b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_v.txt new file mode 100644 index 00000000..09e3e5bb --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/3_Input_NAND_Characteristics/plot_data_v.txt @@ -0,0 +1,271 @@ + * c:\users\malli\esim-workspace\4023_test\4023_test.cir + Transient Analysis Fri Jan 31 12:34:52 2020 +-------------------------------------------------------------------------------- +Index time a1 a2 a3 +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 5.000000e+00 5.000000e+00 +1 1.000000e-05 0.000000e+00 5.000000e+00 5.000000e+00 +2 2.000000e-05 0.000000e+00 5.000000e+00 5.000000e+00 +3 4.000000e-05 0.000000e+00 5.000000e+00 5.000000e+00 +4 8.000000e-05 0.000000e+00 5.000000e+00 5.000000e+00 +5 1.600000e-04 0.000000e+00 5.000000e+00 5.000000e+00 +6 3.200000e-04 0.000000e+00 5.000000e+00 5.000000e+00 +7 6.400000e-04 0.000000e+00 5.000000e+00 5.000000e+00 +8 1.280000e-03 0.000000e+00 5.000000e+00 5.000000e+00 +9 2.560000e-03 0.000000e+00 5.000000e+00 5.000000e+00 +10 4.560000e-03 0.000000e+00 5.000000e+00 5.000000e+00 +11 6.560000e-03 0.000000e+00 5.000000e+00 5.000000e+00 +12 8.560000e-03 0.000000e+00 5.000000e+00 5.000000e+00 +13 1.056000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +14 1.256000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +15 1.456000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +16 1.656000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +17 1.856000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +18 2.056000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +19 2.256000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +20 2.456000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +21 2.656000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +22 2.856000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +23 3.056000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +24 3.256000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +25 3.456000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +26 3.656000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +27 3.856000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +28 4.056000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +29 4.256000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +30 4.456000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +31 4.656000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +32 4.856000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +33 5.056000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +34 5.256000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +35 5.456000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +36 5.656000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +37 5.856000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +38 6.056000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +39 6.256000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +40 6.456000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +41 6.656000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +42 6.856000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +43 7.056000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +44 7.256000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +45 7.456000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +46 7.656000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +47 7.856000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +48 8.056000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +49 8.256000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +50 8.456000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +51 8.656000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +52 8.856000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +53 9.056000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +54 9.256000e-02 0.000000e+00 5.000000e+00 5.000000e+00 + +Index time a1 a2 a3 +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +56 9.656000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +57 9.856000e-02 0.000000e+00 5.000000e+00 5.000000e+00 +58 1.000000e-01 0.000000e+00 5.000000e+00 5.000000e+00 + + * c:\users\malli\esim-workspace\4023_test\4023_test.cir + Transient Analysis Fri Jan 31 12:34:52 2020 +-------------------------------------------------------------------------------- +Index time b1 b2 b3 +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 0.000000e+00 5.000000e+00 +1 1.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +2 2.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +3 4.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +4 8.000000e-05 5.000000e+00 0.000000e+00 5.000000e+00 +5 1.600000e-04 5.000000e+00 0.000000e+00 5.000000e+00 +6 3.200000e-04 5.000000e+00 0.000000e+00 5.000000e+00 +7 6.400000e-04 5.000000e+00 0.000000e+00 5.000000e+00 +8 1.280000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +9 2.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +10 4.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +11 6.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +12 8.560000e-03 5.000000e+00 0.000000e+00 5.000000e+00 +13 1.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +14 1.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +15 1.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +16 1.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +17 1.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +18 2.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +19 2.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +20 2.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +21 2.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +22 2.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +23 3.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +24 3.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +25 3.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +26 3.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +27 3.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +28 4.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +29 4.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +30 4.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +31 4.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +32 4.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +33 5.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +34 5.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +35 5.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +36 5.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +37 5.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +38 6.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +39 6.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +40 6.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +41 6.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +42 6.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +43 7.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +44 7.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +45 7.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +46 7.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +47 7.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +48 8.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +49 8.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +50 8.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +51 8.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +52 8.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +53 9.056000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +54 9.256000e-02 5.000000e+00 0.000000e+00 5.000000e+00 + +Index time b1 b2 b3 +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +56 9.656000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +57 9.856000e-02 5.000000e+00 0.000000e+00 5.000000e+00 +58 1.000000e-01 5.000000e+00 0.000000e+00 5.000000e+00 + + * c:\users\malli\esim-workspace\4023_test\4023_test.cir + Transient Analysis Fri Jan 31 12:34:52 2020 +-------------------------------------------------------------------------------- +Index time c1 c2 c3 +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 +1 1.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +2 2.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +3 4.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +4 8.000000e-05 0.000000e+00 0.000000e+00 0.000000e+00 +5 1.600000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +6 3.200000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +7 6.400000e-04 0.000000e+00 0.000000e+00 0.000000e+00 +8 1.280000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +9 2.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +10 4.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +11 6.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +12 8.560000e-03 0.000000e+00 0.000000e+00 0.000000e+00 +13 1.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +14 1.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +15 1.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +16 1.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +17 1.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +18 2.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +19 2.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +20 2.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +21 2.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +22 2.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +23 3.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +24 3.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +25 3.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +26 3.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +27 3.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +28 4.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +29 4.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +30 4.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +31 4.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +32 4.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +33 5.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +34 5.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +35 5.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +36 5.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +37 5.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +38 6.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +39 6.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +40 6.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +41 6.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +42 6.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +43 7.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +44 7.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +45 7.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +46 7.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +47 7.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +48 8.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +49 8.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +50 8.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +51 8.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +52 8.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +53 9.056000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +54 9.256000e-02 0.000000e+00 0.000000e+00 0.000000e+00 + +Index time c1 c2 c3 +-------------------------------------------------------------------------------- +55 9.456000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +56 9.656000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +57 9.856000e-02 0.000000e+00 0.000000e+00 0.000000e+00 +58 1.000000e-01 0.000000e+00 0.000000e+00 0.000000e+00 + + * c:\users\malli\esim-workspace\4023_test\4023_test.cir + Transient Analysis Fri Jan 31 12:34:52 2020 +-------------------------------------------------------------------------------- +Index time q1 q2 q3 +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 5.000000e+00 5.000000e+00 +1 1.000000e-05 5.000000e+00 5.000000e+00 5.000000e+00 +2 2.000000e-05 5.000000e+00 5.000000e+00 5.000000e+00 +3 4.000000e-05 5.000000e+00 5.000000e+00 5.000000e+00 +4 8.000000e-05 5.000000e+00 5.000000e+00 5.000000e+00 +5 1.600000e-04 5.000000e+00 5.000000e+00 5.000000e+00 +6 3.200000e-04 5.000000e+00 5.000000e+00 5.000000e+00 +7 6.400000e-04 5.000000e+00 5.000000e+00 5.000000e+00 +8 1.280000e-03 5.000000e+00 5.000000e+00 5.000000e+00 +9 2.560000e-03 5.000000e+00 5.000000e+00 5.000000e+00 +10 4.560000e-03 5.000000e+00 5.000000e+00 5.000000e+00 +11 6.560000e-03 5.000000e+00 5.000000e+00 5.000000e+00 +12 8.560000e-03 5.000000e+00 5.000000e+00 5.000000e+00 +13 1.056000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +14 1.256000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +15 1.456000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +16 1.656000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +17 1.856000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +18 2.056000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +19 2.256000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +20 2.456000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +21 2.656000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +22 2.856000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +23 3.056000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +24 3.256000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +25 3.456000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +26 3.656000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +27 3.856000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +28 4.056000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +29 4.256000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +30 4.456000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +31 4.656000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +32 4.856000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +33 5.056000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +34 5.256000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +35 5.456000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +36 5.656000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +37 5.856000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +38 6.056000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +39 6.256000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +40 6.456000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +41 6.656000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +42 6.856000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +43 7.056000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +44 7.256000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +45 7.456000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +46 7.656000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +47 7.856000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +48 8.056000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +49 8.256000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +50 8.456000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +51 8.656000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +52 8.856000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +53 9.056000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +54 9.256000e-02 5.000000e+00 5.000000e+00 5.000000e+00 + +Index time q1 q2 q3 +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +56 9.656000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +57 9.856000e-02 5.000000e+00 5.000000e+00 5.000000e+00 +58 1.000000e-01 5.000000e+00 5.000000e+00 5.000000e+00 diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib index 53c89e01..13935dc6 100644 --- a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-cache.lib @@ -1,3 +1,4 @@ +<<<<<<< HEAD EESchema-LIBRARY Version 2.3
#encoding utf-8
#
@@ -138,3 +139,146 @@ ENDDRAW ENDDEF
#
#End Library
+======= +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-4002_test +# +DEF DC-RESCUE-4002_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4002_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-rescue.lib new file mode 100644 index 00000000..1009327f --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test-rescue.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-4002_test +# +DEF DC-RESCUE-4002_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4002_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro index 43701631..9632c383 100644 --- a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.pro @@ -1,3 +1,4 @@ +<<<<<<< HEAD update=06/01/19 05:45:01
version=1
last_client=eeschema
@@ -42,3 +43,50 @@ LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
+======= +update=Wed Mar 11 12:49:35 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=4002_test-rescue +LibName2=power +LibName3=eSim_Devices +LibName4=eSim_User +LibName5=eSim_Subckt +LibName6=eSim_Sources +LibName7=eSim_Power +LibName8=eSim_Plot +LibName9=eSim_Miscellaneous +LibName10=eSim_Hybrid +LibName11=eSim_Digital +LibName12=eSim_Analog +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch index 1cce0878..963cc36a 100644 --- a/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch +++ b/Examples/Analysis_Of_Digital_IC/4002_test/4002_test.sch @@ -1,3 +1,4 @@ +<<<<<<< HEAD EESchema Schematic File Version 2
LIBS:power
LIBS:eSim_Analog
@@ -615,3 +616,624 @@ Wire Wire Line 6800 2450 6800 2400
Connection ~ 6800 2400
$EndSCHEMATC
+======= +EESchema Schematic File Version 2 +LIBS:4002_test-rescue +LIBS:power +LIBS:eSim_Devices +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Analog +LIBS:4002_test-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L IC_4002 X1 +U 1 1 5CF1C395 +P 5500 3400 +F 0 "X1" H 5500 3550 60 0000 C CNN +F 1 "IC_4002" H 5500 3400 60 0000 C CNN +F 2 "" H 5550 3250 60 0000 C CNN +F 3 "" H 5550 3250 60 0000 C CNN + 1 5500 3400 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U1 +U 1 1 5CF1C610 +P 4350 3450 +F 0 "U1" H 4350 3450 60 0000 C CNN +F 1 "adc_bridge_4" H 4350 3750 60 0000 C CNN +F 2 "" H 4350 3450 60 0000 C CNN +F 3 "" H 4350 3450 60 0000 C CNN + 1 4350 3450 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U3 +U 1 1 5CF1C67F +P 6650 3450 +F 0 "U3" H 6650 3450 60 0000 C CNN +F 1 "adc_bridge_4" H 6650 3750 60 0000 C CNN +F 2 "" H 6650 3450 60 0000 C CNN +F 3 "" H 6650 3450 60 0000 C CNN + 1 6650 3450 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_2 U2 +U 1 1 5CF1CADD +P 6200 2350 +F 0 "U2" H 6200 2350 60 0000 C CNN +F 1 "dac_bridge_2" H 6250 2500 60 0000 C CNN +F 2 "" H 6200 2350 60 0000 C CNN +F 3 "" H 6200 2350 60 0000 C CNN + 1 6200 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CF29F39 +P 7000 2350 +F 0 "R5" H 7050 2480 50 0000 C CNN +F 1 "1k" H 7050 2400 50 0000 C CNN +F 2 "" H 7050 2330 30 0000 C CNN +F 3 "" V 7050 2400 30 0000 C CNN + 1 7000 2350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CF2A627 +P 7000 2450 +F 0 "R6" H 7050 2580 50 0000 C CNN +F 1 "1k" H 7050 2500 50 0000 C CNN +F 2 "" H 7050 2430 30 0000 C CNN +F 3 "" V 7050 2500 30 0000 C CNN + 1 7000 2450 + 1 0 0 -1 +$EndComp +NoConn ~ 5050 3750 +NoConn ~ 5050 3650 +NoConn ~ 5950 3750 +NoConn ~ 5950 3150 +$Comp +L plot_v1 U9 +U 1 1 5CF2F0DA +P 6800 2300 +F 0 "U9" H 6800 2800 60 0000 C CNN +F 1 "plot_v1" H 7000 2650 60 0000 C CNN +F 2 "" H 6800 2300 60 0000 C CNN +F 3 "" H 6800 2300 60 0000 C CNN + 1 6800 2300 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 5CF2FF74 +P 6750 2350 +F 0 "U8" H 6750 2850 60 0000 C CNN +F 1 "plot_v1" H 6950 2700 60 0000 C CNN +F 2 "" H 6750 2350 60 0000 C CNN +F 3 "" H 6750 2350 60 0000 C CNN + 1 6750 2350 + -1 0 0 1 +$EndComp +Text GLabel 6950 2150 2 60 Input ~ 0 +out1 +Text GLabel 6850 2500 2 60 Input ~ 0 +out2 +Wire Wire Line + 3750 3250 3800 3250 +Wire Wire Line + 3750 3350 3800 3350 +Wire Wire Line + 3750 3450 3800 3450 +Wire Wire Line + 3750 3550 3800 3550 +Wire Wire Line + 6100 3350 5950 3350 +Wire Wire Line + 6100 3450 5950 3450 +Wire Wire Line + 6100 3550 5950 3550 +Wire Wire Line + 6100 3650 5950 3650 +Wire Wire Line + 7250 3350 7200 3350 +Wire Wire Line + 7250 3450 7200 3450 +Wire Wire Line + 7250 3550 7200 3550 +Wire Wire Line + 7250 3650 7200 3650 +Wire Wire Line + 8700 4050 8700 2350 +Wire Wire Line + 4900 3250 5050 3250 +Wire Wire Line + 4900 3350 5050 3350 +Wire Wire Line + 4900 3450 5050 3450 +Wire Wire Line + 4900 3550 5050 3550 +Wire Wire Line + 5050 3150 4950 3150 +Wire Wire Line + 4950 3150 4950 2300 +Wire Wire Line + 4950 2300 5750 2300 +Wire Wire Line + 5950 3250 6100 3250 +Wire Wire Line + 6100 3250 6100 3000 +Wire Wire Line + 6100 3000 5150 3000 +Wire Wire Line + 5150 3000 5150 2400 +Wire Wire Line + 5150 2400 5750 2400 +Wire Wire Line + 6900 2300 6750 2300 +Wire Wire Line + 6900 2400 6750 2400 +Wire Wire Line + 7200 2300 7350 2300 +Wire Wire Line + 7350 2300 7350 2400 +Wire Wire Line + 7350 2400 7200 2400 +Wire Wire Line + 8700 2350 7350 2350 +Connection ~ 7350 2350 +Wire Wire Line + 2050 4050 8700 4050 +Wire Wire Line + 6800 2100 6800 2300 +Wire Wire Line + 6750 2450 6750 2550 +Wire Wire Line + 6850 2500 6750 2500 +Connection ~ 6750 2500 +Wire Wire Line + 6950 2150 6800 2150 +Connection ~ 6800 2150 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5CF4D6F1 +P 4750 3950 +F 0 "#FLG01" H 4750 4045 50 0001 C CNN +F 1 "PWR_FLAG" H 4750 4130 50 0000 C CNN +F 2 "" H 4750 3950 50 0000 C CNN +F 3 "" H 4750 3950 50 0000 C CNN + 1 4750 3950 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5CF4EA85 +P 4750 4150 +F 0 "#PWR02" H 4750 3900 50 0001 C CNN +F 1 "GND" H 4750 4000 50 0000 C CNN +F 2 "" H 4750 4150 50 0000 C CNN +F 3 "" H 4750 4150 50 0000 C CNN + 1 4750 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4750 3950 4750 4150 +Connection ~ 4750 4050 +Connection ~ 8700 3650 +Wire Wire Line + 8700 3650 8650 3650 +Connection ~ 8700 3550 +Wire Wire Line + 8650 3550 8700 3550 +Connection ~ 8700 3450 +Wire Wire Line + 8650 3450 8700 3450 +Connection ~ 8700 3350 +Wire Wire Line + 8650 3350 8700 3350 +Wire Wire Line + 2050 3550 2050 4050 +Wire Wire Line + 3250 3850 2850 3850 +Connection ~ 7750 3700 +Wire Wire Line + 7800 3700 7750 3700 +Wire Wire Line + 7800 3750 7850 3750 +Wire Wire Line + 7800 3700 7800 3750 +Connection ~ 7700 3550 +Wire Wire Line + 7700 3800 7700 3550 +Wire Wire Line + 7500 3800 7700 3800 +Wire Wire Line + 7900 3300 7700 3300 +Wire Wire Line + 7900 3050 7900 3300 +Connection ~ 7650 3450 +Wire Wire Line + 7650 3200 7650 3450 +Wire Wire Line + 7400 3200 7650 3200 +Wire Wire Line + 7750 3750 7750 3650 +Connection ~ 7600 3550 +Wire Wire Line + 7600 3600 7600 3550 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3400 7600 3450 +Connection ~ 7700 3350 +Wire Wire Line + 7700 3300 7700 3350 +Wire Wire Line + 7750 3650 7550 3650 +Wire Wire Line + 7550 3550 7750 3550 +Wire Wire Line + 7750 3450 7550 3450 +Wire Wire Line + 7750 3350 7550 3350 +Text GLabel 7900 3050 2 60 Input ~ 0 +v5 +Text GLabel 7400 3200 0 60 Input ~ 0 +v6 +Text GLabel 7500 3800 0 60 Input ~ 0 +v7 +Text GLabel 7850 3750 2 60 Input ~ 0 +v8 +$Comp +L plot_v1 U13 +U 1 1 5CF460B3 +P 7750 3550 +F 0 "U13" H 7750 4050 60 0000 C CNN +F 1 "plot_v1" H 7950 3900 60 0000 C CNN +F 2 "" H 7750 3550 60 0000 C CNN +F 3 "" H 7750 3550 60 0000 C CNN + 1 7750 3550 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U10 +U 1 1 5CF46008 +P 7600 3400 +F 0 "U10" H 7600 3900 60 0000 C CNN +F 1 "plot_v1" H 7800 3750 60 0000 C CNN +F 2 "" H 7600 3400 60 0000 C CNN +F 3 "" H 7600 3400 60 0000 C CNN + 1 7600 3400 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 5CF45F98 +P 7600 3600 +F 0 "U11" H 7600 4100 60 0000 C CNN +F 1 "plot_v1" H 7800 3950 60 0000 C CNN +F 2 "" H 7600 3600 60 0000 C CNN +F 3 "" H 7600 3600 60 0000 C CNN + 1 7600 3600 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 5CF45618 +P 7700 3500 +F 0 "U12" H 7700 4000 60 0000 C CNN +F 1 "plot_v1" H 7900 3850 60 0000 C CNN +F 2 "" H 7700 3500 60 0000 C CNN +F 3 "" H 7700 3500 60 0000 C CNN + 1 7700 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CF232CD +P 7350 3700 +F 0 "R10" H 7400 3830 50 0000 C CNN +F 1 "1k" H 7400 3750 50 0000 C CNN +F 2 "" H 7400 3680 30 0000 C CNN +F 3 "" V 7400 3750 30 0000 C CNN + 1 7350 3700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CF232C7 +P 7350 3600 +F 0 "R9" H 7400 3730 50 0000 C CNN +F 1 "1k" H 7400 3650 50 0000 C CNN +F 2 "" H 7400 3580 30 0000 C CNN +F 3 "" V 7400 3650 30 0000 C CNN + 1 7350 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CF232C1 +P 7350 3500 +F 0 "R8" H 7400 3630 50 0000 C CNN +F 1 "1k" H 7400 3550 50 0000 C CNN +F 2 "" H 7400 3480 30 0000 C CNN +F 3 "" V 7400 3550 30 0000 C CNN + 1 7350 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CF232BB +P 7350 3400 +F 0 "R7" H 7400 3530 50 0000 C CNN +F 1 "1k" H 7400 3450 50 0000 C CNN +F 2 "" H 7400 3380 30 0000 C CNN +F 3 "" V 7400 3450 30 0000 C CNN + 1 7350 3400 + 1 0 0 -1 +$EndComp +$Comp +L DC-RESCUE-4002_test v6 +U 1 1 5CF1E4C8 +P 8200 3550 +F 0 "v6" H 8000 3650 60 0000 C CNN +F 1 "DC" H 8000 3500 60 0000 C CNN +F 2 "R1" H 7900 3550 60 0000 C CNN +F 3 "" H 8200 3550 60 0000 C CNN + 1 8200 3550 + 0 -1 1 0 +$EndComp +$Comp +L DC-RESCUE-4002_test v5 +U 1 1 5CF1E4C2 +P 8200 3650 +F 0 "v5" H 8000 3750 60 0000 C CNN +F 1 "DC" H 8000 3600 60 0000 C CNN +F 2 "R1" H 7900 3650 60 0000 C CNN +F 3 "" H 8200 3650 60 0000 C CNN + 1 8200 3650 + 0 -1 1 0 +$EndComp +$Comp +L DC-RESCUE-4002_test v8 +U 1 1 5CF1E4BC +P 8200 3350 +F 0 "v8" H 8000 3450 60 0000 C CNN +F 1 "DC" H 8000 3300 60 0000 C CNN +F 2 "R1" H 7900 3350 60 0000 C CNN +F 3 "" H 8200 3350 60 0000 C CNN + 1 8200 3350 + 0 -1 1 0 +$EndComp +$Comp +L DC-RESCUE-4002_test v7 +U 1 1 5CF1E4B6 +P 8200 3450 +F 0 "v7" H 8000 3550 60 0000 C CNN +F 1 "DC" H 8000 3400 60 0000 C CNN +F 2 "R1" H 7900 3450 60 0000 C CNN +F 3 "" H 8200 3450 60 0000 C CNN + 1 8200 3450 + 0 -1 1 0 +$EndComp +Connection ~ 3300 3350 +Wire Wire Line + 3300 3150 3300 3350 +Wire Wire Line + 3100 3150 3300 3150 +Connection ~ 3350 3250 +Wire Wire Line + 3350 3100 3350 3250 +Wire Wire Line + 3500 3100 3350 3100 +Connection ~ 3400 3600 +Wire Wire Line + 3500 3600 3400 3600 +Wire Wire Line + 3500 3750 3500 3600 +Connection ~ 3250 3700 +Wire Wire Line + 3050 3700 3250 3700 +Wire Wire Line + 3250 3600 3250 3850 +Connection ~ 3400 3550 +Wire Wire Line + 3400 3550 3400 3650 +Connection ~ 2200 3550 +Wire Wire Line + 3250 3600 3200 3450 +Connection ~ 3250 3350 +Wire Wire Line + 3250 3300 3250 3350 +Connection ~ 3200 3250 +Wire Wire Line + 3200 3200 3200 3250 +Connection ~ 2200 3350 +Wire Wire Line + 2250 3350 2200 3350 +Connection ~ 2200 3450 +Wire Wire Line + 2300 3450 2200 3450 +Wire Wire Line + 2050 3550 2300 3550 +Wire Wire Line + 2200 3250 2200 3550 +Wire Wire Line + 2250 3250 2200 3250 +Wire Wire Line + 3200 3550 3450 3550 +Wire Wire Line + 3200 3450 3450 3450 +Wire Wire Line + 3150 3350 3450 3350 +Wire Wire Line + 3150 3250 3450 3250 +Text GLabel 3500 3750 2 60 Input ~ 0 +v4 +Text GLabel 3050 3700 0 60 Input ~ 0 +v3 +Text GLabel 3100 3150 0 60 Input ~ 0 +v2 +Text GLabel 3500 3100 2 60 Input ~ 0 +v1 +$Comp +L plot_v1 U7 +U 1 1 5CF31477 +P 3400 3450 +F 0 "U7" H 3400 3950 60 0000 C CNN +F 1 "plot_v1" H 3600 3800 60 0000 C CNN +F 2 "" H 3400 3450 60 0000 C CNN +F 3 "" H 3400 3450 60 0000 C CNN + 1 3400 3450 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5CF31400 +P 3050 3850 +F 0 "U4" H 3050 4350 60 0000 C CNN +F 1 "plot_v1" H 3250 4200 60 0000 C CNN +F 2 "" H 3050 3850 60 0000 C CNN +F 3 "" H 3050 3850 60 0000 C CNN + 1 3050 3850 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5CF313A0 +P 3250 3500 +F 0 "U6" H 3250 4000 60 0000 C CNN +F 1 "plot_v1" H 3450 3850 60 0000 C CNN +F 2 "" H 3250 3500 60 0000 C CNN +F 3 "" H 3250 3500 60 0000 C CNN + 1 3250 3500 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5CF303CA +P 3200 3400 +F 0 "U5" H 3200 3900 60 0000 C CNN +F 1 "plot_v1" H 3400 3750 60 0000 C CNN +F 2 "" H 3200 3400 60 0000 C CNN +F 3 "" H 3200 3400 60 0000 C CNN + 1 3200 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CF1FDB5 +P 3550 3600 +F 0 "R4" H 3600 3730 50 0000 C CNN +F 1 "1k" H 3600 3650 50 0000 C CNN +F 2 "" H 3600 3580 30 0000 C CNN +F 3 "" V 3600 3650 30 0000 C CNN + 1 3550 3600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CF1FD69 +P 3550 3500 +F 0 "R3" H 3600 3630 50 0000 C CNN +F 1 "1k" H 3600 3550 50 0000 C CNN +F 2 "" H 3600 3480 30 0000 C CNN +F 3 "" V 3600 3550 30 0000 C CNN + 1 3550 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CF1FD21 +P 3550 3400 +F 0 "R2" H 3600 3530 50 0000 C CNN +F 1 "1k" H 3600 3450 50 0000 C CNN +F 2 "" H 3600 3380 30 0000 C CNN +F 3 "" V 3600 3450 30 0000 C CNN + 1 3550 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CF1FCC6 +P 3550 3300 +F 0 "R1" H 3600 3430 50 0000 C CNN +F 1 "1k" H 3600 3350 50 0000 C CNN +F 2 "" H 3600 3280 30 0000 C CNN +F 3 "" V 3600 3350 30 0000 C CNN + 1 3550 3300 + 1 0 0 -1 +$EndComp +$Comp +L DC-RESCUE-4002_test v4 +U 1 1 5CF1D11E +P 2750 3550 +F 0 "v4" H 2550 3650 60 0000 C CNN +F 1 "DC" H 2550 3500 60 0000 C CNN +F 2 "R1" H 2450 3550 60 0000 C CNN +F 3 "" H 2750 3550 60 0000 C CNN + 1 2750 3550 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4002_test v3 +U 1 1 5CF1D0EF +P 2750 3450 +F 0 "v3" H 2550 3550 60 0000 C CNN +F 1 "DC" H 2550 3400 60 0000 C CNN +F 2 "R1" H 2450 3450 60 0000 C CNN +F 3 "" H 2750 3450 60 0000 C CNN + 1 2750 3450 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4002_test v2 +U 1 1 5CF1D0C3 +P 2700 3350 +F 0 "v2" H 2500 3450 60 0000 C CNN +F 1 "DC" H 2500 3300 60 0000 C CNN +F 2 "R1" H 2400 3350 60 0000 C CNN +F 3 "" H 2700 3350 60 0000 C CNN + 1 2700 3350 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4002_test v1 +U 1 1 5CF1CE2E +P 2700 3250 +F 0 "v1" H 2500 3350 60 0000 C CNN +F 1 "DC" H 2500 3200 60 0000 C CNN +F 2 "R1" H 2400 3250 60 0000 C CNN +F 3 "" H 2700 3250 60 0000 C CNN + 1 2700 3250 + 0 1 1 0 +$EndComp +Connection ~ 6800 2300 +Wire Wire Line + 6750 2450 6800 2450 +Wire Wire Line + 6800 2450 6800 2400 +Connection ~ 6800 2400 +$EndSCHEMATC +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/analysis b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~HEAD index 660a46cc..660a46cc 100644 --- a/Examples/Analysis_Of_Digital_IC/4012_test/analysis +++ b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3 new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4002_test/analysis~fellowship2019-python3 @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib index b58b86b5..b21dbef3 100644 --- a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-cache.lib @@ -1,3 +1,4 @@ +<<<<<<< HEAD EESchema-LIBRARY Version 2.3
#encoding utf-8
#
@@ -120,3 +121,127 @@ ENDDRAW ENDDEF
#
#End Library
+======= +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4012 +# +DEF 4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# DC-RESCUE-4012_test +# +DEF DC-RESCUE-4012_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4012_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-rescue.lib new file mode 100644 index 00000000..5e7dc5c4 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test-rescue.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-4012_test +# +DEF DC-RESCUE-4012_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4012_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro index ee32c69b..8af698d3 100644 --- a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.pro @@ -1,3 +1,4 @@ +<<<<<<< HEAD update=06/01/19 15:09:21
version=1
last_client=eeschema
@@ -43,3 +44,50 @@ LibName9=eSim_PSpice LibName10=eSim_Sources
LibName11=eSim_User
LibName12=eSim_Subckt
+======= +update=Wed Mar 11 12:50:15 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../eSim/kicadSchematicLibrary +[eeschema/libraries] +LibName1=4012_test-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_Subckt +LibName11=eSim_Sources +LibName12=eSim_User +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch index 1380bb1d..28de6099 100644 --- a/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch +++ b/Examples/Analysis_Of_Digital_IC/4012_test/4012_test.sch @@ -1,3 +1,4 @@ +<<<<<<< HEAD EESchema Schematic File Version 2
LIBS:power
LIBS:eSim_Analog
@@ -499,3 +500,506 @@ Wire Wire Line 4800 1850 4800 2050
Connection ~ 4800 2050
$EndSCHEMATC
+======= +EESchema Schematic File Version 2 +LIBS:4012_test-rescue +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:4012_test-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4012 X1 +U 1 1 5CF22C85 +P 5050 4050 +F 0 "X1" H 5050 4050 60 0000 C CNN +F 1 "4012" H 5050 4250 60 0000 C CNN +F 2 "" H 5050 4050 60 0000 C CNN +F 3 "" H 5050 4050 60 0000 C CNN + 1 5050 4050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U5 +U 1 1 5CF24801 +P 3600 4050 +F 0 "U5" H 3600 4050 60 0000 C CNN +F 1 "adc_bridge_4" H 3600 4350 60 0000 C CNN +F 2 "" H 3600 4050 60 0000 C CNN +F 3 "" H 3600 4050 60 0000 C CNN + 1 3600 4050 + 1 0 0 -1 +$EndComp +NoConn ~ 4550 4350 +NoConn ~ 5600 3750 +$Comp +L DC-RESCUE-4012_test v1 +U 1 1 5CF2488C +P 1900 3450 +F 0 "v1" H 1700 3550 60 0000 C CNN +F 1 "DC" H 1700 3400 60 0000 C CNN +F 2 "R1" H 1600 3450 60 0000 C CNN +F 3 "" H 1900 3450 60 0000 C CNN + 1 1900 3450 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4012_test v2 +U 1 1 5CF248E2 +P 1900 4000 +F 0 "v2" H 1700 4100 60 0000 C CNN +F 1 "DC" H 1700 3950 60 0000 C CNN +F 2 "R1" H 1600 4000 60 0000 C CNN +F 3 "" H 1900 4000 60 0000 C CNN + 1 1900 4000 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4012_test v3 +U 1 1 5CF24906 +P 1900 4550 +F 0 "v3" H 1700 4650 60 0000 C CNN +F 1 "DC" H 1700 4500 60 0000 C CNN +F 2 "R1" H 1600 4550 60 0000 C CNN +F 3 "" H 1900 4550 60 0000 C CNN + 1 1900 4550 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4012_test v4 +U 1 1 5CF24935 +P 1900 5100 +F 0 "v4" H 1700 5200 60 0000 C CNN +F 1 "DC" H 1700 5050 60 0000 C CNN +F 2 "R1" H 1600 5100 60 0000 C CNN +F 3 "" H 1900 5100 60 0000 C CNN + 1 1900 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 2350 3450 2800 3450 +Wire Wire Line + 2800 3450 2800 3850 +Wire Wire Line + 2800 3850 3050 3850 +Wire Wire Line + 3050 3950 2350 3950 +Wire Wire Line + 2350 3950 2350 4000 +Wire Wire Line + 2350 4550 2700 4550 +Wire Wire Line + 2700 4550 2700 4050 +Wire Wire Line + 2700 4050 3050 4050 +Wire Wire Line + 3050 4150 3050 5100 +Wire Wire Line + 3050 5100 2350 5100 +Wire Wire Line + 1450 3450 1200 3450 +Wire Wire Line + 1200 3450 1200 5100 +Wire Wire Line + 1200 4000 1450 4000 +Wire Wire Line + 1200 4550 1450 4550 +Connection ~ 1200 4000 +Wire Wire Line + 1200 5100 1450 5100 +Connection ~ 1200 4550 +$Comp +L adc_bridge_4 U9 +U 1 1 5CF24B4A +P 6450 4050 +F 0 "U9" H 6450 4050 60 0000 C CNN +F 1 "adc_bridge_4" H 6450 4350 60 0000 C CNN +F 2 "" H 6450 4050 60 0000 C CNN +F 3 "" H 6450 4050 60 0000 C CNN + 1 6450 4050 + -1 0 0 1 +$EndComp +$Comp +L DC-RESCUE-4012_test v8 +U 1 1 5CF24B50 +P 8150 4650 +F 0 "v8" H 7950 4750 60 0000 C CNN +F 1 "DC" H 7950 4600 60 0000 C CNN +F 2 "R1" H 7850 4650 60 0000 C CNN +F 3 "" H 8150 4650 60 0000 C CNN + 1 8150 4650 + 0 -1 -1 0 +$EndComp +$Comp +L DC-RESCUE-4012_test v7 +U 1 1 5CF24B56 +P 8150 4100 +F 0 "v7" H 7950 4200 60 0000 C CNN +F 1 "DC" H 7950 4050 60 0000 C CNN +F 2 "R1" H 7850 4100 60 0000 C CNN +F 3 "" H 8150 4100 60 0000 C CNN + 1 8150 4100 + 0 -1 -1 0 +$EndComp +$Comp +L DC-RESCUE-4012_test v6 +U 1 1 5CF24B5C +P 8150 3550 +F 0 "v6" H 7950 3650 60 0000 C CNN +F 1 "DC" H 7950 3500 60 0000 C CNN +F 2 "R1" H 7850 3550 60 0000 C CNN +F 3 "" H 8150 3550 60 0000 C CNN + 1 8150 3550 + 0 -1 -1 0 +$EndComp +$Comp +L DC-RESCUE-4012_test v5 +U 1 1 5CF24B62 +P 8150 3000 +F 0 "v5" H 7950 3100 60 0000 C CNN +F 1 "DC" H 7950 2950 60 0000 C CNN +F 2 "R1" H 7850 3000 60 0000 C CNN +F 3 "" H 8150 3000 60 0000 C CNN + 1 8150 3000 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7700 4650 7250 4650 +Wire Wire Line + 7250 4650 7250 4250 +Wire Wire Line + 7250 4250 7000 4250 +Wire Wire Line + 7000 4150 7700 4150 +Wire Wire Line + 7700 4150 7700 4100 +Wire Wire Line + 7700 3550 7350 3550 +Wire Wire Line + 7350 3400 7350 4050 +Wire Wire Line + 7350 4050 7000 4050 +Wire Wire Line + 7000 3950 7000 3000 +Wire Wire Line + 7000 3000 7700 3000 +Wire Wire Line + 8600 4650 8850 4650 +Wire Wire Line + 8850 4650 8850 3000 +Wire Wire Line + 8850 4100 8600 4100 +Wire Wire Line + 8850 3550 8600 3550 +Connection ~ 8850 4100 +Wire Wire Line + 8850 3000 8600 3000 +Connection ~ 8850 3550 +Wire Wire Line + 5900 3950 5600 3950 +Wire Wire Line + 5600 4050 5900 4050 +Wire Wire Line + 5600 4150 5900 4150 +Wire Wire Line + 5600 4250 5900 4250 +Wire Wire Line + 4550 3850 4150 3850 +Wire Wire Line + 4150 3950 4550 3950 +Wire Wire Line + 4150 4050 4550 4050 +Wire Wire Line + 4550 4150 4150 4150 +$Comp +L plot_v1 U1 +U 1 1 5CF2512D +P 2400 3300 +F 0 "U1" H 2400 3800 60 0000 C CNN +F 1 "plot_v1" H 2600 3650 60 0000 C CNN +F 2 "" H 2400 3300 60 0000 C CNN +F 3 "" H 2400 3300 60 0000 C CNN + 1 2400 3300 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5CF25268 +P 3000 3450 +F 0 "U3" H 3000 3950 60 0000 C CNN +F 1 "plot_v1" H 3200 3800 60 0000 C CNN +F 2 "" H 3000 3450 60 0000 C CNN +F 3 "" H 3000 3450 60 0000 C CNN + 1 3000 3450 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5CF252A7 +P 3050 4600 +F 0 "U4" H 3050 5100 60 0000 C CNN +F 1 "plot_v1" H 3250 4950 60 0000 C CNN +F 2 "" H 3050 4600 60 0000 C CNN +F 3 "" H 3050 4600 60 0000 C CNN + 1 3050 4600 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 5CF25311 +P 2900 5100 +F 0 "U2" H 2900 5600 60 0000 C CNN +F 1 "plot_v1" H 3100 5450 60 0000 C CNN +F 2 "" H 2900 5100 60 0000 C CNN +F 3 "" H 2900 5100 60 0000 C CNN + 1 2900 5100 + -1 0 0 1 +$EndComp +Wire Wire Line + 2400 3100 2400 3450 +Connection ~ 2400 3450 +Wire Wire Line + 3000 3250 3000 3550 +Wire Wire Line + 3000 3550 2700 3550 +Wire Wire Line + 2700 3550 2700 3950 +Connection ~ 2700 3950 +Wire Wire Line + 2700 4450 3250 4450 +Wire Wire Line + 3250 4450 3250 4600 +Connection ~ 2700 4450 +Wire Wire Line + 2900 5100 2900 5300 +Connection ~ 2900 5100 +Wire Wire Line + 1200 4250 850 4250 +Wire Wire Line + 850 4150 850 4500 +Connection ~ 1200 4250 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5CF254BC +P 850 4150 +F 0 "#FLG01" H 850 4245 50 0001 C CNN +F 1 "PWR_FLAG" H 850 4330 50 0000 C CNN +F 2 "" H 850 4150 50 0000 C CNN +F 3 "" H 850 4150 50 0000 C CNN + 1 850 4150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR02 +U 1 1 5CF254EE +P 850 4500 +F 0 "#PWR02" H 850 4250 50 0001 C CNN +F 1 "eSim_GND" H 850 4350 50 0000 C CNN +F 2 "" H 850 4500 50 0001 C CNN +F 3 "" H 850 4500 50 0001 C CNN + 1 850 4500 + 1 0 0 -1 +$EndComp +Connection ~ 850 4250 +Text GLabel 2300 3250 0 60 Input ~ 0 +a1 +Text GLabel 2900 3350 0 60 Input ~ 0 +b1 +Text GLabel 2900 4550 3 60 Input ~ 0 +c1 +Text GLabel 2800 5200 0 60 Input ~ 0 +d1 +Wire Wire Line + 2800 5200 2900 5200 +Connection ~ 2900 5200 +Wire Wire Line + 2900 4450 2900 4550 +Connection ~ 2900 4450 +Wire Wire Line + 2900 3350 3000 3350 +Connection ~ 3000 3350 +Wire Wire Line + 2300 3250 2400 3250 +Connection ~ 2400 3250 +$Comp +L plot_v1 U11 +U 1 1 5CF2581B +P 7200 3000 +F 0 "U11" H 7200 3500 60 0000 C CNN +F 1 "plot_v1" H 7400 3350 60 0000 C CNN +F 2 "" H 7200 3000 60 0000 C CNN +F 3 "" H 7200 3000 60 0000 C CNN + 1 7200 3000 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U10 +U 1 1 5CF25889 +P 6500 3450 +F 0 "U10" H 6500 3950 60 0000 C CNN +F 1 "plot_v1" H 6700 3800 60 0000 C CNN +F 2 "" H 6500 3450 60 0000 C CNN +F 3 "" H 6500 3450 60 0000 C CNN + 1 6500 3450 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U13 +U 1 1 5CF258F2 +P 7550 4750 +F 0 "U13" H 7550 5250 60 0000 C CNN +F 1 "plot_v1" H 7750 5100 60 0000 C CNN +F 2 "" H 7550 4750 60 0000 C CNN +F 3 "" H 7550 4750 60 0000 C CNN + 1 7550 4750 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 5CF2597E +P 7200 4800 +F 0 "U12" H 7200 5300 60 0000 C CNN +F 1 "plot_v1" H 7400 5150 60 0000 C CNN +F 2 "" H 7200 4800 60 0000 C CNN +F 3 "" H 7200 4800 60 0000 C CNN + 1 7200 4800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7550 4950 7550 4650 +Connection ~ 7550 4650 +Wire Wire Line + 7000 4800 7150 4800 +Wire Wire Line + 7150 4800 7150 4150 +Connection ~ 7150 4150 +Wire Wire Line + 7200 2800 7200 3400 +Wire Wire Line + 7200 3400 7350 3400 +Connection ~ 7350 3550 +Wire Wire Line + 6500 3250 6500 3450 +Wire Wire Line + 6500 3450 7000 3450 +Connection ~ 7000 3450 +Wire Wire Line + 8850 3800 9450 3800 +Wire Wire Line + 9450 3800 9450 4150 +Connection ~ 8850 3800 +$Comp +L eSim_GND #PWR03 +U 1 1 5CF25F3B +P 9450 4150 +F 0 "#PWR03" H 9450 3900 50 0001 C CNN +F 1 "eSim_GND" H 9450 4000 50 0000 C CNN +F 2 "" H 9450 4150 50 0001 C CNN +F 3 "" H 9450 4150 50 0001 C CNN + 1 9450 4150 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U7 +U 1 1 5CF26149 +P 5050 2800 +F 0 "U7" H 5050 2800 60 0000 C CNN +F 1 "dac_bridge_2" H 5100 2950 60 0000 C CNN +F 2 "" H 5050 2800 60 0000 C CNN +F 3 "" H 5050 2800 60 0000 C CNN + 1 5050 2800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4550 3250 4550 3750 +Wire Wire Line + 4550 3250 5000 3250 +Wire Wire Line + 5100 3250 5800 3250 +Wire Wire Line + 5800 3250 5800 3850 +Wire Wire Line + 5800 3850 5600 3850 +$Comp +L plot_v1 U8 +U 1 1 5CF263AC +P 5400 2000 +F 0 "U8" H 5400 2500 60 0000 C CNN +F 1 "plot_v1" H 5600 2350 60 0000 C CNN +F 2 "" H 5400 2000 60 0000 C CNN +F 3 "" H 5400 2000 60 0000 C CNN + 1 5400 2000 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5CF26445 +P 4800 2050 +F 0 "U6" H 4800 2550 60 0000 C CNN +F 1 "plot_v1" H 5000 2400 60 0000 C CNN +F 2 "" H 4800 2050 60 0000 C CNN +F 3 "" H 4800 2050 60 0000 C CNN + 1 4800 2050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5000 2250 5000 2050 +Wire Wire Line + 5000 2050 4600 2050 +Wire Wire Line + 5100 2250 5100 2000 +Wire Wire Line + 5100 2000 5600 2000 +Text GLabel 4800 1850 1 60 Output ~ 0 +q1 +Text GLabel 5400 1850 1 60 Output ~ 0 +q2 +Text GLabel 7350 2900 2 60 Input ~ 0 +d2 +Text GLabel 6800 3350 1 60 Input ~ 0 +c2 +Text GLabel 7100 4500 0 60 Input ~ 0 +b2 +Text GLabel 7450 4800 0 60 Input ~ 0 +a2 +Wire Wire Line + 7450 4800 7550 4800 +Connection ~ 7550 4800 +Wire Wire Line + 7100 4500 7150 4500 +Connection ~ 7150 4500 +Wire Wire Line + 6800 3350 6800 3450 +Connection ~ 6800 3450 +Wire Wire Line + 7350 2900 7200 2900 +Connection ~ 7200 2900 +Wire Wire Line + 5400 1850 5400 2000 +Connection ~ 5400 2000 +Wire Wire Line + 4800 1850 4800 2050 +Connection ~ 4800 2050 +$EndSCHEMATC +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/analysis~HEAD b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~HEAD new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~HEAD @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4012_test/analysis~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~fellowship2019-python3 new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4012_test/analysis~fellowship2019-python3 @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~HEAD index 0a3ccf7f..0a3ccf7f 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3 new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and-cache.lib~fellowship2019-python3 @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~HEAD index e3c96645..e3c96645 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3 new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir.out~fellowship2019-python3 @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD index 15f8954d..15f8954d 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3 new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.cir~fellowship2019-python3 @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~HEAD index 0fdf4d25..0fdf4d25 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3 new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.pro~fellowship2019-python3 @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~HEAD index c853bf49..c853bf49 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3 new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sch~fellowship2019-python3 @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD index b949ae4f..b949ae4f 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3 new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and.sub~fellowship2019-python3 @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~HEAD index abc5faaa..abc5faaa 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3 new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/3_and_Previous_Values.xml~fellowship2019-python3 @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib index 725472f5..9fb7bb13 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-cache.lib @@ -1,3 +1,4 @@ +<<<<<<< HEAD EESchema-LIBRARY Version 2.3
#encoding utf-8
#
@@ -120,3 +121,127 @@ ENDDRAW ENDDEF
#
#End Library
+======= +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4023 +# +DEF 4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# DC-RESCUE-4023_test +# +DEF DC-RESCUE-4023_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4023_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_3 +# +DEF dac_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-rescue.lib new file mode 100644 index 00000000..63440d3e --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test-rescue.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-4023_test +# +DEF DC-RESCUE-4023_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4023_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro index e4c3c722..ec355936 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.pro @@ -1,3 +1,4 @@ +<<<<<<< HEAD update=06/01/19 15:31:12
version=1
last_client=eeschema
@@ -43,3 +44,50 @@ LibName9=eSim_PSpice LibName10=eSim_Sources
LibName11=eSim_Subckt
LibName12=eSim_User
+======= +update=Wed Mar 11 12:47:38 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../eSim/kicadSchematicLibrary +[eeschema/libraries] +LibName1=4023_test-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_User +LibName11=eSim_Sources +LibName12=eSim_Subckt +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch index 37e50cf7..b1661fee 100644 --- a/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch +++ b/Examples/Analysis_Of_Digital_IC/4023_test/4023_test.sch @@ -1,3 +1,4 @@ +<<<<<<< HEAD EESchema Schematic File Version 2
LIBS:power
LIBS:eSim_Analog
@@ -573,3 +574,581 @@ Wire Wire Line 3050 5150 3050 5000
Connection ~ 3050 5000
$EndSCHEMATC
+======= +EESchema Schematic File Version 2 +LIBS:4023_test-rescue +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4023_test-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4023 X1 +U 1 1 5CF24CF9 +P 5300 3900 +F 0 "X1" H 5300 3800 60 0000 C CNN +F 1 "4023" H 5300 4000 60 0000 C CNN +F 2 "" H 5300 3900 60 0000 C CNN +F 3 "" H 5300 3900 60 0000 C CNN + 1 5300 3900 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U8 +U 1 1 5CF24D5D +P 3450 4500 +F 0 "U8" H 3450 4500 60 0000 C CNN +F 1 "adc_bridge_3" H 3450 4650 60 0000 C CNN +F 2 "" H 3450 4500 60 0000 C CNN +F 3 "" H 3450 4500 60 0000 C CNN + 1 3450 4500 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U7 +U 1 1 5CF24DB6 +P 3400 2850 +F 0 "U7" H 3400 2850 60 0000 C CNN +F 1 "adc_bridge_3" H 3400 3000 60 0000 C CNN +F 2 "" H 3400 2850 60 0000 C CNN +F 3 "" H 3400 2850 60 0000 C CNN + 1 3400 2850 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_3 U10 +U 1 1 5CF24DFF +P 7000 3750 +F 0 "U10" H 7000 3750 60 0000 C CNN +F 1 "adc_bridge_3" H 7000 3900 60 0000 C CNN +F 2 "" H 7000 3750 60 0000 C CNN +F 3 "" H 7000 3750 60 0000 C CNN + 1 7000 3750 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_3 U9 +U 1 1 5CF24ECA +P 6800 5750 +F 0 "U9" H 6800 5750 60 0000 C CNN +F 1 "dac_bridge_3" H 6800 5900 60 0000 C CNN +F 2 "" H 6800 5750 60 0000 C CNN +F 3 "" H 6800 5750 60 0000 C CNN + 1 6800 5750 + 1 0 0 -1 +$EndComp +$Comp +L DC-RESCUE-4023_test v1 +U 1 1 5CF24F1F +P 1700 2350 +F 0 "v1" H 1500 2450 60 0000 C CNN +F 1 "DC" H 1500 2300 60 0000 C CNN +F 2 "R1" H 1400 2350 60 0000 C CNN +F 3 "" H 1700 2350 60 0000 C CNN + 1 1700 2350 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4023_test v2 +U 1 1 5CF24F90 +P 1700 2900 +F 0 "v2" H 1500 3000 60 0000 C CNN +F 1 "DC" H 1500 2850 60 0000 C CNN +F 2 "R1" H 1400 2900 60 0000 C CNN +F 3 "" H 1700 2900 60 0000 C CNN + 1 1700 2900 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4023_test v3 +U 1 1 5CF24FC7 +P 1700 3450 +F 0 "v3" H 1500 3550 60 0000 C CNN +F 1 "DC" H 1500 3400 60 0000 C CNN +F 2 "R1" H 1400 3450 60 0000 C CNN +F 3 "" H 1700 3450 60 0000 C CNN + 1 1700 3450 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4023_test v4 +U 1 1 5CF25001 +P 1750 4000 +F 0 "v4" H 1550 4100 60 0000 C CNN +F 1 "DC" H 1550 3950 60 0000 C CNN +F 2 "R1" H 1450 4000 60 0000 C CNN +F 3 "" H 1750 4000 60 0000 C CNN + 1 1750 4000 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4023_test v5 +U 1 1 5CF25044 +P 1750 4550 +F 0 "v5" H 1550 4650 60 0000 C CNN +F 1 "DC" H 1550 4500 60 0000 C CNN +F 2 "R1" H 1450 4550 60 0000 C CNN +F 3 "" H 1750 4550 60 0000 C CNN + 1 1750 4550 + 0 1 1 0 +$EndComp +$Comp +L DC-RESCUE-4023_test v6 +U 1 1 5CF25082 +P 1750 5050 +F 0 "v6" H 1550 5150 60 0000 C CNN +F 1 "DC" H 1550 5000 60 0000 C CNN +F 2 "R1" H 1450 5050 60 0000 C CNN +F 3 "" H 1750 5050 60 0000 C CNN + 1 1750 5050 + 0 1 1 0 +$EndComp +Wire Wire Line + 2800 2800 2800 2350 +Wire Wire Line + 2800 2350 2150 2350 +Wire Wire Line + 2150 2900 2800 2900 +Wire Wire Line + 2150 3450 2800 3450 +Wire Wire Line + 2800 3450 2800 3000 +Wire Wire Line + 2200 4000 2850 4000 +Wire Wire Line + 2850 3900 2850 4450 +Wire Wire Line + 2850 4550 2200 4550 +Wire Wire Line + 2200 5050 2850 5050 +Wire Wire Line + 2850 5050 2850 4650 +Wire Wire Line + 900 5050 1300 5050 +Wire Wire Line + 900 2350 900 5050 +Wire Wire Line + 900 2350 1250 2350 +Wire Wire Line + 1250 2900 900 2900 +Connection ~ 900 2900 +Wire Wire Line + 1250 3450 900 3450 +Connection ~ 900 3450 +Wire Wire Line + 1300 4000 900 4000 +Connection ~ 900 4000 +Wire Wire Line + 1300 4550 900 4550 +Connection ~ 900 4550 +Wire Wire Line + 3950 2800 4500 2800 +Wire Wire Line + 4500 2800 4500 3600 +Wire Wire Line + 4500 3600 4800 3600 +Wire Wire Line + 3950 2900 4400 2900 +Wire Wire Line + 4400 2900 4400 3700 +Wire Wire Line + 4400 3700 4800 3700 +Wire Wire Line + 3950 3000 5900 3000 +Wire Wire Line + 5900 3000 5900 4200 +Wire Wire Line + 5900 4200 5800 4200 +Wire Wire Line + 6450 3900 5800 3900 +Wire Wire Line + 5800 3800 6450 3800 +Wire Wire Line + 6450 3700 5800 3700 +Wire Wire Line + 4000 4450 4000 3800 +Wire Wire Line + 4000 3800 4800 3800 +Wire Wire Line + 4800 3900 4100 3900 +Wire Wire Line + 4100 3900 4100 4550 +Wire Wire Line + 4100 4550 4000 4550 +Wire Wire Line + 4000 4650 4200 4650 +Wire Wire Line + 4200 4650 4200 4000 +Wire Wire Line + 4200 4000 4800 4000 +Wire Wire Line + 4800 4100 4450 4100 +Wire Wire Line + 4450 4100 4450 5800 +Wire Wire Line + 4450 5800 6200 5800 +Wire Wire Line + 5800 4100 5850 4100 +Wire Wire Line + 5850 4100 5850 5700 +Wire Wire Line + 5850 5700 6200 5700 +Wire Wire Line + 5800 4000 5950 4000 +Wire Wire Line + 5950 4000 5950 5900 +Wire Wire Line + 5950 5900 6200 5900 +$Comp +L DC-RESCUE-4023_test v7 +U 1 1 5CF25804 +P 9250 3250 +F 0 "v7" H 9050 3350 60 0000 C CNN +F 1 "DC" H 9050 3200 60 0000 C CNN +F 2 "R1" H 8950 3250 60 0000 C CNN +F 3 "" H 9250 3250 60 0000 C CNN + 1 9250 3250 + 0 -1 1 0 +$EndComp +$Comp +L DC-RESCUE-4023_test v8 +U 1 1 5CF2580A +P 9250 3800 +F 0 "v8" H 9050 3900 60 0000 C CNN +F 1 "DC" H 9050 3750 60 0000 C CNN +F 2 "R1" H 8950 3800 60 0000 C CNN +F 3 "" H 9250 3800 60 0000 C CNN + 1 9250 3800 + 0 -1 1 0 +$EndComp +$Comp +L DC-RESCUE-4023_test v9 +U 1 1 5CF25810 +P 9250 4300 +F 0 "v9" H 9050 4400 60 0000 C CNN +F 1 "DC" H 9050 4250 60 0000 C CNN +F 2 "R1" H 8950 4300 60 0000 C CNN +F 3 "" H 9250 4300 60 0000 C CNN + 1 9250 4300 + 0 -1 1 0 +$EndComp +Wire Wire Line + 7600 3250 8800 3250 +Wire Wire Line + 7600 3800 8800 3800 +Wire Wire Line + 7600 4300 8800 4300 +Wire Wire Line + 10150 4300 9700 4300 +Wire Wire Line + 9700 3250 10150 3250 +Wire Wire Line + 9700 3800 10500 3800 +Wire Wire Line + 7600 3250 7600 3700 +Wire Wire Line + 7600 4300 7600 3900 +Wire Wire Line + 10150 3250 10150 4300 +Connection ~ 10150 3800 +Wire Wire Line + 10500 3800 10500 4050 +NoConn ~ 5800 3600 +NoConn ~ 4800 4200 +$Comp +L plot_v1 U16 +U 1 1 5CF25B68 +P 8450 3050 +F 0 "U16" H 8450 3550 60 0000 C CNN +F 1 "plot_v1" H 8650 3400 60 0000 C CNN +F 2 "" H 8450 3050 60 0000 C CNN +F 3 "" H 8450 3050 60 0000 C CNN + 1 8450 3050 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 5CF25BF8 +P 7750 3100 +F 0 "U12" H 7750 3600 60 0000 C CNN +F 1 "plot_v1" H 7950 3450 60 0000 C CNN +F 2 "" H 7750 3100 60 0000 C CNN +F 3 "" H 7750 3100 60 0000 C CNN + 1 7750 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U14 +U 1 1 5CF25C4E +P 8050 4300 +F 0 "U14" H 8050 4800 60 0000 C CNN +F 1 "plot_v1" H 8250 4650 60 0000 C CNN +F 2 "" H 8050 4300 60 0000 C CNN +F 3 "" H 8050 4300 60 0000 C CNN + 1 8050 4300 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 5CF25E02 +P 2450 5100 +F 0 "U2" H 2450 5600 60 0000 C CNN +F 1 "plot_v1" H 2650 5450 60 0000 C CNN +F 2 "" H 2450 5100 60 0000 C CNN +F 3 "" H 2450 5100 60 0000 C CNN + 1 2450 5100 + -1 0 0 1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5CF25F10 +P 3000 5000 +F 0 "U5" H 3000 5500 60 0000 C CNN +F 1 "plot_v1" H 3200 5350 60 0000 C CNN +F 2 "" H 3000 5000 60 0000 C CNN +F 3 "" H 3000 5000 60 0000 C CNN + 1 3000 5000 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5CF25F95 +P 2950 3900 +F 0 "U4" H 2950 4400 60 0000 C CNN +F 1 "plot_v1" H 3150 4250 60 0000 C CNN +F 2 "" H 2950 3900 60 0000 C CNN +F 3 "" H 2950 3900 60 0000 C CNN + 1 2950 3900 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5CF25FFB +P 2850 3250 +F 0 "U3" H 2850 3750 60 0000 C CNN +F 1 "plot_v1" H 3050 3600 60 0000 C CNN +F 2 "" H 2850 3250 60 0000 C CNN +F 3 "" H 2850 3250 60 0000 C CNN + 1 2850 3250 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5CF260BA +P 3100 2400 +F 0 "U6" H 3100 2900 60 0000 C CNN +F 1 "plot_v1" H 3300 2750 60 0000 C CNN +F 2 "" H 3100 2400 60 0000 C CNN +F 3 "" H 3100 2400 60 0000 C CNN + 1 3100 2400 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 5CF26164 +P 2400 2300 +F 0 "U1" H 2400 2800 60 0000 C CNN +F 1 "plot_v1" H 2600 2650 60 0000 C CNN +F 2 "" H 2400 2300 60 0000 C CNN +F 3 "" H 2400 2300 60 0000 C CNN + 1 2400 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 5CF261BC +P 700 3900 +F 0 "#PWR01" H 700 3650 50 0001 C CNN +F 1 "eSim_GND" H 700 3750 50 0000 C CNN +F 2 "" H 700 3900 50 0001 C CNN +F 3 "" H 700 3900 50 0001 C CNN + 1 700 3900 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5CF262FB +P 700 3700 +F 0 "#FLG02" H 700 3795 50 0001 C CNN +F 1 "PWR_FLAG" H 700 3880 50 0000 C CNN +F 2 "" H 700 3700 50 0000 C CNN +F 3 "" H 700 3700 50 0000 C CNN + 1 700 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 700 3700 700 3900 +Wire Wire Line + 700 3800 900 3800 +Connection ~ 900 3800 +Connection ~ 700 3800 +Wire Wire Line + 3100 2200 3100 2450 +Wire Wire Line + 3100 2450 2800 2450 +Connection ~ 2800 2450 +Wire Wire Line + 2400 2100 2400 2900 +Connection ~ 2400 2900 +Wire Wire Line + 3050 3250 2800 3250 +Connection ~ 2800 3250 +Wire Wire Line + 3150 3900 2850 3900 +Connection ~ 2850 4000 +Wire Wire Line + 3200 5000 2850 5000 +Connection ~ 2850 5000 +Wire Wire Line + 2450 5300 2450 4550 +Connection ~ 2450 4550 +Wire Wire Line + 7750 2900 7750 3250 +Connection ~ 7750 3250 +Wire Wire Line + 8450 2850 8450 3800 +Connection ~ 8450 3800 +Wire Wire Line + 8050 4500 8050 4300 +Connection ~ 8050 4300 +$Comp +L eSim_GND #PWR03 +U 1 1 5CF26B7B +P 10500 4050 +F 0 "#PWR03" H 10500 3800 50 0001 C CNN +F 1 "eSim_GND" H 10500 3900 50 0000 C CNN +F 2 "" H 10500 4050 50 0001 C CNN +F 3 "" H 10500 4050 50 0001 C CNN + 1 10500 4050 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U13 +U 1 1 5CF26CF6 +P 7900 6100 +F 0 "U13" H 7900 6600 60 0000 C CNN +F 1 "plot_v1" H 8100 6450 60 0000 C CNN +F 2 "" H 7900 6100 60 0000 C CNN +F 3 "" H 7900 6100 60 0000 C CNN + 1 7900 6100 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U15 +U 1 1 5CF26DF2 +P 8250 5700 +F 0 "U15" H 8250 6200 60 0000 C CNN +F 1 "plot_v1" H 8450 6050 60 0000 C CNN +F 2 "" H 8250 5700 60 0000 C CNN +F 3 "" H 8250 5700 60 0000 C CNN + 1 8250 5700 + 0 1 1 0 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 5CF26E57 +P 7600 5200 +F 0 "U11" H 7600 5700 60 0000 C CNN +F 1 "plot_v1" H 7800 5550 60 0000 C CNN +F 2 "" H 7600 5200 60 0000 C CNN +F 3 "" H 7600 5200 60 0000 C CNN + 1 7600 5200 + 0 1 1 0 +$EndComp +Wire Wire Line + 7800 5200 7350 5200 +Wire Wire Line + 7350 5200 7350 5700 +Wire Wire Line + 7350 5800 7850 5800 +Wire Wire Line + 7850 5800 7850 5700 +Wire Wire Line + 7850 5700 8450 5700 +Wire Wire Line + 7350 5900 7650 5900 +Wire Wire Line + 7650 5900 7650 6100 +Wire Wire Line + 7450 6100 8100 6100 +Text GLabel 7200 5300 0 60 Input ~ 0 +q1 +Text GLabel 7700 5650 1 60 Input ~ 0 +q2 +Text GLabel 7450 6100 0 60 Input ~ 0 +q3 +Text GLabel 7900 4400 0 60 Input ~ 0 +c3 +Text GLabel 8300 3500 0 60 Input ~ 0 +b3 +Text GLabel 7600 3050 0 60 Input ~ 0 +a3 +Wire Wire Line + 7550 3050 7750 3050 +Connection ~ 7750 3050 +Wire Wire Line + 8300 3500 8450 3500 +Connection ~ 8450 3500 +Wire Wire Line + 7900 4400 8050 4400 +Connection ~ 8050 4400 +Wire Wire Line + 7200 5300 7350 5300 +Connection ~ 7350 5300 +Wire Wire Line + 7700 5650 7700 5800 +Connection ~ 7700 5800 +Connection ~ 7650 6100 +Text GLabel 2350 4750 0 60 Input ~ 0 +b2 +Text GLabel 3050 5150 3 60 Input ~ 0 +c2 +Text GLabel 3000 4000 3 60 Input ~ 0 +a2 +Text GLabel 2950 3400 3 60 Input ~ 0 +c1 +Text GLabel 2250 2650 0 60 Input ~ 0 +b1 +Text GLabel 3000 2300 0 60 Input ~ 0 +a1 +Wire Wire Line + 3000 2300 3100 2300 +Connection ~ 3100 2300 +Wire Wire Line + 2250 2650 2400 2650 +Connection ~ 2400 2650 +Wire Wire Line + 2950 3400 2950 3250 +Connection ~ 2950 3250 +Wire Wire Line + 3000 4000 3000 3900 +Connection ~ 3000 3900 +Wire Wire Line + 2350 4750 2450 4750 +Connection ~ 2450 4750 +Wire Wire Line + 3050 5150 3050 5000 +Connection ~ 3050 5000 +$EndSCHEMATC +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib index 43241731..cd34331d 100644 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib @@ -1,3 +1,4 @@ +<<<<<<< HEAD EESchema-LIBRARY Version 2.3
#encoding utf-8
#
@@ -150,3 +151,157 @@ ENDDRAW ENDDEF
#
#End Library
+======= +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4028 +# +DEF 4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# DC-RESCUE-4028_test +# +DEF DC-RESCUE-4028_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4028_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_GND +# +DEF eSim_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "eSim_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-rescue.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-rescue.lib new file mode 100644 index 00000000..214f1f4c --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-rescue.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-4028_test +# +DEF DC-RESCUE-4028_test v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4028_test" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro index dc708582..170c38f4 100644 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro @@ -1,3 +1,4 @@ +<<<<<<< HEAD update=06/01/19 16:07:13
version=1
last_client=eeschema
@@ -42,3 +43,50 @@ LibName8=eSim_Power LibName9=eSim_Sources
LibName10=eSim_Subckt
LibName11=eSim_User
+======= +update=Wed Mar 11 12:51:14 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../eSim/kicadSchematicLibrary +[eeschema/libraries] +LibName1=4028_test-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch index 53226145..ba22945c 100644 --- a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch @@ -1,3 +1,4 @@ +<<<<<<< HEAD EESchema Schematic File Version 2
LIBS:power
LIBS:eSim_Analog
@@ -549,3 +550,558 @@ Wire Wire Line 2000 1950 2000 2100
Connection ~ 2000 2100
$EndSCHEMATC
+======= +EESchema Schematic File Version 2 +LIBS:4028_test-rescue +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4028_test-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 4028 X1 +U 1 1 5CF25569 +P 5600 4300 +F 0 "X1" H 5600 4200 60 0000 C CNN +F 1 "4028" H 5600 4350 60 0000 C CNN +F 2 "" H 5600 4300 60 0000 C CNN +F 3 "" H 5600 4300 60 0000 C CNN + 1 5600 4300 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_4 U13 +U 1 1 5CF25781 +P 7300 4350 +F 0 "U13" H 7300 4350 60 0000 C CNN +F 1 "adc_bridge_4" H 7300 4650 60 0000 C CNN +F 2 "" H 7300 4350 60 0000 C CNN +F 3 "" H 7300 4350 60 0000 C CNN + 1 7300 4350 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_8 U11 +U 1 1 5CF257F0 +P 3750 3950 +F 0 "U11" H 3750 3950 60 0000 C CNN +F 1 "dac_bridge_8" H 3750 4100 60 0000 C CNN +F 2 "" H 3750 3950 60 0000 C CNN +F 3 "" H 3750 3950 60 0000 C CNN + 1 3750 3950 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U12 +U 1 1 5CF258CD +P 3800 5050 +F 0 "U12" H 3800 5050 60 0000 C CNN +F 1 "dac_bridge_2" H 3850 5200 60 0000 C CNN +F 2 "" H 3800 5050 60 0000 C CNN +F 3 "" H 3800 5050 60 0000 C CNN + 1 3800 5050 + -1 0 0 -1 +$EndComp +$Comp +L DC-RESCUE-4028_test v2 +U 1 1 5CF25946 +P 9400 3950 +F 0 "v2" H 9200 4050 60 0000 C CNN +F 1 "DC" H 9200 3900 60 0000 C CNN +F 2 "R1" H 9100 3950 60 0000 C CNN +F 3 "" H 9400 3950 60 0000 C CNN + 1 9400 3950 + 0 -1 -1 0 +$EndComp +$Comp +L DC-RESCUE-4028_test v1 +U 1 1 5CF259A4 +P 9400 3400 +F 0 "v1" H 9200 3500 60 0000 C CNN +F 1 "DC" H 9200 3350 60 0000 C CNN +F 2 "R1" H 9100 3400 60 0000 C CNN +F 3 "" H 9400 3400 60 0000 C CNN + 1 9400 3400 + 0 -1 -1 0 +$EndComp +$Comp +L DC-RESCUE-4028_test v3 +U 1 1 5CF259F8 +P 9400 4500 +F 0 "v3" H 9200 4600 60 0000 C CNN +F 1 "DC" H 9200 4450 60 0000 C CNN +F 2 "R1" H 9100 4500 60 0000 C CNN +F 3 "" H 9400 4500 60 0000 C CNN + 1 9400 4500 + 0 -1 -1 0 +$EndComp +$Comp +L DC-RESCUE-4028_test v4 +U 1 1 5CF25A37 +P 9450 5000 +F 0 "v4" H 9250 5100 60 0000 C CNN +F 1 "DC" H 9250 4950 60 0000 C CNN +F 2 "R1" H 9150 5000 60 0000 C CNN +F 3 "" H 9450 5000 60 0000 C CNN + 1 9450 5000 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_GND #PWR01 +U 1 1 5CF25C11 +P 10200 4450 +F 0 "#PWR01" H 10200 4200 50 0001 C CNN +F 1 "eSim_GND" H 10200 4300 50 0000 C CNN +F 2 "" H 10200 4450 50 0001 C CNN +F 3 "" H 10200 4450 50 0001 C CNN + 1 10200 4450 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG02 +U 1 1 5CF25C75 +P 10200 4100 +F 0 "#FLG02" H 10200 4195 50 0001 C CNN +F 1 "PWR_FLAG" H 10200 4280 50 0000 C CNN +F 2 "" H 10200 4100 50 0000 C CNN +F 3 "" H 10200 4100 50 0000 C CNN + 1 10200 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8950 3400 8500 3400 +Wire Wire Line + 8500 3400 8500 4150 +Wire Wire Line + 8500 4150 7850 4150 +Wire Wire Line + 8600 4250 7850 4250 +Wire Wire Line + 8600 3050 8600 4250 +Wire Wire Line + 8600 3950 8950 3950 +Wire Wire Line + 8950 4500 8500 4500 +Wire Wire Line + 8500 4500 8500 4350 +Wire Wire Line + 8500 4350 7850 4350 +Wire Wire Line + 7850 4450 8200 4450 +Wire Wire Line + 8200 4450 8200 5000 +Wire Wire Line + 8200 5000 9000 5000 +Wire Wire Line + 9900 3400 9900 5000 +Wire Wire Line + 9900 3400 9850 3400 +Wire Wire Line + 9850 3950 9900 3950 +Connection ~ 9900 3950 +Wire Wire Line + 9850 4500 9900 4500 +Connection ~ 9900 4500 +Wire Wire Line + 9900 4200 10200 4200 +Wire Wire Line + 10200 4100 10200 4450 +Connection ~ 9900 4200 +Connection ~ 10200 4200 +Wire Wire Line + 5100 4150 4750 4150 +Wire Wire Line + 4750 4150 4750 3900 +Wire Wire Line + 4750 3900 4350 3900 +Wire Wire Line + 6100 4150 6200 4150 +Wire Wire Line + 6200 4150 6200 3700 +Wire Wire Line + 6200 3700 4400 3700 +Wire Wire Line + 4400 3700 4400 4000 +Wire Wire Line + 4400 4000 4350 4000 +Wire Wire Line + 4350 4050 5100 4050 +Wire Wire Line + 4350 4050 4350 4100 +Wire Wire Line + 6100 4050 6250 4050 +Wire Wire Line + 6250 4050 6250 3650 +Wire Wire Line + 6250 3650 4450 3650 +Wire Wire Line + 4450 3650 4450 4200 +Wire Wire Line + 4450 4200 4350 4200 +Wire Wire Line + 5100 3950 4500 3950 +Wire Wire Line + 4500 3950 4500 4300 +Wire Wire Line + 4500 4300 4350 4300 +Wire Wire Line + 5100 4450 4500 4450 +Wire Wire Line + 4500 4450 4500 4400 +Wire Wire Line + 4500 4400 4350 4400 +Wire Wire Line + 5100 4550 4450 4550 +Wire Wire Line + 4450 4550 4450 4500 +Wire Wire Line + 4450 4500 4350 4500 +Wire Wire Line + 4550 4250 5100 4250 +Wire Wire Line + 4550 4250 4550 4600 +Wire Wire Line + 4550 4600 4350 4600 +Wire Wire Line + 6100 4650 6150 4650 +Wire Wire Line + 6150 4650 6150 5000 +Wire Wire Line + 6150 5000 4250 5000 +Wire Wire Line + 4250 5100 4650 5100 +Wire Wire Line + 4650 5100 4650 4350 +Wire Wire Line + 4650 4350 5100 4350 +Wire Wire Line + 6100 4550 6350 4550 +Wire Wire Line + 6350 4550 6350 4150 +Wire Wire Line + 6350 4150 6750 4150 +Wire Wire Line + 6100 4250 6750 4250 +Wire Wire Line + 6100 4350 6750 4350 +Wire Wire Line + 6750 4450 6100 4450 +$Comp +L plot_v1 U2 +U 1 1 5CF261D1 +P 1700 2550 +F 0 "U2" H 1700 3050 60 0000 C CNN +F 1 "plot_v1" H 1900 2900 60 0000 C CNN +F 2 "" H 1700 2550 60 0000 C CNN +F 3 "" H 1700 2550 60 0000 C CNN + 1 1700 2550 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5CF262A9 +P 1700 3050 +F 0 "U3" H 1700 3550 60 0000 C CNN +F 1 "plot_v1" H 1900 3400 60 0000 C CNN +F 2 "" H 1700 3050 60 0000 C CNN +F 3 "" H 1700 3050 60 0000 C CNN + 1 1700 3050 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5CF262EF +P 1700 3450 +F 0 "U4" H 1700 3950 60 0000 C CNN +F 1 "plot_v1" H 1900 3800 60 0000 C CNN +F 2 "" H 1700 3450 60 0000 C CNN +F 3 "" H 1700 3450 60 0000 C CNN + 1 1700 3450 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5CF2632C +P 1700 3850 +F 0 "U5" H 1700 4350 60 0000 C CNN +F 1 "plot_v1" H 1900 4200 60 0000 C CNN +F 2 "" H 1700 3850 60 0000 C CNN +F 3 "" H 1700 3850 60 0000 C CNN + 1 1700 3850 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5CF26370 +P 1700 4250 +F 0 "U6" H 1700 4750 60 0000 C CNN +F 1 "plot_v1" H 1900 4600 60 0000 C CNN +F 2 "" H 1700 4250 60 0000 C CNN +F 3 "" H 1700 4250 60 0000 C CNN + 1 1700 4250 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 5CF263B7 +P 1700 4650 +F 0 "U7" H 1700 5150 60 0000 C CNN +F 1 "plot_v1" H 1900 5000 60 0000 C CNN +F 2 "" H 1700 4650 60 0000 C CNN +F 3 "" H 1700 4650 60 0000 C CNN + 1 1700 4650 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 5CF263FD +P 1700 5050 +F 0 "U8" H 1700 5550 60 0000 C CNN +F 1 "plot_v1" H 1900 5400 60 0000 C CNN +F 2 "" H 1700 5050 60 0000 C CNN +F 3 "" H 1700 5050 60 0000 C CNN + 1 1700 5050 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U9 +U 1 1 5CF26446 +P 1700 5500 +F 0 "U9" H 1700 6000 60 0000 C CNN +F 1 "plot_v1" H 1900 5850 60 0000 C CNN +F 2 "" H 1700 5500 60 0000 C CNN +F 3 "" H 1700 5500 60 0000 C CNN + 1 1700 5500 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U10 +U 1 1 5CF2649A +P 1700 5900 +F 0 "U10" H 1700 6400 60 0000 C CNN +F 1 "plot_v1" H 1900 6250 60 0000 C CNN +F 2 "" H 1700 5900 60 0000 C CNN +F 3 "" H 1700 5900 60 0000 C CNN + 1 1700 5900 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 5CF26545 +P 1700 2100 +F 0 "U1" H 1700 2600 60 0000 C CNN +F 1 "plot_v1" H 1900 2450 60 0000 C CNN +F 2 "" H 1700 2100 60 0000 C CNN +F 3 "" H 1700 2100 60 0000 C CNN + 1 1700 2100 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3200 3900 2900 3900 +Wire Wire Line + 2900 3900 2900 2100 +Wire Wire Line + 2900 2100 1500 2100 +Wire Wire Line + 1500 2550 2850 2550 +Wire Wire Line + 2850 2550 2850 4000 +Wire Wire Line + 2850 4000 3200 4000 +Wire Wire Line + 3200 4100 2700 4100 +Wire Wire Line + 2700 4100 2700 3050 +Wire Wire Line + 2700 3050 1500 3050 +Wire Wire Line + 1500 3450 2650 3450 +Wire Wire Line + 2650 3450 2650 4200 +Wire Wire Line + 2650 4200 3200 4200 +Wire Wire Line + 3200 4300 2600 4300 +Wire Wire Line + 2600 4300 2600 3850 +Wire Wire Line + 2600 3850 1500 3850 +Wire Wire Line + 1500 4250 2550 4250 +Wire Wire Line + 2550 4250 2550 4400 +Wire Wire Line + 2550 4400 3200 4400 +Wire Wire Line + 2450 4500 3200 4500 +Wire Wire Line + 2450 4500 2450 4650 +Wire Wire Line + 2450 4650 1500 4650 +Wire Wire Line + 1500 5050 2600 5050 +Wire Wire Line + 2600 5050 2600 4600 +Wire Wire Line + 2600 4600 3200 4600 +Wire Wire Line + 3250 5000 2650 5000 +Wire Wire Line + 2650 5000 2650 5500 +Wire Wire Line + 2650 5500 1500 5500 +Wire Wire Line + 3250 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5900 +Wire Wire Line + 2700 5900 1500 5900 +$Comp +L plot_v1 U16 +U 1 1 5CF26B3C +P 8600 3250 +F 0 "U16" H 8600 3750 60 0000 C CNN +F 1 "plot_v1" H 8800 3600 60 0000 C CNN +F 2 "" H 8600 3250 60 0000 C CNN +F 3 "" H 8600 3250 60 0000 C CNN + 1 8600 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U15 +U 1 1 5CF26C0A +P 8250 3750 +F 0 "U15" H 8250 4250 60 0000 C CNN +F 1 "plot_v1" H 8450 4100 60 0000 C CNN +F 2 "" H 8250 3750 60 0000 C CNN +F 3 "" H 8250 3750 60 0000 C CNN + 1 8250 3750 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U14 +U 1 1 5CF26C90 +P 8150 4900 +F 0 "U14" H 8150 5400 60 0000 C CNN +F 1 "plot_v1" H 8350 5250 60 0000 C CNN +F 2 "" H 8150 4900 60 0000 C CNN +F 3 "" H 8150 4900 60 0000 C CNN + 1 8150 4900 + 0 -1 -1 0 +$EndComp +$Comp +L plot_v1 U17 +U 1 1 5CF26D07 +P 8750 5150 +F 0 "U17" H 8750 5650 60 0000 C CNN +F 1 "plot_v1" H 8950 5500 60 0000 C CNN +F 2 "" H 8750 5150 60 0000 C CNN +F 3 "" H 8750 5150 60 0000 C CNN + 1 8750 5150 + -1 0 0 1 +$EndComp +Wire Wire Line + 8750 5350 8750 4500 +Connection ~ 8750 4500 +Wire Wire Line + 7950 4900 8200 4900 +Connection ~ 8200 4900 +Wire Wire Line + 8050 3750 8500 3750 +Connection ~ 8500 3750 +Connection ~ 8600 3950 +Text GLabel 8450 3250 0 60 Input ~ 0 +a1 +Text GLabel 8250 3850 3 60 Input ~ 0 +a0 +Text GLabel 8600 4750 0 60 Input ~ 0 +a2 +Text GLabel 8050 5050 3 60 Input ~ 0 +a3 +Wire Wire Line + 8050 5050 8050 4900 +Connection ~ 8050 4900 +Wire Wire Line + 8600 4750 8750 4750 +Connection ~ 8750 4750 +Wire Wire Line + 8250 3850 8250 3750 +Connection ~ 8250 3750 +Wire Wire Line + 8450 3250 8600 3250 +Connection ~ 8600 3250 +NoConn ~ 6100 3950 +NoConn ~ 5100 4650 +Text GLabel 2000 1950 1 60 Output ~ 0 +q0 +Text GLabel 2000 2450 1 60 Output ~ 0 +q1 +Text GLabel 1900 2900 1 60 Output ~ 0 +q2 +Text GLabel 1850 3350 1 60 Output ~ 0 +q3 +Text GLabel 1850 3750 1 60 Output ~ 0 +q4 +Text GLabel 1850 4150 1 60 Output ~ 0 +q5 +Text GLabel 1800 4550 1 60 Output ~ 0 +q6 +Text GLabel 1800 4950 1 60 Output ~ 0 +q7 +Text GLabel 1800 5400 1 60 Output ~ 0 +q8 +Text GLabel 1800 5800 1 60 Output ~ 0 +q9 +Wire Wire Line + 1800 5800 1800 5900 +Connection ~ 1800 5900 +Wire Wire Line + 1800 5400 1800 5500 +Connection ~ 1800 5500 +Wire Wire Line + 1800 4950 1800 5050 +Connection ~ 1800 5050 +Wire Wire Line + 1800 4550 1800 4650 +Connection ~ 1800 4650 +Wire Wire Line + 1850 4150 1850 4250 +Connection ~ 1850 4250 +Wire Wire Line + 1850 3750 1850 3850 +Connection ~ 1850 3850 +Wire Wire Line + 1850 3350 1850 3450 +Connection ~ 1850 3450 +Wire Wire Line + 1900 2900 1900 3050 +Connection ~ 1900 3050 +Wire Wire Line + 2000 2450 2000 2550 +Connection ~ 2000 2550 +Wire Wire Line + 2000 1950 2000 2100 +Connection ~ 2000 2100 +$EndSCHEMATC +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~HEAD index 0a3ccf7f..0a3ccf7f 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~fellowship2019-python3 new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and-cache.lib~fellowship2019-python3 @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~HEAD index e3c96645..e3c96645 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~fellowship2019-python3 new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir.out~fellowship2019-python3 @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~HEAD index 15f8954d..15f8954d 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3 new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.cir~fellowship2019-python3 @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~HEAD index 0fdf4d25..0fdf4d25 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~fellowship2019-python3 new file mode 100644 index 00000000..2c9ac554 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.pro~fellowship2019-python3 @@ -0,0 +1,58 @@ +update=03/26/19 18:40:23 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_PSpice +LibName23=eSim_Sources +LibName24=eSim_Subckt +LibName25=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~HEAD index c853bf49..c853bf49 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~fellowship2019-python3 new file mode 100644 index 00000000..86be0215 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sch~fellowship2019-python3 @@ -0,0 +1,121 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~HEAD index b949ae4f..b949ae4f 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~fellowship2019-python3 new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and.sub~fellowship2019-python3 @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~HEAD b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~HEAD new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~HEAD @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~fellowship2019-python3 new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/3_and_Previous_Values.xml~fellowship2019-python3 @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~HEAD index e316d596..e316d596 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~fellowship2019-python3 new file mode 100644 index 00000000..4ee605a2 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073-cache.lib~fellowship2019-python3 @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~HEAD index d22d0923..d22d0923 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~fellowship2019-python3 new file mode 100644 index 00000000..b25337cd --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir.out~fellowship2019-python3 @@ -0,0 +1,16 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~HEAD index 7afe79fe..7afe79fe 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~fellowship2019-python3 new file mode 100644 index 00000000..e159f055 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.cir~fellowship2019-python3 @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4073\4073.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:41:15 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad9_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +X3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ 3_and +X2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ 3_and + +.end diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~HEAD index 7ed8e96e..7ed8e96e 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~fellowship2019-python3 new file mode 100644 index 00000000..94cd9bd4 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.pro~fellowship2019-python3 @@ -0,0 +1,43 @@ +update=05/31/19 16:37:06 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~HEAD index ff6d873a..ff6d873a 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~fellowship2019-python3 new file mode 100644 index 00000000..045208e6 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sch~fellowship2019-python3 @@ -0,0 +1,263 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 5CF10AEA +P 4550 2650 +F 0 "X1" H 4650 2600 60 0000 C CNN +F 1 "3_and" H 4700 2800 60 0000 C CNN +F 2 "" H 4550 2650 60 0000 C CNN +F 3 "" H 4550 2650 60 0000 C CNN + 1 4550 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CF10B72 +P 3100 2200 +F 0 "U1" H 3150 2300 30 0000 C CNN +F 1 "PORT" H 3100 2200 30 0000 C CNN +F 2 "" H 3100 2200 60 0000 C CNN +F 3 "" H 3100 2200 60 0000 C CNN + 1 3100 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CF10BC9 +P 3100 2500 +F 0 "U1" H 3150 2600 30 0000 C CNN +F 1 "PORT" H 3100 2500 30 0000 C CNN +F 2 "" H 3100 2500 60 0000 C CNN +F 3 "" H 3100 2500 60 0000 C CNN + 2 3100 2500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 5CF10BEA +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 8 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 5CF10C10 +P 6200 2600 +F 0 "U1" H 6250 2700 30 0000 C CNN +F 1 "PORT" H 6200 2600 30 0000 C CNN +F 2 "" H 6200 2600 60 0000 C CNN +F 3 "" H 6200 2600 60 0000 C CNN + 9 6200 2600 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2600 5050 2600 +Wire Wire Line + 4200 2500 4200 2200 +Wire Wire Line + 4200 2200 3350 2200 +Wire Wire Line + 3350 2500 3850 2500 +Wire Wire Line + 3850 2500 3850 2600 +Wire Wire Line + 3850 2600 4200 2600 +Wire Wire Line + 4200 2700 4200 2850 +Wire Wire Line + 4200 2850 3350 2850 +$Comp +L 3_and X3 +U 1 1 5CF10DE5 +P 4600 4100 +F 0 "X3" H 4700 4050 60 0000 C CNN +F 1 "3_and" H 4750 4250 60 0000 C CNN +F 2 "" H 4600 4100 60 0000 C CNN +F 3 "" H 4600 4100 60 0000 C CNN + 1 4600 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CF10DEB +P 3150 3650 +F 0 "U1" H 3200 3750 30 0000 C CNN +F 1 "PORT" H 3150 3650 30 0000 C CNN +F 2 "" H 3150 3650 60 0000 C CNN +F 3 "" H 3150 3650 60 0000 C CNN + 3 3150 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CF10DF1 +P 3150 3950 +F 0 "U1" H 3200 4050 30 0000 C CNN +F 1 "PORT" H 3150 3950 30 0000 C CNN +F 2 "" H 3150 3950 60 0000 C CNN +F 3 "" H 3150 3950 60 0000 C CNN + 4 3150 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5CF10DF7 +P 3150 4300 +F 0 "U1" H 3200 4400 30 0000 C CNN +F 1 "PORT" H 3150 4300 30 0000 C CNN +F 2 "" H 3150 4300 60 0000 C CNN +F 3 "" H 3150 4300 60 0000 C CNN + 5 3150 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CF10DFD +P 6250 4050 +F 0 "U1" H 6300 4150 30 0000 C CNN +F 1 "PORT" H 6250 4050 30 0000 C CNN +F 2 "" H 6250 4050 60 0000 C CNN +F 3 "" H 6250 4050 60 0000 C CNN + 6 6250 4050 + -1 0 0 1 +$EndComp +Wire Wire Line + 6000 4050 5100 4050 +Wire Wire Line + 4250 3950 4250 3650 +Wire Wire Line + 4250 3650 3400 3650 +Wire Wire Line + 3400 3950 3900 3950 +Wire Wire Line + 3900 3950 3900 4050 +Wire Wire Line + 3900 4050 4250 4050 +Wire Wire Line + 4250 4150 4250 4300 +Wire Wire Line + 4250 4300 3400 4300 +$Comp +L 3_and X2 +U 1 1 5CF10E9C +P 4550 5450 +F 0 "X2" H 4650 5400 60 0000 C CNN +F 1 "3_and" H 4700 5600 60 0000 C CNN +F 2 "" H 4550 5450 60 0000 C CNN +F 3 "" H 4550 5450 60 0000 C CNN + 1 4550 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 5CF10EA2 +P 3100 5000 +F 0 "U1" H 3150 5100 30 0000 C CNN +F 1 "PORT" H 3100 5000 30 0000 C CNN +F 2 "" H 3100 5000 60 0000 C CNN +F 3 "" H 3100 5000 60 0000 C CNN + 11 3100 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 5CF10EA8 +P 3100 5300 +F 0 "U1" H 3150 5400 30 0000 C CNN +F 1 "PORT" H 3100 5300 30 0000 C CNN +F 2 "" H 3100 5300 60 0000 C CNN +F 3 "" H 3100 5300 60 0000 C CNN + 12 3100 5300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 5CF10EAE +P 3100 5650 +F 0 "U1" H 3150 5750 30 0000 C CNN +F 1 "PORT" H 3100 5650 30 0000 C CNN +F 2 "" H 3100 5650 60 0000 C CNN +F 3 "" H 3100 5650 60 0000 C CNN + 13 3100 5650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 5CF10EB4 +P 6200 5400 +F 0 "U1" H 6250 5500 30 0000 C CNN +F 1 "PORT" H 6200 5400 30 0000 C CNN +F 2 "" H 6200 5400 60 0000 C CNN +F 3 "" H 6200 5400 60 0000 C CNN + 10 6200 5400 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 5400 5050 5400 +Wire Wire Line + 4200 5300 4200 5000 +Wire Wire Line + 4200 5000 3350 5000 +Wire Wire Line + 3350 5300 3850 5300 +Wire Wire Line + 3850 5300 3850 5400 +Wire Wire Line + 3850 5400 4200 5400 +Wire Wire Line + 4200 5500 4200 5650 +Wire Wire Line + 4200 5650 3350 5650 +$Comp +L PORT U1 +U 7 1 5CF11A2A +P 7500 4100 +F 0 "U1" H 7550 4200 30 0000 C CNN +F 1 "PORT" H 7500 4100 30 0000 C CNN +F 2 "" H 7500 4100 60 0000 C CNN +F 3 "" H 7500 4100 60 0000 C CNN + 7 7500 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 5CF11A8A +P 7550 4600 +F 0 "U1" H 7600 4700 30 0000 C CNN +F 1 "PORT" H 7550 4600 30 0000 C CNN +F 2 "" H 7550 4600 60 0000 C CNN +F 3 "" H 7550 4600 60 0000 C CNN + 14 7550 4600 + -1 0 0 1 +$EndComp +NoConn ~ 7250 4100 +NoConn ~ 7300 4600 +$EndSCHEMATC diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~HEAD index b10679cc..b10679cc 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~fellowship2019-python3 new file mode 100644 index 00000000..15208169 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073.sub~fellowship2019-python3 @@ -0,0 +1,10 @@ +* Subcircuit 4073 +.subckt 4073 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\users\malli\esim\src\subcircuitlibrary\4073\4073.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad9_ 3_and +x3 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ 3_and +x2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ 3_and +* Control Statements + +.ends 4073
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~HEAD index 5acac768..5acac768 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~HEAD diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~fellowship2019-python3 b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~fellowship2019-python3 new file mode 100644 index 00000000..5acac768 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_Previous_Values.xml~fellowship2019-python3 @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel /><subcircuit><x2><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x2><x3><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x3><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro index 1ff3178b..a356f8bb 100644 --- a/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro +++ b/Examples/Analysis_Of_Digital_IC/4073_test/4073_test.pro @@ -40,7 +40,13 @@ LibName6=eSim_Hybrid LibName7=eSim_Miscellaneous LibName8=eSim_Plot LibName9=eSim_Power +<<<<<<< HEAD LibName10=eSim_PSpice LibName11=eSim_Sources LibName12=eSim_Subckt LibName13=eSim_User +======= +LibName10=eSim_User +LibName11=eSim_Sources +LibName12=eSim_Subckt +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib index 10a35d95..b26d4bdf 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-cache.lib @@ -27,11 +27,19 @@ X VDD 14 550 300 200 L 50 50 1 1 I ENDDRAW ENDDEF # +<<<<<<< HEAD # DC # DEF DC v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN F1 "DC" -200 -50 60 H V C CNN +======= +# DC-RESCUE-4_Input_NAND_Charcateristics +# +DEF DC-RESCUE-4_Input_NAND_Charcateristics v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4_Input_NAND_Charcateristics" -200 -50 60 H V C CNN +>>>>>>> fellowship2019-python3 F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-rescue.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-rescue.lib new file mode 100644 index 00000000..46932345 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics-rescue.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-4_Input_NAND_Charcateristics +# +DEF DC-RESCUE-4_Input_NAND_Charcateristics v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4_Input_NAND_Charcateristics" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro index ee32c69b..cacee8d6 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.pro @@ -1,3 +1,4 @@ +<<<<<<< HEAD update=06/01/19 15:09:21
version=1
last_client=eeschema
@@ -43,3 +44,50 @@ LibName9=eSim_PSpice LibName10=eSim_Sources
LibName11=eSim_User
LibName12=eSim_Subckt
+======= +update=Wed Mar 11 12:52:26 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../eSim/kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_Input_NAND_Charcateristics-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_Subckt +LibName11=eSim_Sources +LibName12=eSim_User +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch index 55a46f82..40e78f30 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NAND_Charcateristics/4_Input_NAND_Charcateristics.sch @@ -1,4 +1,8 @@ EESchema Schematic File Version 2 +<<<<<<< HEAD +======= +LIBS:4_Input_NAND_Charcateristics-rescue +>>>>>>> fellowship2019-python3 LIBS:power LIBS:eSim_Analog LIBS:eSim_Devices @@ -7,7 +11,10 @@ LIBS:eSim_Hybrid LIBS:eSim_Miscellaneous LIBS:eSim_Plot LIBS:eSim_Power +<<<<<<< HEAD LIBS:eSim_PSpice +======= +>>>>>>> fellowship2019-python3 LIBS:eSim_Sources LIBS:eSim_User LIBS:eSim_Subckt @@ -51,7 +58,11 @@ $EndComp NoConn ~ 4550 4350 NoConn ~ 5600 3750 $Comp +<<<<<<< HEAD L DC v1 +======= +L DC-RESCUE-4_Input_NAND_Charcateristics v1 +>>>>>>> fellowship2019-python3 U 1 1 5CF2488C P 1900 3450 F 0 "v1" H 1700 3550 60 0000 C CNN @@ -62,7 +73,11 @@ F 3 "" H 1900 3450 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v2 +======= +L DC-RESCUE-4_Input_NAND_Charcateristics v2 +>>>>>>> fellowship2019-python3 U 1 1 5CF248E2 P 1900 4000 F 0 "v2" H 1700 4100 60 0000 C CNN @@ -73,7 +88,11 @@ F 3 "" H 1900 4000 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v3 +======= +L DC-RESCUE-4_Input_NAND_Charcateristics v3 +>>>>>>> fellowship2019-python3 U 1 1 5CF24906 P 1900 4550 F 0 "v3" H 1700 4650 60 0000 C CNN @@ -84,7 +103,11 @@ F 3 "" H 1900 4550 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v4 +======= +L DC-RESCUE-4_Input_NAND_Charcateristics v4 +>>>>>>> fellowship2019-python3 U 1 1 5CF24935 P 1900 5100 F 0 "v4" H 1700 5200 60 0000 C CNN @@ -138,7 +161,11 @@ F 3 "" H 6450 4050 60 0000 C CNN -1 0 0 1 $EndComp $Comp +<<<<<<< HEAD L DC v8 +======= +L DC-RESCUE-4_Input_NAND_Charcateristics v8 +>>>>>>> fellowship2019-python3 U 1 1 5CF24B50 P 8150 4650 F 0 "v8" H 7950 4750 60 0000 C CNN @@ -149,7 +176,11 @@ F 3 "" H 8150 4650 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp +<<<<<<< HEAD L DC v7 +======= +L DC-RESCUE-4_Input_NAND_Charcateristics v7 +>>>>>>> fellowship2019-python3 U 1 1 5CF24B56 P 8150 4100 F 0 "v7" H 7950 4200 60 0000 C CNN @@ -160,7 +191,11 @@ F 3 "" H 8150 4100 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp +<<<<<<< HEAD L DC v6 +======= +L DC-RESCUE-4_Input_NAND_Charcateristics v6 +>>>>>>> fellowship2019-python3 U 1 1 5CF24B5C P 8150 3550 F 0 "v6" H 7950 3650 60 0000 C CNN @@ -171,7 +206,11 @@ F 3 "" H 8150 3550 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp +<<<<<<< HEAD L DC v5 +======= +L DC-RESCUE-4_Input_NAND_Charcateristics v5 +>>>>>>> fellowship2019-python3 U 1 1 5CF24B62 P 8150 3000 F 0 "v5" H 7950 3100 60 0000 C CNN diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib index 57f05c24..c955612e 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-cache.lib @@ -1,11 +1,19 @@ EESchema-LIBRARY Version 2.3 #encoding utf-8 # +<<<<<<< HEAD # DC # DEF DC v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN F1 "DC" -200 -50 60 H V C CNN +======= +# DC-RESCUE-4_Input_NOR_Characteristics +# +DEF DC-RESCUE-4_Input_NOR_Characteristics v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4_Input_NOR_Characteristics" -200 -50 60 H V C CNN +>>>>>>> fellowship2019-python3 F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST @@ -110,9 +118,16 @@ ENDDEF # DEF eSim_R R 0 0 N Y 1 F N F0 "R" 50 130 50 H V C CNN +<<<<<<< HEAD F1 "eSim_R" 50 50 50 H V C CNN F2 "" 50 -20 30 H V C CNN F3 "" 50 50 30 V V C CNN +======= +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +>>>>>>> fellowship2019-python3 $FPLIST R_* Resistor_* diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-rescue.lib b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-rescue.lib new file mode 100644 index 00000000..9ba9e4d7 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics-rescue.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-4_Input_NOR_Characteristics +# +DEF DC-RESCUE-4_Input_NOR_Characteristics v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-4_Input_NOR_Characteristics" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro index 43701631..7634e0b8 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.pro @@ -1,3 +1,4 @@ +<<<<<<< HEAD update=06/01/19 05:45:01
version=1
last_client=eeschema
@@ -42,3 +43,50 @@ LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
LibName11=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
+======= +update=Wed Mar 11 12:54:03 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=4_Input_NOR_Characteristics-rescue +LibName2=power +LibName3=eSim_Devices +LibName4=eSim_User +LibName5=eSim_Subckt +LibName6=eSim_Sources +LibName7=eSim_Power +LibName8=eSim_Plot +LibName9=eSim_Miscellaneous +LibName10=eSim_Hybrid +LibName11=eSim_Digital +LibName12=eSim_Analog +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch index e07e773f..f18161c9 100644 --- a/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch +++ b/Examples/Analysis_Of_Digital_IC/4_Input_NOR_Characteristics/4_Input_NOR_Characteristics.sch @@ -1,5 +1,20 @@ EESchema Schematic File Version 2 +<<<<<<< HEAD LIBS:power +======= +LIBS:4_Input_NOR_Characteristics-rescue +LIBS:power +LIBS:eSim_Devices +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Analog +>>>>>>> fellowship2019-python3 LIBS:4_Input_NOR_Characteristics-cache EELAYER 25 0 EELAYER END @@ -364,7 +379,11 @@ F 3 "" V 7400 3450 30 0000 C CNN 1 0 0 -1 $EndComp $Comp +<<<<<<< HEAD L DC v6 +======= +L DC-RESCUE-4_Input_NOR_Characteristics v6 +>>>>>>> fellowship2019-python3 U 1 1 5CF1E4C8 P 8200 3550 F 0 "v6" H 8000 3650 60 0000 C CNN @@ -375,7 +394,11 @@ F 3 "" H 8200 3550 60 0000 C CNN 0 -1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v5 +======= +L DC-RESCUE-4_Input_NOR_Characteristics v5 +>>>>>>> fellowship2019-python3 U 1 1 5CF1E4C2 P 8200 3650 F 0 "v5" H 8000 3750 60 0000 C CNN @@ -386,7 +409,11 @@ F 3 "" H 8200 3650 60 0000 C CNN 0 -1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v8 +======= +L DC-RESCUE-4_Input_NOR_Characteristics v8 +>>>>>>> fellowship2019-python3 U 1 1 5CF1E4BC P 8200 3350 F 0 "v8" H 8000 3450 60 0000 C CNN @@ -397,7 +424,11 @@ F 3 "" H 8200 3350 60 0000 C CNN 0 -1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v7 +======= +L DC-RESCUE-4_Input_NOR_Characteristics v7 +>>>>>>> fellowship2019-python3 U 1 1 5CF1E4B6 P 8200 3450 F 0 "v7" H 8000 3550 60 0000 C CNN @@ -556,7 +587,11 @@ F 3 "" V 3600 3350 30 0000 C CNN 1 0 0 -1 $EndComp $Comp +<<<<<<< HEAD L DC v4 +======= +L DC-RESCUE-4_Input_NOR_Characteristics v4 +>>>>>>> fellowship2019-python3 U 1 1 5CF1D11E P 2750 3550 F 0 "v4" H 2550 3650 60 0000 C CNN @@ -567,7 +602,11 @@ F 3 "" H 2750 3550 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v3 +======= +L DC-RESCUE-4_Input_NOR_Characteristics v3 +>>>>>>> fellowship2019-python3 U 1 1 5CF1D0EF P 2750 3450 F 0 "v3" H 2550 3550 60 0000 C CNN @@ -578,7 +617,11 @@ F 3 "" H 2750 3450 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v2 +======= +L DC-RESCUE-4_Input_NOR_Characteristics v2 +>>>>>>> fellowship2019-python3 U 1 1 5CF1D0C3 P 2700 3350 F 0 "v2" H 2500 3450 60 0000 C CNN @@ -589,7 +632,11 @@ F 3 "" H 2700 3350 60 0000 C CNN 0 1 1 0 $EndComp $Comp +<<<<<<< HEAD L DC v1 +======= +L DC-RESCUE-4_Input_NOR_Characteristics v1 +>>>>>>> fellowship2019-python3 U 1 1 5CF1CE2E P 2700 3250 F 0 "v1" H 2500 3350 60 0000 C CNN diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib index e21eb0f8..81e6945f 100644 --- a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-cache.lib @@ -29,11 +29,19 @@ X Vdd 16 500 350 200 L 50 50 1 1 O ENDDRAW ENDDEF # +<<<<<<< HEAD # DC # DEF DC v 0 40 Y Y 1 F N F0 "v" -200 100 60 H V C CNN F1 "DC" -200 -50 60 H V C CNN +======= +# DC-RESCUE-BCDToDecimalDecoder +# +DEF DC-RESCUE-BCDToDecimalDecoder v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-BCDToDecimalDecoder" -200 -50 60 H V C CNN +>>>>>>> fellowship2019-python3 F2 "R1" -300 0 60 H V C CNN F3 "" 0 0 60 H V C CNN $FPLIST diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-rescue.lib b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-rescue.lib new file mode 100644 index 00000000..5c30d95b --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder-rescue.lib @@ -0,0 +1,21 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC-RESCUE-BCDToDecimalDecoder +# +DEF DC-RESCUE-BCDToDecimalDecoder v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC-RESCUE-BCDToDecimalDecoder" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro index dc708582..3a7a5a58 100644 --- a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.pro @@ -1,3 +1,4 @@ +<<<<<<< HEAD update=06/01/19 16:07:13
version=1
last_client=eeschema
@@ -42,3 +43,50 @@ LibName8=eSim_Power LibName9=eSim_Sources
LibName10=eSim_Subckt
LibName11=eSim_User
+======= +update=Wed Mar 11 12:54:17 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../eSim/kicadSchematicLibrary +[eeschema/libraries] +LibName1=BCDToDecimalDecoder-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_Sources +LibName11=eSim_Subckt +LibName12=eSim_User +>>>>>>> fellowship2019-python3 diff --git a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch index e4c093fd..15ab433e 100644 --- a/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch +++ b/Examples/Analysis_Of_Digital_IC/BCDToDecimalDecoder/BCDToDecimalDecoder.sch @@ -1,4 +1,8 @@ EESchema Schematic File Version 2 +<<<<<<< HEAD +======= +LIBS:BCDToDecimalDecoder-rescue +>>>>>>> fellowship2019-python3 LIBS:power LIBS:eSim_Analog LIBS:eSim_Devices @@ -70,7 +74,11 @@ F 3 "" H 3800 5050 60 0000 C CNN -1 0 0 -1 $EndComp $Comp +<<<<<<< HEAD L DC v2 +======= +L DC-RESCUE-BCDToDecimalDecoder v2 +>>>>>>> fellowship2019-python3 U 1 1 5CF25946 P 9400 3950 F 0 "v2" H 9200 4050 60 0000 C CNN @@ -81,7 +89,11 @@ F 3 "" H 9400 3950 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp +<<<<<<< HEAD L DC v1 +======= +L DC-RESCUE-BCDToDecimalDecoder v1 +>>>>>>> fellowship2019-python3 U 1 1 5CF259A4 P 9400 3400 F 0 "v1" H 9200 3500 60 0000 C CNN @@ -92,7 +104,11 @@ F 3 "" H 9400 3400 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp +<<<<<<< HEAD L DC v3 +======= +L DC-RESCUE-BCDToDecimalDecoder v3 +>>>>>>> fellowship2019-python3 U 1 1 5CF259F8 P 9400 4500 F 0 "v3" H 9200 4600 60 0000 C CNN @@ -103,7 +119,11 @@ F 3 "" H 9400 4500 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp +<<<<<<< HEAD L DC v4 +======= +L DC-RESCUE-BCDToDecimalDecoder v4 +>>>>>>> fellowship2019-python3 U 1 1 5CF25A37 P 9450 5000 F 0 "v4" H 9250 5100 60 0000 C CNN diff --git a/Examples/Astable555/555/NPN.lib b/Examples/Astable555/555/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/Examples/Astable555/555/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Examples/Astable555/Astable555-cache.lib b/Examples/Astable555/Astable555-cache.lib new file mode 100644 index 00000000..e0ae38fe --- /dev/null +++ b/Examples/Astable555/Astable555-cache.lib @@ -0,0 +1,103 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Astable555/Astable555.cir b/Examples/Astable555/Astable555.cir new file mode 100644 index 00000000..ba4b84ce --- /dev/null +++ b/Examples/Astable555/Astable555.cir @@ -0,0 +1,19 @@ +* /home/ash98/eSim-Workspace/555/555.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 11:17:26 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 V_Out GND 1k +R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 1k +R2 Net-_R1-Pad2_ C_Out 10k +v1 Net-_R1-Pad1_ GND DC +C1 C_Out GND 0.1u +C2 Net-_C2-Pad1_ GND 0.01u +U2 V_Out plot_v1 +U1 C_Out plot_v1 +X1 GND C_Out V_Out Net-_R1-Pad1_ Net-_C2-Pad1_ C_Out Net-_R1-Pad2_ Net-_R1-Pad1_ LM555N + +.end diff --git a/Examples/Astable555/Astable555.cir.out b/Examples/Astable555/Astable555.cir.out new file mode 100644 index 00000000..0e4615e2 --- /dev/null +++ b/Examples/Astable555/Astable555.cir.out @@ -0,0 +1,24 @@ +* /home/ash98/esim-workspace/555/555.cir + +.include lm555n.sub +r3 v_out gnd 1k +r1 net-_r1-pad1_ net-_r1-pad2_ 1k +r2 net-_r1-pad2_ c_out 10k +v1 net-_r1-pad1_ gnd dc 10 +c1 c_out gnd 0.1u +c2 net-_c2-pad1_ gnd 0.01u +* u2 v_out plot_v1 +* u1 c_out plot_v1 +x1 gnd c_out v_out net-_r1-pad1_ net-_c2-pad1_ c_out net-_r1-pad2_ net-_r1-pad1_ lm555n +.tran 1e-03 50e-03 0e-00 + +* Control Statements +.control +option noopalter +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(v_out) +plot v(c_out) +.endc +.end diff --git a/Examples/Astable555/Astable555.pro b/Examples/Astable555/Astable555.pro new file mode 100644 index 00000000..a75a7de6 --- /dev/null +++ b/Examples/Astable555/Astable555.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_User +LibName23=transistors +LibName24=conn +LibName25=eSim_Plot +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/Examples/Astable555/Astable555.proj b/Examples/Astable555/Astable555.proj new file mode 100644 index 00000000..958ec40d --- /dev/null +++ b/Examples/Astable555/Astable555.proj @@ -0,0 +1 @@ +schematicFile 555.sch diff --git a/Examples/Astable555/Astable555.sch b/Examples/Astable555/Astable555.sch new file mode 100644 index 00000000..78d11841 --- /dev/null +++ b/Examples/Astable555/Astable555.sch @@ -0,0 +1,256 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R3 +U 1 1 5E01A4E5 +P 6950 4150 +F 0 "R3" H 7000 4280 50 0000 C CNN +F 1 "1k" H 7000 4100 50 0000 C CNN +F 2 "" H 7000 4130 30 0000 C CNN +F 3 "" V 7000 4200 30 0000 C CNN + 1 6950 4150 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5E01A555 +P 4200 3500 +F 0 "R1" H 4250 3630 50 0000 C CNN +F 1 "1k" H 4250 3450 50 0000 C CNN +F 2 "" H 4250 3480 30 0000 C CNN +F 3 "" V 4250 3550 30 0000 C CNN + 1 4200 3500 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5E01A5D6 +P 4200 4000 +F 0 "R2" H 4250 4130 50 0000 C CNN +F 1 "10k" H 4250 3950 50 0000 C CNN +F 2 "" H 4250 3980 30 0000 C CNN +F 3 "" V 4250 4050 30 0000 C CNN + 1 4200 4000 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 5E01A67B +P 3400 3750 +F 0 "v1" H 3200 3850 60 0000 C CNN +F 1 "DC" H 3200 3700 60 0000 C CNN +F 2 "R1" H 3100 3750 60 0000 C CNN +F 3 "" H 3400 3750 60 0000 C CNN + 1 3400 3750 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 5E01A6D6 +P 3400 4300 +F 0 "#PWR01" H 3400 4050 50 0001 C CNN +F 1 "GND" H 3400 4150 50 0000 C CNN +F 2 "" H 3400 4300 50 0001 C CNN +F 3 "" H 3400 4300 50 0001 C CNN + 1 3400 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5E01A70A +P 4250 4600 +F 0 "C1" H 4275 4700 50 0000 L CNN +F 1 "0.1u" H 4275 4500 50 0000 L CNN +F 2 "" H 4288 4450 30 0000 C CNN +F 3 "" H 4250 4600 60 0000 C CNN + 1 4250 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_C C2 +U 1 1 5E01A8AB +P 4850 4600 +F 0 "C2" H 4875 4700 50 0000 L CNN +F 1 "0.01u" H 4875 4500 50 0000 L CNN +F 2 "" H 4888 4450 30 0000 C CNN +F 3 "" H 4850 4600 60 0000 C CNN + 1 4850 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5E01AA9B +P 5650 4950 +F 0 "#PWR02" H 5650 4700 50 0001 C CNN +F 1 "GND" H 5650 4800 50 0000 C CNN +F 2 "" H 5650 4950 50 0001 C CNN +F 3 "" H 5650 4950 50 0001 C CNN + 1 5650 4950 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 5E01AAF8 +P 6700 3850 +F 0 "U2" H 6700 4350 60 0000 C CNN +F 1 "plot_v1" H 6900 4200 60 0000 C CNN +F 2 "" H 6700 3850 60 0000 C CNN +F 3 "" H 6700 3850 60 0000 C CNN + 1 6700 3850 + 1 0 0 -1 +$EndComp +Text GLabel 6850 3900 0 60 Input ~ 0 +V_Out +$Comp +L plot_v1 U1 +U 1 1 5E01ABD2 +P 3850 4550 +F 0 "U1" H 3850 5050 60 0000 C CNN +F 1 "plot_v1" H 4050 4900 60 0000 C CNN +F 2 "" H 3850 4550 60 0000 C CNN +F 3 "" H 3850 4550 60 0000 C CNN + 1 3850 4550 + 1 0 0 -1 +$EndComp +Text GLabel 4000 4500 0 60 Input ~ 0 +C_Out +Wire Wire Line + 4250 3700 4250 3900 +Wire Wire Line + 6200 4000 6500 4000 +Wire Wire Line + 6500 4000 6500 3350 +Wire Wire Line + 6500 3350 4500 3350 +Wire Wire Line + 4500 3350 4500 3800 +Wire Wire Line + 4500 3800 4250 3800 +Connection ~ 4250 3800 +Wire Wire Line + 5100 4250 4650 4250 +Wire Wire Line + 4650 4250 4650 3100 +Wire Wire Line + 3400 3100 5650 3100 +Wire Wire Line + 5650 3100 5650 3400 +Wire Wire Line + 4250 3100 4250 3400 +Connection ~ 4650 3100 +Wire Wire Line + 3400 3300 3400 3100 +Connection ~ 4250 3100 +Wire Wire Line + 3400 4300 3400 4200 +Wire Wire Line + 4250 4200 4250 4450 +Wire Wire Line + 6200 4250 6450 4250 +Wire Wire Line + 6450 4250 6450 5200 +Wire Wire Line + 6450 5200 4550 5200 +Wire Wire Line + 4550 5200 4550 3750 +Wire Wire Line + 3850 4350 4550 4350 +Connection ~ 4250 4350 +Wire Wire Line + 4550 3750 5100 3750 +Connection ~ 4550 4350 +Wire Wire Line + 4850 4450 4850 4000 +Wire Wire Line + 4850 4000 5100 4000 +Wire Wire Line + 4250 4750 4250 4850 +Wire Wire Line + 4250 4850 7000 4850 +Wire Wire Line + 4850 4850 4850 4750 +Wire Wire Line + 5650 4600 5650 4950 +Connection ~ 4850 4850 +Wire Wire Line + 6200 3750 7000 3750 +Wire Wire Line + 7000 3750 7000 4050 +Wire Wire Line + 7000 4850 7000 4350 +Connection ~ 5650 4850 +Wire Wire Line + 6700 3650 6700 3750 +Connection ~ 6700 3750 +Wire Wire Line + 6850 3900 7000 3900 +Connection ~ 7000 3900 +Wire Wire Line + 4000 4500 4050 4500 +Wire Wire Line + 4050 4500 4050 4350 +Connection ~ 4050 4350 +$Comp +L LM555N X1 +U 1 1 5E01A47E +P 5650 4000 +F 0 "X1" H 5650 3950 60 0000 C CNN +F 1 "LM555N" H 5650 4100 60 0000 C CNN +F 2 "" H 5600 4000 60 0000 C CNN +F 3 "" H 5600 4000 60 0000 C CNN + 1 5650 4000 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/Astable555/Astable555_Previous_Values.xml b/Examples/Astable555/Astable555_Previous_Values.xml new file mode 100644 index 00000000..4375860d --- /dev/null +++ b/Examples/Astable555/Astable555_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">10</field1></v1></source><model /><devicemodel /><subcircuit><x1><field>/home/ash98/Downloads/lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">50</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Astable555/analysis b/Examples/Astable555/analysis new file mode 100644 index 00000000..2a579eef --- /dev/null +++ b/Examples/Astable555/analysis @@ -0,0 +1 @@ +.tran 1e-03 50e-03 0e-00
\ No newline at end of file diff --git a/Examples/Astable555/lm555n-cache.lib b/Examples/Astable555/lm555n-cache.lib new file mode 100644 index 00000000..824af11e --- /dev/null +++ b/Examples/Astable555/lm555n-cache.lib @@ -0,0 +1,205 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND-RESCUE-lm555n +# +DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# R-RESCUE-lm555n +# +DEF R-RESCUE-lm555n R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" 0 150 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_srlatch +# +DEF d_srlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srlatch" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X EN 3 -800 0 200 R 50 50 1 1 I +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# limit +# +DEF limit U 0 40 Y Y 1 F N +F0 "U" 50 -50 60 H V C CNN +F1 "limit" 50 50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Astable555/lm555n-rescue.lib b/Examples/Astable555/lm555n-rescue.lib new file mode 100644 index 00000000..fffeca36 --- /dev/null +++ b/Examples/Astable555/lm555n-rescue.lib @@ -0,0 +1,18 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# d_inverter-RESCUE-lm555n +# +DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/Astable555/lm555n.cir b/Examples/Astable555/lm555n.cir new file mode 100644 index 00000000..682d4945 --- /dev/null +++ b/Examples/Astable555/lm555n.cir @@ -0,0 +1,31 @@ +* /home/ash98/Downloads/lm555n/lm555n.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 15:58:04 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +E2 Net-_E2-Pad1_ GND /c /d 10000 +U1 Net-_Q1-Pad3_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad1_ Net-_R1-Pad1_ PORT +R8 Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500 +R7 Net-_E2-Pad1_ Net-_R7-Pad2_ 25 +R6 Net-_E1-Pad1_ Net-_R6-Pad2_ 25 +E1 Net-_E1-Pad1_ GND /b /a 10000 +R4 /b /a 2E6 +R5 /c /d 2E6 +R3 /c Net-_Q1-Pad3_ 5000 +R2 /a /c 5000 +R1 Net-_R1-Pad1_ /a 5000 +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U7-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad6_ Net-_U10-Pad1_ d_srlatch +U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ adc_bridge_1 +U4 Net-_U3-Pad2_ Net-_U4-Pad2_ adc_bridge_1 +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ adc_bridge_1 +U3 Net-_R7-Pad2_ Net-_U3-Pad2_ limit +U2 Net-_R6-Pad2_ Net-_U2-Pad2_ limit +U9 Net-_U8-Pad6_ Net-_U1-Pad3_ dac_bridge_1 +U10 Net-_U10-Pad1_ Net-_R8-Pad1_ dac_bridge_1 +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN + +.end diff --git a/Examples/Astable555/lm555n.cir.out b/Examples/Astable555/lm555n.cir.out new file mode 100644 index 00000000..a81070a1 --- /dev/null +++ b/Examples/Astable555/lm555n.cir.out @@ -0,0 +1,42 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +.include npn_1.lib +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/Astable555/lm555n.pro b/Examples/Astable555/lm555n.pro new file mode 100644 index 00000000..0a5408b6 --- /dev/null +++ b/Examples/Astable555/lm555n.pro @@ -0,0 +1,57 @@ +update=Tue Apr 2 17:35:59 2019 +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +[eeschema/libraries] +LibName1=lm555n-rescue +LibName2=power +LibName3=device +LibName4=transistors +LibName5=conn +LibName6=linear +LibName7=regul +LibName8=74xx +LibName9=cmos4000 +LibName10=adc-dac +LibName11=memory +LibName12=xilinx +LibName13=special +LibName14=microcontrollers +LibName15=dsp +LibName16=microchip +LibName17=analog_switches +LibName18=motorola +LibName19=texas +LibName20=intel +LibName21=audio +LibName22=interface +LibName23=digital-audio +LibName24=philips +LibName25=display +LibName26=cypress +LibName27=siliconi +LibName28=opto +LibName29=atmel +LibName30=contrib +LibName31=valves +LibName32=analogSpice +LibName33=analogXSpice +LibName34=converterSpice +LibName35=digitalSpice +LibName36=linearSpice +LibName37=measurementSpice +LibName38=portSpice +LibName39=sourcesSpice +LibName40=digitalXSpice +LibName41=eSim_User +LibName42=eSim_Subckt +LibName43=eSim_Sources +LibName44=eSim_PSpice +LibName45=eSim_Power +LibName46=eSim_Plot +LibName47=eSim_Miscellaneous +LibName48=eSim_Hybrid +LibName49=eSim_Digital +LibName50=eSim_Devices +LibName51=eSim_Analog diff --git a/Examples/Astable555/lm555n.sch b/Examples/Astable555/lm555n.sch new file mode 100644 index 00000000..28110b13 --- /dev/null +++ b/Examples/Astable555/lm555n.sch @@ -0,0 +1,518 @@ +EESchema Schematic File Version 2 +LIBS:lm555n-rescue +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3700 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 2650 3000 2850 3000 +Wire Wire Line + 2650 4750 2650 4650 +Connection ~ 2350 3550 +Connection ~ 2350 4900 +Wire Wire Line + 2350 4100 2350 4200 +Wire Wire Line + 9100 4900 9100 4800 +Wire Wire Line + 8500 4600 8500 4250 +Wire Wire Line + 3350 3250 3050 3250 +Wire Wire Line + 3050 3250 3050 3750 +Wire Wire Line + 3500 4350 3500 4500 +Wire Wire Line + 3650 3550 4200 3550 +Wire Wire Line + 3850 3250 4200 3250 +Wire Wire Line + 3150 3550 3150 3700 +Wire Wire Line + 3150 3700 3500 3700 +Wire Wire Line + 3500 3700 3500 3750 +Connection ~ 3500 4450 +Wire Wire Line + 3700 4450 3700 4400 +Wire Wire Line + 3050 4350 3050 4450 +Wire Wire Line + 3050 4450 3700 4450 +Wire Wire Line + 9100 4250 9000 4250 +Wire Wire Line + 9100 4400 9100 4350 +Wire Wire Line + 9100 4350 9200 4350 +Wire Wire Line + 10100 2950 10350 2950 +Wire Wire Line + 2350 4900 2350 4700 +Wire Wire Line + 2350 3500 2350 3600 +Wire Wire Line + 2250 3000 2350 3000 +Wire Wire Line + 2350 4150 2650 4150 +Connection ~ 2350 4150 +Wire Wire Line + 2250 3550 2650 3550 +Wire Wire Line + 2650 3550 2650 3500 +Wire Wire Line + 4300 4750 4300 4650 +Text Label 2800 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 3000 4050 +F 0 "E2" H 2800 4150 50 0000 C CNN +F 1 "10000" H 2800 4000 50 0000 C CNN +F 2 "" H 3000 4050 60 0001 C CNN +F 3 "" H 3000 4050 60 0001 C CNN + 1 3000 4050 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 3700 4400 +F 0 "#FLG01" H 3700 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 3700 4630 30 0000 C CNN +F 2 "" H 3700 4400 60 0001 C CNN +F 3 "" H 3700 4400 60 0001 C CNN + 1 3700 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 2000 3550 +F 0 "U1" H 2000 3500 30 0000 C CNN +F 1 "PORT" H 2000 3550 30 0000 C CNN +F 2 "" H 2000 3550 60 0001 C CNN +F 3 "" H 2000 3550 60 0001 C CNN + 5 2000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 2000 4900 +F 0 "U1" H 2000 4850 30 0000 C CNN +F 1 "PORT" H 2000 4900 30 0000 C CNN +F 2 "" H 2000 4900 60 0001 C CNN +F 3 "" H 2000 4900 60 0001 C CNN + 1 2000 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 2650 5000 +F 0 "U1" H 2650 4950 30 0000 C CNN +F 1 "PORT" H 2650 5000 30 0000 C CNN +F 2 "" H 2650 5000 60 0001 C CNN +F 3 "" H 2650 5000 60 0001 C CNN + 2 2650 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 4300 5000 +F 0 "U1" H 4300 4950 30 0000 C CNN +F 1 "PORT" H 4300 5000 30 0000 C CNN +F 2 "" H 4300 5000 60 0001 C CNN +F 3 "" H 4300 5000 60 0001 C CNN + 4 4300 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 9450 4350 +F 0 "U1" H 9450 4300 30 0000 C CNN +F 1 "PORT" H 9450 4350 30 0000 C CNN +F 2 "" H 9450 4350 60 0001 C CNN +F 3 "" H 9450 4350 60 0001 C CNN + 7 9450 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 10600 2950 +F 0 "U1" H 10600 2900 30 0000 C CNN +F 1 "PORT" H 10600 2950 30 0000 C CNN +F 2 "" H 10600 2950 60 0001 C CNN +F 3 "" H 10600 2950 60 0001 C CNN + 3 10600 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 3100 3000 +F 0 "U1" H 3100 2950 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0001 C CNN +F 3 "" H 3100 3000 60 0001 C CNN + 6 3100 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 2000 3000 +F 0 "U1" H 2000 2950 30 0000 C CNN +F 1 "PORT" H 2000 3000 30 0000 C CNN +F 2 "" H 2000 3000 60 0001 C CNN +F 3 "" H 2000 3000 60 0001 C CNN + 8 2000 3000 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R8 +U 1 1 50AA20DA +P 8750 4250 +F 0 "R8" V 8830 4250 50 0000 C CNN +F 1 "1500" V 8750 4250 50 0000 C CNN +F 2 "" H 8750 4250 60 0001 C CNN +F 3 "" H 8750 4250 60 0001 C CNN + 1 8750 4250 + 0 1 1 0 +$EndComp +$Comp +L GND-RESCUE-lm555n #PWR02 +U 1 1 50AA140C +P 3500 4500 +F 0 "#PWR02" H 3500 4500 30 0001 C CNN +F 1 "GND" H 3500 4430 30 0001 C CNN +F 2 "" H 3500 4500 60 0001 C CNN +F 3 "" H 3500 4500 60 0001 C CNN + 1 3500 4500 + 1 0 0 -1 +$EndComp +Text Label 2800 4000 0 60 ~ 0 +c +Text Label 2650 4650 0 60 ~ 0 +d +Text Label 2650 4150 0 60 ~ 0 +c +$Comp +L R-RESCUE-lm555n R7 +U 1 1 50AA12F7 +P 3600 3250 +F 0 "R7" V 3680 3250 50 0000 C CNN +F 1 "25" V 3600 3250 50 0000 C CNN +F 2 "" H 3600 3250 60 0001 C CNN +F 3 "" H 3600 3250 60 0001 C CNN + 1 3600 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R6 +U 1 1 50AA12B0 +P 3400 3550 +F 0 "R6" V 3480 3550 50 0000 C CNN +F 1 "25" V 3400 3550 50 0000 C CNN +F 2 "" H 3400 3550 60 0001 C CNN +F 3 "" H 3400 3550 60 0001 C CNN + 1 3400 3550 + 0 -1 -1 0 +$EndComp +Text Label 3250 4000 0 60 ~ 0 +b +Text Label 3250 4100 0 60 ~ 0 +a +Text Label 2650 3000 0 60 ~ 0 +b +Text Label 2650 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 3450 4050 +F 0 "E1" H 3250 4150 50 0000 C CNN +F 1 "10000" H 3250 4000 50 0000 C CNN +F 2 "" H 3450 4050 60 0001 C CNN +F 3 "" H 3450 4050 60 0001 C CNN + 1 3450 4050 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R4 +U 1 1 50A9E00B +P 2650 3250 +F 0 "R4" V 2730 3250 50 0000 C CNN +F 1 "2E6" V 2650 3250 50 0000 C CNN +F 2 "" H 2650 3250 60 0001 C CNN +F 3 "" H 2650 3250 60 0001 C CNN + 1 2650 3250 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R5 +U 1 1 50A9E001 +P 2650 4400 +F 0 "R5" V 2730 4400 50 0000 C CNN +F 1 "2E6" V 2650 4400 50 0000 C CNN +F 2 "" H 2650 4400 60 0001 C CNN +F 3 "" H 2650 4400 60 0001 C CNN + 1 2650 4400 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R3 +U 1 1 50A9DF09 +P 2350 4450 +F 0 "R3" V 2430 4450 50 0000 C CNN +F 1 "5000" V 2350 4450 50 0000 C CNN +F 2 "" H 2350 4450 60 0001 C CNN +F 3 "" H 2350 4450 60 0001 C CNN + 1 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R2 +U 1 1 50A9DF03 +P 2350 3850 +F 0 "R2" V 2430 3850 50 0000 C CNN +F 1 "5000" V 2350 3850 50 0000 C CNN +F 2 "" H 2350 3850 60 0001 C CNN +F 3 "" H 2350 3850 60 0001 C CNN + 1 2350 3850 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R1 +U 1 1 50A9DEFE +P 2350 3250 +F 0 "R1" V 2430 3250 50 0000 C CNN +F 1 "5000" V 2350 3250 50 0000 C CNN +F 2 "" H 2350 3250 60 0001 C CNN +F 3 "" H 2350 3250 60 0001 C CNN + 1 2350 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_srlatch U8 +U 1 1 5E01E563 +P 8000 3350 +F 0 "U8" H 8000 3350 60 0000 C CNN +F 1 "d_srlatch" H 8050 3500 60 0000 C CNN +F 2 "" H 8000 3350 60 0000 C CNN +F 3 "" H 8000 3350 60 0000 C CNN + 1 8000 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5E01F10F +P 7450 4400 +F 0 "U7" H 7450 4300 60 0000 C CNN +F 1 "d_inverter" H 7450 4550 60 0000 C CNN +F 2 "" H 7500 4350 60 0000 C CNN +F 3 "" H 7500 4350 60 0000 C CNN + 1 7450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 4400 8150 4400 +Wire Wire Line + 8000 4400 8000 4150 +$Comp +L adc_bridge_1 U5 +U 1 1 5E01F2C7 +P 6350 3400 +F 0 "U5" H 6350 3400 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3550 60 0000 C CNN +F 2 "" H 6350 3400 60 0000 C CNN +F 3 "" H 6350 3400 60 0000 C CNN + 1 6350 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3350 7200 3350 +Wire Wire Line + 4300 4650 5600 4650 +Wire Wire Line + 5600 4650 5600 3350 +Wire Wire Line + 5600 3350 5750 3350 +$Comp +L adc_bridge_1 U4 +U 1 1 5E01F3F2 +P 6350 3000 +F 0 "U4" H 6350 3000 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3150 60 0000 C CNN +F 2 "" H 6350 3000 60 0000 C CNN +F 3 "" H 6350 3000 60 0000 C CNN + 1 6350 3000 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U6 +U 1 1 5E01F469 +P 6350 3850 +F 0 "U6" H 6350 3850 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 4000 60 0000 C CNN +F 2 "" H 6350 3850 60 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3800 7200 3800 +Wire Wire Line + 7200 2950 6900 2950 +$Comp +L limit U3 +U 1 1 5E01F5DC +P 4900 2950 +F 0 "U3" H 4950 2900 60 0000 C CNN +F 1 "limit" H 4950 3000 60 0000 C CNN +F 2 "" H 4900 3000 60 0000 C CNN +F 3 "" H 4900 3000 60 0000 C CNN + 1 4900 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 2950 5750 2950 +Wire Wire Line + 4200 3250 4200 2950 +Wire Wire Line + 4200 2950 4500 2950 +$Comp +L limit U2 +U 1 1 5E01F79D +P 4800 3800 +F 0 "U2" H 4850 3750 60 0000 C CNN +F 1 "limit" H 4850 3850 60 0000 C CNN +F 2 "" H 4800 3850 60 0000 C CNN +F 3 "" H 4800 3850 60 0000 C CNN + 1 4800 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 3800 5750 3800 +Wire Wire Line + 4200 3550 4200 3800 +Wire Wire Line + 4200 3800 4400 3800 +Wire Wire Line + 7050 3350 7050 4400 +Wire Wire Line + 7050 4400 7150 4400 +Connection ~ 7050 3350 +Wire Wire Line + 8000 2600 8150 2600 +Wire Wire Line + 8150 2600 8150 4400 +Connection ~ 8000 4400 +$Comp +L dac_bridge_1 U9 +U 1 1 5E01FCD2 +P 9550 3000 +F 0 "U9" H 9550 3000 60 0000 C CNN +F 1 "dac_bridge_1" H 9550 3150 60 0000 C CNN +F 2 "" H 9550 3000 60 0000 C CNN +F 3 "" H 9550 3000 60 0000 C CNN + 1 9550 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 2950 8950 2950 +$Comp +L dac_bridge_1 U10 +U 1 1 5E01FE8E +P 9600 3850 +F 0 "U10" H 9600 3850 60 0000 C CNN +F 1 "dac_bridge_1" H 9600 4000 60 0000 C CNN +F 2 "" H 9600 3850 60 0000 C CNN +F 3 "" H 9600 3850 60 0000 C CNN + 1 9600 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 3800 8800 3800 +Wire Wire Line + 9100 4000 9100 4250 +Wire Wire Line + 9100 4000 10300 4000 +Wire Wire Line + 10300 4000 10300 3800 +Wire Wire Line + 10300 3800 10150 3800 +$Comp +L eSim_NPN Q1 +U 1 1 5E01E782 +P 9000 4600 +F 0 "Q1" H 8900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 8950 4750 50 0000 R CNN +F 2 "" H 9200 4700 29 0000 C CNN +F 3 "" H 9000 4600 60 0000 C CNN + 1 9000 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 4600 8500 4600 +Wire Wire Line + 2250 4900 9100 4900 +$EndSCHEMATC diff --git a/Examples/Astable555/lm555n.sub b/Examples/Astable555/lm555n.sub new file mode 100644 index 00000000..b524f5c6 --- /dev/null +++ b/Examples/Astable555/lm555n.sub @@ -0,0 +1,39 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +.include npn_1.lib +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) +*control statements + +.ends lm555n diff --git a/Examples/Astable555/lm555n_Previous_Values.xml b/Examples/Astable555/lm555n_Previous_Values.xml new file mode 100644 index 00000000..58d33ec5 --- /dev/null +++ b/Examples/Astable555/lm555n_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">false</field2><field3 name="Oct">true</field3><field4 name="Start Frequency">kjadsfh</field4><field5 name="Stop Frequency">jhdsakj</field5><field6 name="No. of points">897897</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Astable555/npn.lib b/Examples/Astable555/npn.lib new file mode 100644 index 00000000..2bf6420d --- /dev/null +++ b/Examples/Astable555/npn.lib @@ -0,0 +1,4 @@ +.model npn( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Examples/Astable555/npn_1.lib b/Examples/Astable555/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/Examples/Astable555/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/Examples/BJT_Biascircuit/BJT_Biascircuit.pro b/Examples/BJT_Biascircuit/BJT_Biascircuit.pro index 8da3fa54..f449ea48 100644 --- a/Examples/BJT_Biascircuit/BJT_Biascircuit.pro +++ b/Examples/BJT_Biascircuit/BJT_Biascircuit.pro @@ -62,6 +62,7 @@ LibName28=opto LibName29=atmel LibName30=contrib LibName31=power +<<<<<<< HEAD LibName32=device LibName33=transistors LibName34=conn @@ -70,3 +71,11 @@ LibName36=regul LibName37=74xx LibName38=cmos4000 LibName39=/home/fossee/library/eSim_Plot +======= +LibName32=eSim_Plot +LibName33=transistors +LibName34=conn +LibName35=74xx +LibName36=regul + +>>>>>>> fellowship2019-python3 diff --git a/Examples/BJT_CB_config/BJT_CB_config.pro b/Examples/BJT_CB_config/BJT_CB_config.pro index 4bb665c8..42e7b22f 100644 --- a/Examples/BJT_CB_config/BJT_CB_config.pro +++ b/Examples/BJT_CB_config/BJT_CB_config.pro @@ -63,6 +63,7 @@ LibName29=opto LibName30=atmel LibName31=contrib LibName32=power +<<<<<<< HEAD LibName33=device LibName34=transistors LibName35=conn @@ -70,3 +71,10 @@ LibName36=linear LibName37=regul LibName38=74xx LibName39=cmos4000 +======= +LibName33=74xx +LibName34=transistors +LibName35=conn +LibName36=cmos4000 +LibName37=regul +>>>>>>> fellowship2019-python3 diff --git a/Examples/BJT_CE_config/BJT_CE_config.pro b/Examples/BJT_CE_config/BJT_CE_config.pro index 64472dee..178e112d 100644 --- a/Examples/BJT_CE_config/BJT_CE_config.pro +++ b/Examples/BJT_CE_config/BJT_CE_config.pro @@ -61,6 +61,7 @@ LibName27=opto LibName28=atmel
LibName29=contrib
LibName30=power
+<<<<<<< HEAD LibName31=device
LibName32=transistors
LibName33=conn
@@ -69,3 +70,11 @@ LibName35=regul LibName36=74xx
LibName37=cmos4000
LibName38=eSim_Plot
+======= +LibName31=eSim_Plot
+LibName32=transistors
+LibName33=conn
+LibName34=cmos4000
+LibName35=regul
+LibName36=74xx
+>>>>>>> fellowship2019-python3 diff --git a/Examples/BJT_Frequency_Response/BJT_Frequency_Response.cir.out b/Examples/BJT_Frequency_Response/BJT_Frequency_Response.cir.out index 4be2d69b..7f123137 100644 --- a/Examples/BJT_Frequency_Response/BJT_Frequency_Response.cir.out +++ b/Examples/BJT_Frequency_Response/BJT_Frequency_Response.cir.out @@ -2,7 +2,11 @@ .include NPN.lib v1 net-_r2-pad2_ gnd dc 10 +<<<<<<< HEAD +v2 in gnd sine( 0.5 5 50 0 0) +======= v2 in gnd ac 0.5 0 +>>>>>>> fellowship2019-python3 c1 net-_c1-pad1_ net-_c1-pad2_ 40u c2 gnd net-_c2-pad2_ 100u c3 out net-_c3-pad2_ 40u diff --git a/Examples/BJT_Frequency_Response/BJT_Frequency_Response.pro b/Examples/BJT_Frequency_Response/BJT_Frequency_Response.pro index afdcf2d3..188278d7 100644 --- a/Examples/BJT_Frequency_Response/BJT_Frequency_Response.pro +++ b/Examples/BJT_Frequency_Response/BJT_Frequency_Response.pro @@ -62,10 +62,8 @@ LibName28=opto LibName29=atmel LibName30=contrib LibName31=power -LibName32=device +LibName32=74xx LibName33=transistors LibName34=conn -LibName35=linear +LibName35=cmos4000 LibName36=regul -LibName37=74xx -LibName38=cmos4000 diff --git a/Examples/BJT_amplifier/BJT_amplifier.pro b/Examples/BJT_amplifier/BJT_amplifier.pro index 1baaf847..34286d46 100644 --- a/Examples/BJT_amplifier/BJT_amplifier.pro +++ b/Examples/BJT_amplifier/BJT_amplifier.pro @@ -16,10 +16,10 @@ LibName9=eSim_Sources LibName10=eSim_Subckt LibName11=eSim_User LibName12=power -LibName13=device +LibName13=contrib LibName14=transistors LibName15=conn -LibName16=linear +LibName16=valves LibName17=regul LibName18=74xx LibName19=cmos4000 @@ -42,5 +42,8 @@ LibName35=cypress LibName36=siliconi LibName37=opto LibName38=atmel +<<<<<<< HEAD LibName39=contrib LibName40=valves +======= +>>>>>>> fellowship2019-python3 diff --git a/Examples/BasicGates/BasicGates.pro b/Examples/BasicGates/BasicGates.pro index 329f39fa..13e48b4a 100644 --- a/Examples/BasicGates/BasicGates.pro +++ b/Examples/BasicGates/BasicGates.pro @@ -16,17 +16,17 @@ LibName9=eSim_Sources LibName10=eSim_Subckt LibName11=eSim_User LibName12=power -LibName13=device +LibName13=contrib LibName14=transistors LibName15=conn -LibName16=linear +LibName16=valves LibName17=regul LibName18=74xx LibName19=cmos4000 LibName20=adc-dac LibName21=memory LibName22=xilinx -LibName23=special +LibName23=atmel LibName24=microcontrollers LibName25=dsp LibName26=microchip @@ -42,6 +42,3 @@ LibName35=display LibName36=cypress LibName37=siliconi LibName38=opto -LibName39=atmel -LibName40=contrib -LibName41=valves |