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| author | Sumanto Kar | 2022-02-08 16:22:43 +0530 |
|---|---|---|
| committer | GitHub | 2022-02-08 16:22:43 +0530 |
| commit | 536407d5e932bc3ba94b0286d1ee659205088520 (patch) | |
| tree | 9f74c56f253ad28e98173e9486c2b956a252126b | |
| parent | c28c426d72c72ef2327021f1fe8d7a7d97a76aa1 (diff) | |
| parent | b2c5afc0a22390f221083af05c1ce2703907df25 (diff) | |
| download | eSim-536407d5e932bc3ba94b0286d1ee659205088520.tar.gz eSim-536407d5e932bc3ba94b0286d1ee659205088520.tar.bz2 eSim-536407d5e932bc3ba94b0286d1ee659205088520.zip | |
Merge pull request #182 from Eyantra698Sumanto/master
Added Clock Generator and DAC
27 files changed, 2283 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib b/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib new file mode 100644 index 00000000..f7dfef8a --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC-cache.lib @@ -0,0 +1,91 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# summer +# +DEF summer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "summer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -200 250 -200 -250 300 0 -200 250 N +X IN1 1 -400 150 200 R 50 50 1 1 I +X IN2 2 -400 -150 200 R 50 50 1 1 I +X OUT 3 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir new file mode 100644 index 00000000..7090a7d0 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir @@ -0,0 +1,32 @@ +* /home/sumanto/eSim-2.1/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Feb 7 03:24:28 2022 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_R1-Pad1_ Net-_R1-Pad2_ 1024k +R2 Net-_R2-Pad1_ Net-_R1-Pad2_ 512k +R3 Net-_R3-Pad1_ Net-_R1-Pad2_ 256k +R4 Net-_R4-Pad1_ Net-_R1-Pad2_ 128k +R5 Net-_R5-Pad1_ Net-_R1-Pad2_ 64k +R6 Net-_R6-Pad1_ Net-_R1-Pad2_ 32k +R7 Net-_R7-Pad1_ Net-_R1-Pad2_ 16k +R9 Net-_R9-Pad1_ Net-_R1-Pad2_ 8k +R10 Net-_R10-Pad1_ Net-_R1-Pad2_ 4k +R11 Net-_R11-Pad1_ Net-_R1-Pad2_ 2k +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT +U2 Net-_R1-Pad2_ GND Net-_U1-Pad11_ summer +U3 Net-_U1-Pad1_ GND Net-_R1-Pad1_ summer +U8 Net-_U1-Pad2_ GND Net-_R2-Pad1_ summer +U4 Net-_U1-Pad3_ GND Net-_R3-Pad1_ summer +U5 Net-_U1-Pad4_ GND Net-_R4-Pad1_ summer +U9 Net-_U1-Pad5_ GND Net-_R5-Pad1_ summer +U10 Net-_U1-Pad6_ GND Net-_R6-Pad1_ summer +U6 Net-_U1-Pad7_ GND Net-_R7-Pad1_ summer +U7 Net-_U1-Pad8_ GND Net-_R9-Pad1_ summer +U12 Net-_U1-Pad9_ GND Net-_R10-Pad1_ summer +U11 Net-_U1-Pad10_ GND Net-_R11-Pad1_ summer + +.end diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out new file mode 100644 index 00000000..725a6302 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.cir.out @@ -0,0 +1,66 @@ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/10bitdac/10bitdac.cir + +r1 net-_r1-pad1_ net-_r1-pad2_ 1024k +r2 net-_r2-pad1_ net-_r1-pad2_ 512k +r3 net-_r3-pad1_ net-_r1-pad2_ 256k +r4 net-_r4-pad1_ net-_r1-pad2_ 128k +r5 net-_r5-pad1_ net-_r1-pad2_ 64k +r6 net-_r6-pad1_ net-_r1-pad2_ 32k +r7 net-_r7-pad1_ net-_r1-pad2_ 16k +r9 net-_r9-pad1_ net-_r1-pad2_ 8k +r10 net-_r10-pad1_ net-_r1-pad2_ 4k +r11 net-_r11-pad1_ net-_r1-pad2_ 2k +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port +* u2 net-_r1-pad2_ gnd net-_u1-pad11_ summer +* u3 net-_u1-pad1_ gnd net-_r1-pad1_ summer +* u8 net-_u1-pad2_ gnd net-_r2-pad1_ summer +* u4 net-_u1-pad3_ gnd net-_r3-pad1_ summer +* u5 net-_u1-pad4_ gnd net-_r4-pad1_ summer +* u9 net-_u1-pad5_ gnd net-_r5-pad1_ summer +* u10 net-_u1-pad6_ gnd net-_r6-pad1_ summer +* u6 net-_u1-pad7_ gnd net-_r7-pad1_ summer +* u7 net-_u1-pad8_ gnd net-_r9-pad1_ summer +* u12 net-_u1-pad9_ gnd net-_r10-pad1_ summer +* u11 net-_u1-pad10_ gnd net-_r11-pad1_ summer +a1 [net-_r1-pad2_ gnd ] net-_u1-pad11_ u2 +a2 [net-_u1-pad1_ gnd ] net-_r1-pad1_ u3 +a3 [net-_u1-pad2_ gnd ] net-_r2-pad1_ u8 +a4 [net-_u1-pad3_ gnd ] net-_r3-pad1_ u4 +a5 [net-_u1-pad4_ gnd ] net-_r4-pad1_ u5 +a6 [net-_u1-pad5_ gnd ] net-_r5-pad1_ u9 +a7 [net-_u1-pad6_ gnd ] net-_r6-pad1_ u10 +a8 [net-_u1-pad7_ gnd ] net-_r7-pad1_ u6 +a9 [net-_u1-pad8_ gnd ] net-_r9-pad1_ u7 +a10 [net-_u1-pad9_ gnd ] net-_r10-pad1_ u12 +a11 [net-_u1-pad10_ gnd ] net-_r11-pad1_ u11 +* Schematic Name: summer, NgSpice Name: summer +.model u2 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u3 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u8 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u4 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u5 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u9 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u10 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u6 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u7 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u12 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u11 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +.tran 1e-03 10e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.pro b/library/SubcircuitLibrary/10bitDAC/10bitDAC.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.sch b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sch new file mode 100644 index 00000000..09d81434 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sch @@ -0,0 +1,555 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:10bitDAC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 61DEB37D +P 4400 2250 +F 0 "R1" H 4450 2380 50 0000 C CNN +F 1 "1024k" H 4450 2200 50 0000 C CNN +F 2 "" H 4450 2230 30 0000 C CNN +F 3 "" V 4450 2300 30 0000 C CNN + 1 4400 2250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 61DEB37E +P 4450 2550 +F 0 "R2" H 4500 2680 50 0000 C CNN +F 1 "512k" H 4500 2500 50 0000 C CNN +F 2 "" H 4500 2530 30 0000 C CNN +F 3 "" V 4500 2600 30 0000 C CNN + 1 4450 2550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 61DEB37F +P 4450 2850 +F 0 "R3" H 4500 2980 50 0000 C CNN +F 1 "256k" H 4500 2800 50 0000 C CNN +F 2 "" H 4500 2830 30 0000 C CNN +F 3 "" V 4500 2900 30 0000 C CNN + 1 4450 2850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 61DEB380 +P 4450 3200 +F 0 "R4" H 4500 3330 50 0000 C CNN +F 1 "128k" H 4500 3150 50 0000 C CNN +F 2 "" H 4500 3180 30 0000 C CNN +F 3 "" V 4500 3250 30 0000 C CNN + 1 4450 3200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 61DEB381 +P 4450 3550 +F 0 "R5" H 4500 3680 50 0000 C CNN +F 1 "64k" H 4500 3500 50 0000 C CNN +F 2 "" H 4500 3530 30 0000 C CNN +F 3 "" V 4500 3600 30 0000 C CNN + 1 4450 3550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 61DEB382 +P 4450 3900 +F 0 "R6" H 4500 4030 50 0000 C CNN +F 1 "32k" H 4500 3850 50 0000 C CNN +F 2 "" H 4500 3880 30 0000 C CNN +F 3 "" V 4500 3950 30 0000 C CNN + 1 4450 3900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 61DEB383 +P 4450 4250 +F 0 "R7" H 4500 4380 50 0000 C CNN +F 1 "16k" H 4500 4200 50 0000 C CNN +F 2 "" H 4500 4230 30 0000 C CNN +F 3 "" V 4500 4300 30 0000 C CNN + 1 4450 4250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 61DEB384 +P 4450 4600 +F 0 "R9" H 4500 4730 50 0000 C CNN +F 1 "8k" H 4500 4550 50 0000 C CNN +F 2 "" H 4500 4580 30 0000 C CNN +F 3 "" V 4500 4650 30 0000 C CNN + 1 4450 4600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 61DEB385 +P 4450 4900 +F 0 "R10" H 4500 5030 50 0000 C CNN +F 1 "4k" H 4500 4850 50 0000 C CNN +F 2 "" H 4500 4880 30 0000 C CNN +F 3 "" V 4500 4950 30 0000 C CNN + 1 4450 4900 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 61DEB386 +P 4400 5200 +F 0 "R11" H 4450 5330 50 0000 C CNN +F 1 "2k" H 4450 5150 50 0000 C CNN +F 2 "" H 4450 5180 30 0000 C CNN +F 3 "" V 4450 5250 30 0000 C CNN + 1 4400 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 61DEFF7E +P 2100 6350 +F 0 "U1" H 2150 6450 30 0000 C CNN +F 1 "PORT" H 2100 6350 30 0000 C CNN +F 2 "" H 2100 6350 60 0000 C CNN +F 3 "" H 2100 6350 60 0000 C CNN + 10 2100 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 61DEFFF5 +P 2100 5800 +F 0 "U1" H 2150 5900 30 0000 C CNN +F 1 "PORT" H 2100 5800 30 0000 C CNN +F 2 "" H 2100 5800 60 0000 C CNN +F 3 "" H 2100 5800 60 0000 C CNN + 9 2100 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 61DF0058 +P 2050 5250 +F 0 "U1" H 2100 5350 30 0000 C CNN +F 1 "PORT" H 2050 5250 30 0000 C CNN +F 2 "" H 2050 5250 60 0000 C CNN +F 3 "" H 2050 5250 60 0000 C CNN + 8 2050 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 61DF00BB +P 2050 4650 +F 0 "U1" H 2100 4750 30 0000 C CNN +F 1 "PORT" H 2050 4650 30 0000 C CNN +F 2 "" H 2050 4650 60 0000 C CNN +F 3 "" H 2050 4650 60 0000 C CNN + 7 2050 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 61DF0148 +P 2100 4000 +F 0 "U1" H 2150 4100 30 0000 C CNN +F 1 "PORT" H 2100 4000 30 0000 C CNN +F 2 "" H 2100 4000 60 0000 C CNN +F 3 "" H 2100 4000 60 0000 C CNN + 6 2100 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 61DF01D7 +P 2100 3450 +F 0 "U1" H 2150 3550 30 0000 C CNN +F 1 "PORT" H 2100 3450 30 0000 C CNN +F 2 "" H 2100 3450 60 0000 C CNN +F 3 "" H 2100 3450 60 0000 C CNN + 5 2100 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 61DF026C +P 2050 2900 +F 0 "U1" H 2100 3000 30 0000 C CNN +F 1 "PORT" H 2050 2900 30 0000 C CNN +F 2 "" H 2050 2900 60 0000 C CNN +F 3 "" H 2050 2900 60 0000 C CNN + 4 2050 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 61DF0309 +P 2050 2350 +F 0 "U1" H 2100 2450 30 0000 C CNN +F 1 "PORT" H 2050 2350 30 0000 C CNN +F 2 "" H 2050 2350 60 0000 C CNN +F 3 "" H 2050 2350 60 0000 C CNN + 3 2050 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 61DF03AE +P 2100 1850 +F 0 "U1" H 2150 1950 30 0000 C CNN +F 1 "PORT" H 2100 1850 30 0000 C CNN +F 2 "" H 2100 1850 60 0000 C CNN +F 3 "" H 2100 1850 60 0000 C CNN + 2 2100 1850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 61DF041D +P 2050 1250 +F 0 "U1" H 2100 1350 30 0000 C CNN +F 1 "PORT" H 2050 1250 30 0000 C CNN +F 2 "" H 2050 1250 60 0000 C CNN +F 3 "" H 2050 1250 60 0000 C CNN + 1 2050 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 61DF0D04 +P 7650 5200 +F 0 "U1" H 7700 5300 30 0000 C CNN +F 1 "PORT" H 7650 5200 30 0000 C CNN +F 2 "" H 7650 5200 60 0000 C CNN +F 3 "" H 7650 5200 60 0000 C CNN + 11 7650 5200 + -1 0 0 -1 +$EndComp +$Comp +L summer U2 +U 1 1 61DEBE2F +P 6550 4000 +F 0 "U2" H 6550 3950 60 0000 C CNN +F 1 "summer" H 6550 4050 60 0000 C CNN +F 2 "" H 6550 4000 60 0000 C CNN +F 3 "" H 6550 4000 60 0000 C CNN + 1 6550 4000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR2 +U 1 1 61DEBEC1 +P 6150 4150 +F 0 "#PWR2" H 6150 3900 50 0001 C CNN +F 1 "GND" H 6150 4000 50 0000 C CNN +F 2 "" H 6150 4150 50 0001 C CNN +F 3 "" H 6150 4150 50 0001 C CNN + 1 6150 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 4850 4650 4850 +Wire Wire Line + 5100 2200 5100 5150 +Wire Wire Line + 5100 5150 4600 5150 +Wire Wire Line + 4600 2200 5100 2200 +Connection ~ 5100 4850 +Wire Wire Line + 4650 2500 5100 2500 +Connection ~ 5100 2500 +Wire Wire Line + 4650 2800 5100 2800 +Connection ~ 5100 2800 +Wire Wire Line + 4650 3150 5100 3150 +Connection ~ 5100 3150 +Wire Wire Line + 4650 3500 5100 3500 +Connection ~ 5100 3500 +Connection ~ 5100 3850 +Wire Wire Line + 4650 4200 5100 4200 +Connection ~ 5100 4200 +Wire Wire Line + 4650 4550 5100 4550 +Connection ~ 5100 4550 +Connection ~ 5750 3850 +Wire Wire Line + 7050 4000 7050 5200 +Wire Wire Line + 7050 5200 7400 5200 +Wire Wire Line + 4650 3850 6150 3850 +Wire Wire Line + 3700 2200 4300 2200 +Wire Wire Line + 3600 2500 4350 2500 +Wire Wire Line + 3500 2800 4350 2800 +Wire Wire Line + 3700 3150 4350 3150 +Wire Wire Line + 3250 3500 4350 3500 +Wire Wire Line + 3250 3850 4350 3850 +Wire Wire Line + 3200 4200 4350 4200 +Wire Wire Line + 3250 4600 4350 4600 +Wire Wire Line + 4350 4600 4350 4550 +Wire Wire Line + 3300 4850 4350 4850 +Wire Wire Line + 3700 5150 4300 5150 +Wire Wire Line + 2350 5800 2400 5800 +$Comp +L summer U3 +U 1 1 62005AB8 +P 2700 1400 +F 0 "U3" H 2700 1350 60 0000 C CNN +F 1 "summer" H 2700 1450 60 0000 C CNN +F 2 "" H 2700 1400 60 0000 C CNN +F 3 "" H 2700 1400 60 0000 C CNN + 1 2700 1400 + 1 0 0 -1 +$EndComp +$Comp +L summer U8 +U 1 1 62006578 +P 2750 2000 +F 0 "U8" H 2750 1950 60 0000 C CNN +F 1 "summer" H 2750 2050 60 0000 C CNN +F 2 "" H 2750 2000 60 0000 C CNN +F 3 "" H 2750 2000 60 0000 C CNN + 1 2750 2000 + 1 0 0 -1 +$EndComp +$Comp +L summer U4 +U 1 1 6200669E +P 2700 2500 +F 0 "U4" H 2700 2450 60 0000 C CNN +F 1 "summer" H 2700 2550 60 0000 C CNN +F 2 "" H 2700 2500 60 0000 C CNN +F 3 "" H 2700 2500 60 0000 C CNN + 1 2700 2500 + 1 0 0 -1 +$EndComp +$Comp +L summer U5 +U 1 1 620067C5 +P 2700 3050 +F 0 "U5" H 2700 3000 60 0000 C CNN +F 1 "summer" H 2700 3100 60 0000 C CNN +F 2 "" H 2700 3050 60 0000 C CNN +F 3 "" H 2700 3050 60 0000 C CNN + 1 2700 3050 + 1 0 0 -1 +$EndComp +$Comp +L summer U9 +U 1 1 62006869 +P 2750 3600 +F 0 "U9" H 2750 3550 60 0000 C CNN +F 1 "summer" H 2750 3650 60 0000 C CNN +F 2 "" H 2750 3600 60 0000 C CNN +F 3 "" H 2750 3600 60 0000 C CNN + 1 2750 3600 + 1 0 0 -1 +$EndComp +$Comp +L summer U10 +U 1 1 62006A63 +P 2750 4150 +F 0 "U10" H 2750 4100 60 0000 C CNN +F 1 "summer" H 2750 4200 60 0000 C CNN +F 2 "" H 2750 4150 60 0000 C CNN +F 3 "" H 2750 4150 60 0000 C CNN + 1 2750 4150 + 1 0 0 -1 +$EndComp +$Comp +L summer U6 +U 1 1 62006B47 +P 2700 4800 +F 0 "U6" H 2700 4750 60 0000 C CNN +F 1 "summer" H 2700 4850 60 0000 C CNN +F 2 "" H 2700 4800 60 0000 C CNN +F 3 "" H 2700 4800 60 0000 C CNN + 1 2700 4800 + 1 0 0 -1 +$EndComp +$Comp +L summer U7 +U 1 1 62006C2E +P 2700 5400 +F 0 "U7" H 2700 5350 60 0000 C CNN +F 1 "summer" H 2700 5450 60 0000 C CNN +F 2 "" H 2700 5400 60 0000 C CNN +F 3 "" H 2700 5400 60 0000 C CNN + 1 2700 5400 + 1 0 0 -1 +$EndComp +$Comp +L summer U12 +U 1 1 62006D0E +P 2800 5950 +F 0 "U12" H 2800 5900 60 0000 C CNN +F 1 "summer" H 2800 6000 60 0000 C CNN +F 2 "" H 2800 5950 60 0000 C CNN +F 3 "" H 2800 5950 60 0000 C CNN + 1 2800 5950 + 1 0 0 -1 +$EndComp +$Comp +L summer U11 +U 1 1 62006DC0 +P 2750 6500 +F 0 "U11" H 2750 6450 60 0000 C CNN +F 1 "summer" H 2750 6550 60 0000 C CNN +F 2 "" H 2750 6500 60 0000 C CNN +F 3 "" H 2750 6500 60 0000 C CNN + 1 2750 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3200 1400 3700 1400 +Wire Wire Line + 3700 1400 3700 2200 +Wire Wire Line + 3600 2500 3600 2000 +Wire Wire Line + 3600 2000 3250 2000 +Wire Wire Line + 3200 2500 3500 2500 +Wire Wire Line + 3500 2500 3500 2800 +Wire Wire Line + 3200 3050 3700 3050 +Wire Wire Line + 3700 3050 3700 3150 +Wire Wire Line + 3250 3500 3250 3600 +Wire Wire Line + 3250 3850 3250 4150 +Wire Wire Line + 3200 4200 3200 4800 +Wire Wire Line + 3250 4600 3250 5400 +Wire Wire Line + 3250 5400 3200 5400 +Wire Wire Line + 3300 4850 3300 5950 +Wire Wire Line + 3700 5150 3700 6500 +Wire Wire Line + 3700 6500 3250 6500 +$Comp +L GND #PWR1 +U 1 1 620071B7 +P 1400 6750 +F 0 "#PWR1" H 1400 6500 50 0001 C CNN +F 1 "GND" H 1400 6600 50 0000 C CNN +F 2 "" H 1400 6750 50 0001 C CNN +F 3 "" H 1400 6750 50 0001 C CNN + 1 1400 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2350 6650 1400 6650 +Wire Wire Line + 1400 6650 1400 6750 +Wire Wire Line + 2400 6100 1450 6100 +Wire Wire Line + 1450 4300 1450 6650 +Connection ~ 1450 6650 +Wire Wire Line + 2300 5550 1450 5550 +Connection ~ 1450 6100 +Wire Wire Line + 2300 4950 1450 4950 +Connection ~ 1450 5550 +Wire Wire Line + 2350 4300 1450 4300 +Connection ~ 1450 4950 +Wire Wire Line + 2350 3750 1450 3750 +Wire Wire Line + 1450 1550 1450 4350 +Connection ~ 1450 4350 +Wire Wire Line + 2300 3200 1450 3200 +Connection ~ 1450 3750 +Wire Wire Line + 2300 2650 1450 2650 +Connection ~ 1450 3200 +Wire Wire Line + 2350 2150 1450 2150 +Connection ~ 1450 2650 +Wire Wire Line + 2300 1550 1450 1550 +Connection ~ 1450 2150 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC.sub b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sub new file mode 100644 index 00000000..0a0445d9 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC.sub @@ -0,0 +1,61 @@ +* Subcircuit 10bitDAC + +.subckt 10bitDAC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/10bitdac/10bitdac.cir +r1 net-_r1-pad1_ net-_r1-pad2_ 1024k +r2 net-_r2-pad1_ net-_r1-pad2_ 512k +r3 net-_r3-pad1_ net-_r1-pad2_ 256k +r4 net-_r4-pad1_ net-_r1-pad2_ 128k +r5 net-_r5-pad1_ net-_r1-pad2_ 64k +r6 net-_r6-pad1_ net-_r1-pad2_ 32k +r7 net-_r7-pad1_ net-_r1-pad2_ 16k +r9 net-_r9-pad1_ net-_r1-pad2_ 8k +r10 net-_r10-pad1_ net-_r1-pad2_ 4k +r11 net-_r11-pad1_ net-_r1-pad2_ 2k +* u2 net-_r1-pad2_ gnd net-_u1-pad11_ summer +* u3 net-_u1-pad1_ gnd net-_r1-pad1_ summer +* u8 net-_u1-pad2_ gnd net-_r2-pad1_ summer +* u4 net-_u1-pad3_ gnd net-_r3-pad1_ summer +* u5 net-_u1-pad4_ gnd net-_r4-pad1_ summer +* u9 net-_u1-pad5_ gnd net-_r5-pad1_ summer +* u10 net-_u1-pad6_ gnd net-_r6-pad1_ summer +* u6 net-_u1-pad7_ gnd net-_r7-pad1_ summer +* u7 net-_u1-pad8_ gnd net-_r9-pad1_ summer +* u12 net-_u1-pad9_ gnd net-_r10-pad1_ summer +* u11 net-_u1-pad10_ gnd net-_r11-pad1_ summer +a1 [net-_r1-pad2_ gnd ] net-_u1-pad11_ u2 +a2 [net-_u1-pad1_ gnd ] net-_r1-pad1_ u3 +a3 [net-_u1-pad2_ gnd ] net-_r2-pad1_ u8 +a4 [net-_u1-pad3_ gnd ] net-_r3-pad1_ u4 +a5 [net-_u1-pad4_ gnd ] net-_r4-pad1_ u5 +a6 [net-_u1-pad5_ gnd ] net-_r5-pad1_ u9 +a7 [net-_u1-pad6_ gnd ] net-_r6-pad1_ u10 +a8 [net-_u1-pad7_ gnd ] net-_r7-pad1_ u6 +a9 [net-_u1-pad8_ gnd ] net-_r9-pad1_ u7 +a10 [net-_u1-pad9_ gnd ] net-_r10-pad1_ u12 +a11 [net-_u1-pad10_ gnd ] net-_r11-pad1_ u11 +* Schematic Name: summer, NgSpice Name: summer +.model u2 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u3 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u8 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u4 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u5 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u9 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u10 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u6 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u7 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u12 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Schematic Name: summer, NgSpice Name: summer +.model u11 summer(in_offset=[0.0 0.0 ] in_gain=[1.0 1.0 ] out_gain=1.0 out_offset=0.0 ) +* Control Statements + +.ends 10bitDAC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml b/library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml new file mode 100644 index 00000000..25253eac --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/10bitDAC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">10</field1></v1></source><model><u2 name="type">summer<field1 name="Enter offset for input (default=0.0) 1" /><field2 name="Enter offset for input (default=0.0) 2" /><field3 name="Enter gain for input(default=1.0) 1" /><field4 name="Enter gain for input(default=1.0) 2" /><field5 name="Enter gain for output (default=1.0)" /><field6 name="Enter offset for output (default=0.0)" /></u2><u12 name="type">summer<field1 name="Enter offset for input (default=0.0) 1" /><field2 name="Enter offset for input (default=0.0) 2" /><field3 name="Enter gain for input(default=1.0) 1" /><field4 name="Enter gain for input(default=1.0) 2" /><field5 name="Enter gain for output (default=1.0)" /><field6 name="Enter offset for output (default=0.0)" /></u12><u3 name="type">gain<field7 name="Enter offset for input (default=0.0)" /><field8 name="Enter gain (default=1.0) 1" /><field9 name="Enter offset for output (default=0.0)" /></u3><u4 name="type">gain<field10 name="Enter offset for input (default=0.0)" /><field11 name="Enter gain (default=1.0) 1" /><field12 name="Enter offset for output (default=0.0)" /></u4><u5 name="type">gain<field13 name="Enter offset for input (default=0.0)" /><field14 name="Enter gain (default=1.0) 1" /><field15 name="Enter offset for output (default=0.0)" /></u5><u6 name="type">gain<field16 name="Enter offset for input (default=0.0)" /><field17 name="Enter gain (default=1.0) 1" /><field18 name="Enter offset for output (default=0.0)" /></u6><u7 name="type">gain<field19 name="Enter offset for input (default=0.0)" /><field20 name="Enter gain (default=1.0) 1" /><field21 name="Enter offset for output (default=0.0)" /></u7><u8 name="type">gain<field22 name="Enter offset for input (default=0.0)" /><field23 name="Enter gain (default=1.0) 1" /><field24 name="Enter offset for output (default=0.0)" /></u8><u9 name="type">gain<field25 name="Enter offset for input (default=0.0)" /><field26 name="Enter gain (default=1.0) 1" /><field27 name="Enter offset for output (default=0.0)" /></u9><u10 name="type">gain<field28 name="Enter offset for input (default=0.0)" /><field29 name="Enter gain (default=1.0) 1" /><field30 name="Enter offset for output (default=0.0)" /></u10><u12 name="type">gain<field31 name="Enter offset for input (default=0.0)" /><field32 name="Enter gain (default=1.0) 1" /><field33 name="Enter offset for output (default=0.0)" /></u12><u11 name="type">gain<field34 name="Enter offset for input (default=0.0)" /><field35 name="Enter gain (default=1.0) 1" /><field36 name="Enter offset for output (default=0.0)" /></u11><u3 name="type">summer<field7 name="Enter offset for input (default=0.0) 1" /><field8 name="Enter offset for input (default=0.0) 2" /><field9 name="Enter gain for input(default=1.0) 1" /><field10 name="Enter gain for input(default=1.0) 2" /><field11 name="Enter gain for output (default=1.0)" /><field12 name="Enter offset for output (default=0.0)" /></u3><u8 name="type">summer<field13 name="Enter offset for input (default=0.0) 1" /><field14 name="Enter offset for input (default=0.0) 2" /><field15 name="Enter gain for input(default=1.0) 1" /><field16 name="Enter gain for input(default=1.0) 2" /><field17 name="Enter gain for output (default=1.0)" /><field18 name="Enter offset for output (default=0.0)" /></u8><u4 name="type">summer<field19 name="Enter offset for input (default=0.0) 1" /><field20 name="Enter offset for input (default=0.0) 2" /><field21 name="Enter gain for input(default=1.0) 1" /><field22 name="Enter gain for input(default=1.0) 2" /><field23 name="Enter gain for output (default=1.0)" /><field24 name="Enter offset for output (default=0.0)" /></u4><u5 name="type">summer<field25 name="Enter offset for input (default=0.0) 1" /><field26 name="Enter offset for input (default=0.0) 2" /><field27 name="Enter gain for input(default=1.0) 1" /><field28 name="Enter gain for input(default=1.0) 2" /><field29 name="Enter gain for output (default=1.0)" /><field30 name="Enter offset for output (default=0.0)" /></u5><u9 name="type">summer<field31 name="Enter offset for input (default=0.0) 1" /><field32 name="Enter offset for input (default=0.0) 2" /><field33 name="Enter gain for input(default=1.0) 1" /><field34 name="Enter gain for input(default=1.0) 2" /><field35 name="Enter gain for output (default=1.0)" /><field36 name="Enter offset for output (default=0.0)" /></u9><u10 name="type">summer<field37 name="Enter offset for input (default=0.0) 1" /><field38 name="Enter offset for input (default=0.0) 2" /><field39 name="Enter gain for input(default=1.0) 1" /><field40 name="Enter gain for input(default=1.0) 2" /><field41 name="Enter gain for output (default=1.0)" /><field42 name="Enter offset for output (default=0.0)" /></u10><u6 name="type">summer<field43 name="Enter offset for input (default=0.0) 1" /><field44 name="Enter offset for input (default=0.0) 2" /><field45 name="Enter gain for input(default=1.0) 1" /><field46 name="Enter gain for input(default=1.0) 2" /><field47 name="Enter gain for output (default=1.0)" /><field48 name="Enter offset for output (default=0.0)" /></u6><u7 name="type">summer<field49 name="Enter offset for input (default=0.0) 1" /><field50 name="Enter offset for input (default=0.0) 2" /><field51 name="Enter gain for input(default=1.0) 1" /><field52 name="Enter gain for input(default=1.0) 2" /><field53 name="Enter gain for output (default=1.0)" /><field54 name="Enter offset for output (default=0.0)" /></u7><u11 name="type">summer<field61 name="Enter offset for input (default=0.0) 1" /><field62 name="Enter offset for input (default=0.0) 2" /><field63 name="Enter gain for input(default=1.0) 1" /><field64 name="Enter gain for input(default=1.0) 2" /><field65 name="Enter gain for output (default=1.0)" /><field66 name="Enter offset for output (default=0.0)" /></u11></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/10bitDAC/analysis b/library/SubcircuitLibrary/10bitDAC/analysis new file mode 100644 index 00000000..14b93089 --- /dev/null +++ b/library/SubcircuitLibrary/10bitDAC/analysis @@ -0,0 +1 @@ +.tran 1e-03 10e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator-cache.lib b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator-cache.lib new file mode 100644 index 00000000..3b31c94c --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator-cache.lib @@ -0,0 +1,115 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir new file mode 100644 index 00000000..3abc6d22 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir @@ -0,0 +1,14 @@ +* /home/sumanto/eSim-2.1/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jan 12 16:16:30 2022 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 Net-_R3-Pad1_ GND 1k +C2 Net-_C2-Pad1_ GND 0.01u +X1 GND Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_U1-Pad1_ Net-_C2-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ LM555N +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_R3-Pad1_ Net-_U1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir.out b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir.out new file mode 100644 index 00000000..3ca86ff5 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.cir.out @@ -0,0 +1,16 @@ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/clock_pulse_generator/clock_pulse_generator.cir + +.include lm555n.sub +r3 net-_r3-pad1_ gnd 1k +c2 net-_c2-pad1_ gnd 0.01u +x1 gnd net-_u1-pad3_ net-_r3-pad1_ net-_u1-pad1_ net-_c2-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ lm555n +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_r3-pad1_ port +.tran 1e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.pro b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sch b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sch new file mode 100644 index 00000000..55c5c45f --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sch @@ -0,0 +1,206 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:Clock_pulse_generator-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_R R3 +U 1 1 61DEABA3 +P 6950 4150 +F 0 "R3" H 7000 4280 50 0000 C CNN +F 1 "1k" H 7000 4100 50 0000 C CNN +F 2 "" H 7000 4130 30 0000 C CNN +F 3 "" V 7000 4200 30 0000 C CNN + 1 6950 4150 + 0 1 1 0 +$EndComp +$Comp +L eSim_C C2 +U 1 1 61DEABA9 +P 4850 4600 +F 0 "C2" H 4875 4700 50 0000 L CNN +F 1 "0.01u" H 4875 4500 50 0000 L CNN +F 2 "" H 4888 4450 30 0000 C CNN +F 3 "" H 4850 4600 60 0000 C CNN + 1 4850 4600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 61DEABAA +P 5650 4950 +F 0 "#PWR1" H 5650 4700 50 0001 C CNN +F 1 "GND" H 5650 4800 50 0000 C CNN +F 2 "" H 5650 4950 50 0001 C CNN +F 3 "" H 5650 4950 50 0001 C CNN + 1 5650 4950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 4000 6500 4000 +Wire Wire Line + 6500 4000 6500 3350 +Wire Wire Line + 6500 3350 4500 3350 +Wire Wire Line + 4500 3350 4500 3800 +Wire Wire Line + 4500 3800 4250 3800 +Wire Wire Line + 5100 4250 4650 4250 +Wire Wire Line + 4650 4250 4650 3100 +Wire Wire Line + 3400 3100 5650 3100 +Wire Wire Line + 5650 3100 5650 3400 +Connection ~ 4650 3100 +Wire Wire Line + 6200 4250 6450 4250 +Wire Wire Line + 6450 4250 6450 5200 +Wire Wire Line + 6450 5200 4550 5200 +Wire Wire Line + 4550 5200 4550 3750 +Wire Wire Line + 4550 3750 5100 3750 +Connection ~ 4550 4350 +Wire Wire Line + 4850 4450 4850 4000 +Wire Wire Line + 4850 4000 5100 4000 +Wire Wire Line + 4850 4850 7000 4850 +Wire Wire Line + 5650 4600 5650 4950 +Wire Wire Line + 6200 3750 7000 3750 +Wire Wire Line + 7000 3750 7000 4050 +Wire Wire Line + 7000 4850 7000 4350 +Connection ~ 5650 4850 +$Comp +L LM555N X1 +U 1 1 61DEABAD +P 5650 4000 +F 0 "X1" H 5650 3950 60 0000 C CNN +F 1 "LM555N" H 5650 4100 60 0000 C CNN +F 2 "" H 5600 4000 60 0000 C CNN +F 3 "" H 5600 4000 60 0000 C CNN + 1 5650 4000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 4350 4250 4350 +$Comp +L PORT U1 +U 1 1 61DEAE73 +P 3150 3100 +F 0 "U1" H 3200 3200 30 0000 C CNN +F 1 "PORT" H 3150 3100 30 0000 C CNN +F 2 "" H 3150 3100 60 0000 C CNN +F 3 "" H 3150 3100 60 0000 C CNN + 1 3150 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 4850 4850 4750 +$Comp +L PORT U1 +U 2 1 61DEB4B4 +P 4000 3800 +F 0 "U1" H 4050 3900 30 0000 C CNN +F 1 "PORT" H 4000 3800 30 0000 C CNN +F 2 "" H 4000 3800 60 0000 C CNN +F 3 "" H 4000 3800 60 0000 C CNN + 2 4000 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 61DEB51D +P 4000 4350 +F 0 "U1" H 4050 4450 30 0000 C CNN +F 1 "PORT" H 4000 4350 30 0000 C CNN +F 2 "" H 4000 4350 60 0000 C CNN +F 3 "" H 4000 4350 60 0000 C CNN + 3 4000 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 61DEB688 +P 7250 3750 +F 0 "U1" H 7300 3850 30 0000 C CNN +F 1 "PORT" H 7250 3750 30 0000 C CNN +F 2 "" H 7250 3750 60 0000 C CNN +F 3 "" H 7250 3750 60 0000 C CNN + 4 7250 3750 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 61DEB2E9 +P 4100 4500 +F 0 "U1" H 4150 4600 30 0000 C CNN +F 1 "PORT" H 4100 4500 30 0000 C CNN +F 2 "" H 4100 4500 60 0000 C CNN +F 3 "" H 4100 4500 60 0000 C CNN + 5 4100 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 4500 4550 4500 +Connection ~ 4550 4500 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sub b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sub new file mode 100644 index 00000000..6c5c8a10 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator.sub @@ -0,0 +1,11 @@ +* Subcircuit Clock_pulse_generator +.include lm555n.sub + +.subckt Clock_pulse_generator net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_r3-pad1_ +* /home/sumanto/esim-2.1/library/subcircuitlibrary/clock_pulse_generator/clock_pulse_generator.cir +r3 net-_r3-pad1_ gnd 1k +c2 net-_c2-pad1_ gnd 0.01u +x1 gnd net-_u1-pad3_ net-_r3-pad1_ net-_u1-pad1_ net-_c2-pad1_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ lm555n +* Control Statements + +.ends Clock_pulse_generator
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator_Previous_Values.xml b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator_Previous_Values.xml new file mode 100644 index 00000000..2f8011a8 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/Clock_pulse_generator_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>/home/sumanto/eSim-2.1/library/SubcircuitLibrary/lm555n</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/NPN.lib b/library/SubcircuitLibrary/Clock_pulse_generator/NPN.lib new file mode 100755 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/analysis b/library/SubcircuitLibrary/Clock_pulse_generator/analysis new file mode 100644 index 00000000..f496aec4 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/analysis @@ -0,0 +1 @@ +.tran 1e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-cache.lib b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-cache.lib new file mode 100755 index 00000000..824af11e --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-cache.lib @@ -0,0 +1,205 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND-RESCUE-lm555n +# +DEF ~GND-RESCUE-lm555n #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND-RESCUE-lm555n" 0 -70 30 H I C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 75 50 H I C CNN +F1 "PWR_FLAG" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +X pwr 1 0 0 0 U 50 50 0 0 w +P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N +ENDDRAW +ENDDEF +# +# R-RESCUE-lm555n +# +DEF R-RESCUE-lm555n R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R-RESCUE-lm555n" 0 0 50 V V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +$FPLIST + R? + SM0603 + SM0805 + R?-* +$ENDFPLIST +DRAW +S -40 150 40 -150 0 1 12 N +X ~ 1 0 250 100 D 60 60 1 1 P +X ~ 2 0 -250 100 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +# VCVS +# +DEF VCVS E 0 40 Y Y 1 F N +F0 "E" 0 150 50 H V C CNN +F1 "VCVS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_srlatch +# +DEF d_srlatch U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srlatch" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X EN 3 -800 0 200 R 50 50 1 1 I +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# limit +# +DEF limit U 0 40 Y Y 1 F N +F0 "U" 50 -50 60 H V C CNN +F1 "limit" 50 50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +C 300 0 0 0 1 0 N +P 4 0 1 0 -200 200 -200 -200 400 0 -200 200 N +X IN 1 -400 0 200 R 50 50 1 1 I +X OUT 2 600 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-rescue.lib b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-rescue.lib new file mode 100755 index 00000000..fffeca36 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n-rescue.lib @@ -0,0 +1,18 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# d_inverter-RESCUE-lm555n +# +DEF d_inverter-RESCUE-lm555n U 0 40 Y Y 1 F N +F0 "U" -150 100 40 H V C CNN +F1 "d_inverter-RESCUE-lm555n" 100 100 40 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +P 4 0 1 0 -100 -100 -100 100 100 0 -100 -100 N +X in 1 -250 0 150 R 25 25 1 1 I +X out 2 250 0 150 L 25 25 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir new file mode 100755 index 00000000..682d4945 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir @@ -0,0 +1,31 @@ +* /home/ash98/Downloads/lm555n/lm555n.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 24 15:58:04 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +E2 Net-_E2-Pad1_ GND /c /d 10000 +U1 Net-_Q1-Pad3_ /d Net-_U1-Pad3_ Net-_U1-Pad4_ /a /b Net-_Q1-Pad1_ Net-_R1-Pad1_ PORT +R8 Net-_R8-Pad1_ Net-_Q1-Pad2_ 1500 +R7 Net-_E2-Pad1_ Net-_R7-Pad2_ 25 +R6 Net-_E1-Pad1_ Net-_R6-Pad2_ 25 +E1 Net-_E1-Pad1_ GND /b /a 10000 +R4 /b /a 2E6 +R5 /c /d 2E6 +R3 /c Net-_Q1-Pad3_ 5000 +R2 /a /c 5000 +R1 Net-_R1-Pad1_ /a 5000 +U8 Net-_U4-Pad2_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U7-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad6_ Net-_U10-Pad1_ d_srlatch +U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ adc_bridge_1 +U4 Net-_U3-Pad2_ Net-_U4-Pad2_ adc_bridge_1 +U6 Net-_U2-Pad2_ Net-_U6-Pad2_ adc_bridge_1 +U3 Net-_R7-Pad2_ Net-_U3-Pad2_ limit +U2 Net-_R6-Pad2_ Net-_U2-Pad2_ limit +U9 Net-_U8-Pad6_ Net-_U1-Pad3_ dac_bridge_1 +U10 Net-_U10-Pad1_ Net-_R8-Pad1_ dac_bridge_1 +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN + +.end diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir.out b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir.out new file mode 100755 index 00000000..a81070a1 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.cir.out @@ -0,0 +1,42 @@ +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +.include npn_1.lib +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +u1 22 14 7 6 15 16 3 13 port +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) + +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.pro b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.pro new file mode 100755 index 00000000..662ea66d --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.pro @@ -0,0 +1,44 @@ +update=Wed Mar 18 14:16:41 2020 +last_client=eeschema +[eeschema] +version=1 +LibDir=/home/yogesh/FreeEDA/library +[eeschema/libraries] +LibName1=lm555n-rescue +LibName2=power +LibName3=transistors +LibName4=conn +LibName5=regul +LibName6=74xx +LibName7=cmos4000 +LibName8=adc-dac +LibName9=memory +LibName10=xilinx +LibName11=microcontrollers +LibName12=dsp +LibName13=microchip +LibName14=analog_switches +LibName15=motorola +LibName16=texas +LibName17=intel +LibName18=audio +LibName19=interface +LibName20=digital-audio +LibName21=philips +LibName22=display +LibName23=cypress +LibName24=siliconi +LibName25=opto +LibName26=atmel +LibName27=contrib +LibName28=valves +LibName29=eSim_User +LibName30=eSim_Subckt +LibName31=eSim_Sources +LibName32=eSim_Power +LibName33=eSim_Plot +LibName34=eSim_Miscellaneous +LibName35=eSim_Hybrid +LibName36=eSim_Digital +LibName37=eSim_Devices +LibName38=eSim_Analog diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sch b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sch new file mode 100755 index 00000000..28110b13 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sch @@ -0,0 +1,518 @@ +EESchema Schematic File Version 2 +LIBS:lm555n-rescue +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_User +LIBS:eSim_Subckt +LIBS:eSim_Sources +LIBS:eSim_PSpice +LIBS:eSim_Power +LIBS:eSim_Plot +LIBS:eSim_Miscellaneous +LIBS:eSim_Hybrid +LIBS:eSim_Digital +LIBS:eSim_Devices +LIBS:eSim_Analog +LIBS:lm555n-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "17 dec 2012" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Text Notes 3700 3050 0 60 ~ 0 +IC 555 +Wire Wire Line + 2650 3000 2850 3000 +Wire Wire Line + 2650 4750 2650 4650 +Connection ~ 2350 3550 +Connection ~ 2350 4900 +Wire Wire Line + 2350 4100 2350 4200 +Wire Wire Line + 9100 4900 9100 4800 +Wire Wire Line + 8500 4600 8500 4250 +Wire Wire Line + 3350 3250 3050 3250 +Wire Wire Line + 3050 3250 3050 3750 +Wire Wire Line + 3500 4350 3500 4500 +Wire Wire Line + 3650 3550 4200 3550 +Wire Wire Line + 3850 3250 4200 3250 +Wire Wire Line + 3150 3550 3150 3700 +Wire Wire Line + 3150 3700 3500 3700 +Wire Wire Line + 3500 3700 3500 3750 +Connection ~ 3500 4450 +Wire Wire Line + 3700 4450 3700 4400 +Wire Wire Line + 3050 4350 3050 4450 +Wire Wire Line + 3050 4450 3700 4450 +Wire Wire Line + 9100 4250 9000 4250 +Wire Wire Line + 9100 4400 9100 4350 +Wire Wire Line + 9100 4350 9200 4350 +Wire Wire Line + 10100 2950 10350 2950 +Wire Wire Line + 2350 4900 2350 4700 +Wire Wire Line + 2350 3500 2350 3600 +Wire Wire Line + 2250 3000 2350 3000 +Wire Wire Line + 2350 4150 2650 4150 +Connection ~ 2350 4150 +Wire Wire Line + 2250 3550 2650 3550 +Wire Wire Line + 2650 3550 2650 3500 +Wire Wire Line + 4300 4750 4300 4650 +Text Label 2800 4100 0 60 ~ 0 +d +$Comp +L VCVS E2 +U 1 1 50AA12FF +P 3000 4050 +F 0 "E2" H 2800 4150 50 0000 C CNN +F 1 "10000" H 2800 4000 50 0000 C CNN +F 2 "" H 3000 4050 60 0001 C CNN +F 3 "" H 3000 4050 60 0001 C CNN + 1 3000 4050 + 0 1 1 0 +$EndComp +$Comp +L PWR_FLAG #FLG01 +U 1 1 50AA39A3 +P 3700 4400 +F 0 "#FLG01" H 3700 4670 30 0001 C CNN +F 1 "PWR_FLAG" H 3700 4630 30 0000 C CNN +F 2 "" H 3700 4400 60 0001 C CNN +F 3 "" H 3700 4400 60 0001 C CNN + 1 3700 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 50AA2210 +P 2000 3550 +F 0 "U1" H 2000 3500 30 0000 C CNN +F 1 "PORT" H 2000 3550 30 0000 C CNN +F 2 "" H 2000 3550 60 0001 C CNN +F 3 "" H 2000 3550 60 0001 C CNN + 5 2000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 50AA21C7 +P 2000 4900 +F 0 "U1" H 2000 4850 30 0000 C CNN +F 1 "PORT" H 2000 4900 30 0000 C CNN +F 2 "" H 2000 4900 60 0001 C CNN +F 3 "" H 2000 4900 60 0001 C CNN + 1 2000 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 50AA21BC +P 2650 5000 +F 0 "U1" H 2650 4950 30 0000 C CNN +F 1 "PORT" H 2650 5000 30 0000 C CNN +F 2 "" H 2650 5000 60 0001 C CNN +F 3 "" H 2650 5000 60 0001 C CNN + 2 2650 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 50AA21A9 +P 4300 5000 +F 0 "U1" H 4300 4950 30 0000 C CNN +F 1 "PORT" H 4300 5000 30 0000 C CNN +F 2 "" H 4300 5000 60 0001 C CNN +F 3 "" H 4300 5000 60 0001 C CNN + 4 4300 5000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 50AA21A0 +P 9450 4350 +F 0 "U1" H 9450 4300 30 0000 C CNN +F 1 "PORT" H 9450 4350 30 0000 C CNN +F 2 "" H 9450 4350 60 0001 C CNN +F 3 "" H 9450 4350 60 0001 C CNN + 7 9450 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 50AA2181 +P 10600 2950 +F 0 "U1" H 10600 2900 30 0000 C CNN +F 1 "PORT" H 10600 2950 30 0000 C CNN +F 2 "" H 10600 2950 60 0001 C CNN +F 3 "" H 10600 2950 60 0001 C CNN + 3 10600 2950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 50AA2171 +P 3100 3000 +F 0 "U1" H 3100 2950 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0001 C CNN +F 3 "" H 3100 3000 60 0001 C CNN + 6 3100 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 50AA2162 +P 2000 3000 +F 0 "U1" H 2000 2950 30 0000 C CNN +F 1 "PORT" H 2000 3000 30 0000 C CNN +F 2 "" H 2000 3000 60 0001 C CNN +F 3 "" H 2000 3000 60 0001 C CNN + 8 2000 3000 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R8 +U 1 1 50AA20DA +P 8750 4250 +F 0 "R8" V 8830 4250 50 0000 C CNN +F 1 "1500" V 8750 4250 50 0000 C CNN +F 2 "" H 8750 4250 60 0001 C CNN +F 3 "" H 8750 4250 60 0001 C CNN + 1 8750 4250 + 0 1 1 0 +$EndComp +$Comp +L GND-RESCUE-lm555n #PWR02 +U 1 1 50AA140C +P 3500 4500 +F 0 "#PWR02" H 3500 4500 30 0001 C CNN +F 1 "GND" H 3500 4430 30 0001 C CNN +F 2 "" H 3500 4500 60 0001 C CNN +F 3 "" H 3500 4500 60 0001 C CNN + 1 3500 4500 + 1 0 0 -1 +$EndComp +Text Label 2800 4000 0 60 ~ 0 +c +Text Label 2650 4650 0 60 ~ 0 +d +Text Label 2650 4150 0 60 ~ 0 +c +$Comp +L R-RESCUE-lm555n R7 +U 1 1 50AA12F7 +P 3600 3250 +F 0 "R7" V 3680 3250 50 0000 C CNN +F 1 "25" V 3600 3250 50 0000 C CNN +F 2 "" H 3600 3250 60 0001 C CNN +F 3 "" H 3600 3250 60 0001 C CNN + 1 3600 3250 + 0 -1 -1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R6 +U 1 1 50AA12B0 +P 3400 3550 +F 0 "R6" V 3480 3550 50 0000 C CNN +F 1 "25" V 3400 3550 50 0000 C CNN +F 2 "" H 3400 3550 60 0001 C CNN +F 3 "" H 3400 3550 60 0001 C CNN + 1 3400 3550 + 0 -1 -1 0 +$EndComp +Text Label 3250 4000 0 60 ~ 0 +b +Text Label 3250 4100 0 60 ~ 0 +a +Text Label 2650 3000 0 60 ~ 0 +b +Text Label 2650 3500 0 60 ~ 0 +a +$Comp +L VCVS E1 +U 1 1 50AA11B6 +P 3450 4050 +F 0 "E1" H 3250 4150 50 0000 C CNN +F 1 "10000" H 3250 4000 50 0000 C CNN +F 2 "" H 3450 4050 60 0001 C CNN +F 3 "" H 3450 4050 60 0001 C CNN + 1 3450 4050 + 0 1 1 0 +$EndComp +$Comp +L R-RESCUE-lm555n R4 +U 1 1 50A9E00B +P 2650 3250 +F 0 "R4" V 2730 3250 50 0000 C CNN +F 1 "2E6" V 2650 3250 50 0000 C CNN +F 2 "" H 2650 3250 60 0001 C CNN +F 3 "" H 2650 3250 60 0001 C CNN + 1 2650 3250 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R5 +U 1 1 50A9E001 +P 2650 4400 +F 0 "R5" V 2730 4400 50 0000 C CNN +F 1 "2E6" V 2650 4400 50 0000 C CNN +F 2 "" H 2650 4400 60 0001 C CNN +F 3 "" H 2650 4400 60 0001 C CNN + 1 2650 4400 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R3 +U 1 1 50A9DF09 +P 2350 4450 +F 0 "R3" V 2430 4450 50 0000 C CNN +F 1 "5000" V 2350 4450 50 0000 C CNN +F 2 "" H 2350 4450 60 0001 C CNN +F 3 "" H 2350 4450 60 0001 C CNN + 1 2350 4450 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R2 +U 1 1 50A9DF03 +P 2350 3850 +F 0 "R2" V 2430 3850 50 0000 C CNN +F 1 "5000" V 2350 3850 50 0000 C CNN +F 2 "" H 2350 3850 60 0001 C CNN +F 3 "" H 2350 3850 60 0001 C CNN + 1 2350 3850 + 1 0 0 -1 +$EndComp +$Comp +L R-RESCUE-lm555n R1 +U 1 1 50A9DEFE +P 2350 3250 +F 0 "R1" V 2430 3250 50 0000 C CNN +F 1 "5000" V 2350 3250 50 0000 C CNN +F 2 "" H 2350 3250 60 0001 C CNN +F 3 "" H 2350 3250 60 0001 C CNN + 1 2350 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_srlatch U8 +U 1 1 5E01E563 +P 8000 3350 +F 0 "U8" H 8000 3350 60 0000 C CNN +F 1 "d_srlatch" H 8050 3500 60 0000 C CNN +F 2 "" H 8000 3350 60 0000 C CNN +F 3 "" H 8000 3350 60 0000 C CNN + 1 8000 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 5E01F10F +P 7450 4400 +F 0 "U7" H 7450 4300 60 0000 C CNN +F 1 "d_inverter" H 7450 4550 60 0000 C CNN +F 2 "" H 7500 4350 60 0000 C CNN +F 3 "" H 7500 4350 60 0000 C CNN + 1 7450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 4400 8150 4400 +Wire Wire Line + 8000 4400 8000 4150 +$Comp +L adc_bridge_1 U5 +U 1 1 5E01F2C7 +P 6350 3400 +F 0 "U5" H 6350 3400 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3550 60 0000 C CNN +F 2 "" H 6350 3400 60 0000 C CNN +F 3 "" H 6350 3400 60 0000 C CNN + 1 6350 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3350 7200 3350 +Wire Wire Line + 4300 4650 5600 4650 +Wire Wire Line + 5600 4650 5600 3350 +Wire Wire Line + 5600 3350 5750 3350 +$Comp +L adc_bridge_1 U4 +U 1 1 5E01F3F2 +P 6350 3000 +F 0 "U4" H 6350 3000 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 3150 60 0000 C CNN +F 2 "" H 6350 3000 60 0000 C CNN +F 3 "" H 6350 3000 60 0000 C CNN + 1 6350 3000 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U6 +U 1 1 5E01F469 +P 6350 3850 +F 0 "U6" H 6350 3850 60 0000 C CNN +F 1 "adc_bridge_1" H 6350 4000 60 0000 C CNN +F 2 "" H 6350 3850 60 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 3800 7200 3800 +Wire Wire Line + 7200 2950 6900 2950 +$Comp +L limit U3 +U 1 1 5E01F5DC +P 4900 2950 +F 0 "U3" H 4950 2900 60 0000 C CNN +F 1 "limit" H 4950 3000 60 0000 C CNN +F 2 "" H 4900 3000 60 0000 C CNN +F 3 "" H 4900 3000 60 0000 C CNN + 1 4900 2950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5500 2950 5750 2950 +Wire Wire Line + 4200 3250 4200 2950 +Wire Wire Line + 4200 2950 4500 2950 +$Comp +L limit U2 +U 1 1 5E01F79D +P 4800 3800 +F 0 "U2" H 4850 3750 60 0000 C CNN +F 1 "limit" H 4850 3850 60 0000 C CNN +F 2 "" H 4800 3850 60 0000 C CNN +F 3 "" H 4800 3850 60 0000 C CNN + 1 4800 3800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5400 3800 5750 3800 +Wire Wire Line + 4200 3550 4200 3800 +Wire Wire Line + 4200 3800 4400 3800 +Wire Wire Line + 7050 3350 7050 4400 +Wire Wire Line + 7050 4400 7150 4400 +Connection ~ 7050 3350 +Wire Wire Line + 8000 2600 8150 2600 +Wire Wire Line + 8150 2600 8150 4400 +Connection ~ 8000 4400 +$Comp +L dac_bridge_1 U9 +U 1 1 5E01FCD2 +P 9550 3000 +F 0 "U9" H 9550 3000 60 0000 C CNN +F 1 "dac_bridge_1" H 9550 3150 60 0000 C CNN +F 2 "" H 9550 3000 60 0000 C CNN +F 3 "" H 9550 3000 60 0000 C CNN + 1 9550 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 2950 8950 2950 +$Comp +L dac_bridge_1 U10 +U 1 1 5E01FE8E +P 9600 3850 +F 0 "U10" H 9600 3850 60 0000 C CNN +F 1 "dac_bridge_1" H 9600 4000 60 0000 C CNN +F 2 "" H 9600 3850 60 0000 C CNN +F 3 "" H 9600 3850 60 0000 C CNN + 1 9600 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 3800 8800 3800 +Wire Wire Line + 9100 4000 9100 4250 +Wire Wire Line + 9100 4000 10300 4000 +Wire Wire Line + 10300 4000 10300 3800 +Wire Wire Line + 10300 3800 10150 3800 +$Comp +L eSim_NPN Q1 +U 1 1 5E01E782 +P 9000 4600 +F 0 "Q1" H 8900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 8950 4750 50 0000 R CNN +F 2 "" H 9200 4700 29 0000 C CNN +F 3 "" H 9000 4600 60 0000 C CNN + 1 9000 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 4600 8500 4600 +Wire Wire Line + 2250 4900 9100 4900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sub b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sub new file mode 100755 index 00000000..b524f5c6 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n.sub @@ -0,0 +1,39 @@ +* Subcircuit lm555n +.subckt lm555n 22 14 7 6 15 16 3 13 +.include npn_1.lib +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +* Inverter d_inverter +* SR Latch d_srlatch +e2 18 0 23 14 10000 +* Limiter limit8 +* Digital to Analog converter dac8 +* Analog to Digital converter adc8 +r8 9 2 1500 +q1 3 2 22 npn_1 +r7 18 20 25 +r6 17 19 25 +e1 17 0 16 15 10000 +r4 16 15 2e6 +r5 23 14 2e6 +r3 23 22 5000 +r2 15 23 5000 +r1 13 15 5000 +a1 5 21 u5 +.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) +a2 1 4 5 21 21 8 10 u6 +.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 ++sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 ++sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) +a3 19 11 u4 +a4 20 12 u4 +.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) +a5 [8] [7] u3 +a6 [10] [9] u3 +.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) +a7 [11] [4] u2 +a8 [12] [1] u2 +a9 [6] [5] u2 +.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) +*control statements + +.ends lm555n diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/lm555n_Previous_Values.xml b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n_Previous_Values.xml new file mode 100755 index 00000000..58d33ec5 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/lm555n_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u5 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u5><u6 name="type">d_srlatch<field4 name="Enter IC (default=0)" /><field5 name="Enter value for SR Load (default=1.0e-12)" /><field6 name="Enter Set Delay (default=1.0e-9)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter SR Delay (default=1.0e-9)" /><field9 name="Enter Enable Delay (default=1.0e-9)" /><field10 name="Enter Reset Delay (default=1.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter value for Reset Load (default=1.0e-12)" /><field14 name="Enter value for Enable Load (default=1.0e-12)" /></u6></model><devicemodel><q1><field /></q1></devicemodel><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">false</field2><field3 name="Oct">true</field3><field4 name="Start Frequency">kjadsfh</field4><field5 name="Stop Frequency">jhdsakj</field5><field6 name="No. of points">897897</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/Clock_pulse_generator/npn_1.lib b/library/SubcircuitLibrary/Clock_pulse_generator/npn_1.lib new file mode 100755 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/Clock_pulse_generator/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib index cc4c57db..ce0c8f05 100644 --- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib +++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib @@ -1,6 +1,45 @@ EESchema-LIBRARY Version 2.3 #encoding utf-8 # +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# # 2BITMUL # DEF 2BITMUL X 0 40 Y Y 1 F N |