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| author | rahulp13 | 2022-09-24 01:50:20 +0530 |
|---|---|---|
| committer | rahulp13 | 2022-09-24 01:50:20 +0530 |
| commit | f633fa2bc5625011b4b76d941fa8a95b4681cdb9 (patch) | |
| tree | 73434f9077f4a4e40e88c531ddd9542cd2c4ea4f | |
| parent | dade73ab5ec12358db92661cbde483fba906ea65 (diff) | |
| download | eSim-f633fa2bc5625011b4b76d941fa8a95b4681cdb9.tar.gz eSim-f633fa2bc5625011b4b76d941fa8a95b4681cdb9.tar.bz2 eSim-f633fa2bc5625011b4b76d941fa8a95b4681cdb9.zip | |
Added chapters for SKY130 and NgVeri
| -rw-r--r-- | NgVeri/MakerchipNgVeriicon.png | bin | 0 -> 441192 bytes | |||
| -rw-r--r-- | NgVeri/acceptTOS.png | bin | 0 -> 95434 bytes | |||
| -rw-r--r-- | NgVeri/addingvfile.png | bin | 0 -> 299064 bytes | |||
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| -rw-r--r-- | NgVeri/choosemodel.png | bin | 0 -> 238624 bytes | |||
| -rw-r--r-- | NgVeri/cirout1.png | bin | 0 -> 607459 bytes | |||
| -rw-r--r-- | NgVeri/cirout2.png | bin | 0 -> 455874 bytes | |||
| -rw-r--r-- | NgVeri/compile1.png | bin | 0 -> 177218 bytes | |||
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| -rw-r--r-- | NgVeri/defaultworkspace.png | bin | 0 -> 350486 bytes | |||
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| -rw-r--r-- | NgVeri/output1.png | bin | 0 -> 162891 bytes | |||
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| -rw-r--r-- | NgVeri/readwritepermission.png | bin | 0 -> 209542 bytes | |||
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| -rw-r--r-- | NgVeri/removereg.png | bin | 0 -> 192000 bytes | |||
| -rw-r--r-- | NgVeri/runverilator.png | bin | 0 -> 579896 bytes | |||
| -rw-r--r-- | NgVeri/savingvfile.png | bin | 0 -> 205553 bytes | |||
| -rw-r--r-- | NgVeri/schematicwithblockdescription.png | bin | 0 -> 226344 bytes | |||
| -rw-r--r-- | NgVeri/sourcev1.png | bin | 0 -> 153144 bytes | |||
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| -rw-r--r-- | NgVeri/svfile.png | bin | 0 -> 311795 bytes | |||
| -rw-r--r-- | NgVeri/verilogcode.png | bin | 0 -> 130074 bytes | |||
| -rw-r--r-- | SKY130/DeviceModelTab.PNG | bin | 0 -> 245993 bytes | |||
| -rw-r--r-- | SKY130/SKY130inverterSchematic.PNG | bin | 0 -> 103796 bytes | |||
| -rw-r--r-- | SKY130/SKY130libraries.PNG | bin | 0 -> 30558 bytes | |||
| -rw-r--r-- | SKY130/SKY130mode.PNG | bin | 0 -> 25419 bytes | |||
| -rw-r--r-- | SKY130/SKY130subcktlibraries.PNG | bin | 0 -> 31633 bytes | |||
| -rw-r--r-- | SKY130/Simulation.PNG | bin | 0 -> 42850 bytes | |||
| -rw-r--r-- | SKY130/Subcircuits.PNG | bin | 0 -> 34024 bytes | |||
| -rw-r--r-- | SKY130/SubcircuitsPath.PNG | bin | 0 -> 74392 bytes | |||
| -rw-r--r-- | SKY130/Subcircuitsadded.PNG | bin | 0 -> 48171 bytes | |||
| -rw-r--r-- | SKY130/netlist.PNG | bin | 0 -> 111821 bytes | |||
| -rw-r--r-- | chap_10.tex | 295 | ||||
| -rw-r--r-- | chap_11.tex | 914 | ||||
| -rw-r--r-- | chap_12.tex | 452 | ||||
| -rw-r--r-- | chap_13.tex | 692 | ||||
| -rw-r--r-- | chap_14.tex | 416 | ||||
| -rw-r--r-- | chap_9.tex | 266 |
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-\section {Introduction} -OpenModelica (OM) is an open source modeling and simulation tool based on -Modelica language. Modelica is an object oriented language. As a result, it has all the -features of an object oriented language such as inheritance. Models or circuits are -defined in the form of classes, with in which there are components, functions, -connection and placement information. The OM suite has the following major tools. - -\subsection {OMEdit} -An IDE for modeling and simulation. It supports a lot of electrical components. It -has a good graphical interface to drag and drop components and create the circuit. -One can only do transient simulation using this interface. An attractive feature of -OMEdit is the plotting interface. All the parameters in the circuit like voltages and currents through each component, -parameters like frequency, delay etc. will be displayed as -a list, after simulation. The user can choose the variables to be plotted in an -interactive manner from this list. On choosing the variable to plot, it will be plotted -on the plot window. One can also create multiple plot windows. - -\subsection {OMOptim} -An IDE for optimisation. It lists all the variables in the given model. One can choose -the variables to be optimised from the list. Multiple models can be loaded for a given -optimisation problem. One can do multi objective optimisations as well. It supports -various optimisation algorithms such as Particle Swarm Optimisation (PSO) and -Simulated Annealing (SA). The results are displayed graphically. - -\section {OpenModelica in eSim} -The above two functionalities can be accessed through the {\tt Modelica Converter} and {\tt OM Optimisation} tools on the eSim left toolbar. The two examples given below illustrates how to use OpenModelica in eSim. - -\subsubsection {Low Pass Filter circuit} -Let us now see how to simulate a low pass filter in OpenModelica. -\begin{enumerate} -\item Open the schematic and create the circuit as shown in \figref{lowpass}. -\begin{figure}[h] -\centering -\includegraphics[width=\lgfig]{list_of_figures/1.png} -\caption{Circuit schematic: Low pass filter} -\label{lowpass} -\end{figure} -\item Create the KiCad netlist. Now the analysis and analysis parameters are given as shown in \figref{lowpass-analysis}. +NGHDL feature facilitates creation of user-defined models for mixed-signal circuit simulation in eSim. By interfacing GHDL and Ngspice, we achieve mixed-signal simulation. Digital models are simulated using GHDL and XSPICE engine of Ngspice. \\ -\begin{figure}[h] -\centering -\includegraphics[width=\lgfig]{list_of_figures/2.png} -\caption{Analysis parameters: Low pass filter} -\label{lowpass-analysis} -\end{figure} -\item The source details are given as in \figref{lowpass-source}. The generated KiCad netlist is then converted to ngspice compatible netlist. +%To access NGHDL click on the NGHDL button on the left pane of window as shown in figure \figref{screen3}: +%\pagebreak -\begin{figure}[h] -\centering -\includegraphics[width=\lgfig]{list_of_figures/3.png} -\caption{Source details: Low pass filter} -\label{lowpass-source} -\end{figure} +\section{Introduction} -\item Simulate the ngspice netlist. The simulation curves are shown in \figref{lowpass-simulation}. +Ngspice supports mixed-signal simulation, i.e. it can simulate both digital and analog component. It defines a \texttt{model} which has the functionality of the circuit component, which can be used in the netlist. +For example you can create an \texttt{adder} model in Ngspice and use it in any circuit netlist of Ngspice. \\ -\begin{figure}[h] -\centering -\includegraphics[width=\lgfig]{list_of_figures/4.png} -\caption{Simulation: Low pass filter} -\label{lowpass-simulation} -\end{figure} +However, it is not feasible to define complex digital models without a complete understanding of Ngspice and XSPICE architectures and is a time-consuming process. Also, most of the users are familiar with GHDL and can write the models using VHDL code with ease. +Hence, NGHDL provides an interface to write VHDL code for a digital model and install it as model in Ngspice. So whenever Ngspice looks for that model, it will actually interface with VHDL code to get the result. \\ -\item Now to use OpenModelica, click on {\tt Modelica Converter} in the bottom left of eSim left toolbar.{\textit Make sure you have OpenModelica installed in the system}. This converter converts the spice netlist to Modelica format. Click on the LPF in the left that is appended in OpenModelica main window. Make sure you are in text view to see the Modelica code as shown in \figref{om-convert} Figure shows that LPF circuit is being used as a model, the initialisation of sources and components are in the beginning followed by the connection information. n3, n0,n2 are the nodes. - -\begin{figure}[h] +\begin{figure}[!htp] \centering -\includegraphics[width=\lgfig]{list_of_figures/5.png} -\caption{OpenModelica: Text view} -\label{om-convert} +\includegraphics[width = 12cm, height = 6cm]{./NGHDL/NGHDL_Overview.png} +\caption{Overview of NGHDL} +\label{overview} \end{figure} +%description of Overview: +\figref{overview} shows the overview of NGHDL indicating its architecture at the abstract level. The values for the digital models present in the netlist are fetched from the GHDL side of the interface whereas the values of the analog part are fetched from Ngspice's spice3f5 engine. Digital and Analog components in \figref{overview} are connected to each other with the help of the hybrid ADC and DAC models provided by Ngspice. This helps in the signal level switching when simulation is performed. As analog signals are in continuous time domain and Digital signals are in discrete time domain, hybrid components help bridge the gap. More information on the parameters of ADC and DAC present in Appendix : D. -Default Modelica libary is used for electrical sources and components. This has to imported so that it can be used in the current circuit. This is available in the left side of main window. - -\item Click on Simulation Setup on the toolbar at the top. A window opens as shown in \figref{om-simsetup}. Give start and stop time. Click {\tt OK}. +\pagebreak -\begin{figure}[h] -\centering -\includegraphics[width=\lgfig]{list_of_figures/6.png} -\caption{OpenModelica: Simulation setup} -\label{om-simsetup} -\end{figure} +\section{Digital Model creation using NGHDL} -\item A plotting window opens. Click on the node at the right to display the waveform. The window is shown in \figref{om-simulation}. +%Description of User Flow of NGHDL -\begin{figure}[h] +\begin{figure}[!htp] \centering -\includegraphics[width=\lgfig]{list_of_figures/7.png} -\caption{OpenModelica: Simulation} -\label{om-simulation} +\includegraphics[width = 12cm, height = 8cm]{./NGHDL/NGHDL_Flow.png} +\caption{User flow for NGHDL} +\label{user_flow} \end{figure} -\end{enumerate} - -\subsection {OM Optimisation} - -Now let us explore how to use OpenModelica for optimisation through an example. Find the value of resistance R2 that maximises the power dissipated through it for the circuit in \figref{optim-circuit}. This is an illustration of the Maximum Power Transfer Theorem. The power is maximum when R2 = R1, i.e., when R2 = 100. So maximum power would be Pmax = 0.0625. Let us now see the steps to be followed find the value of R2 using eSim. - -\begin{figure}[h] -\centering -\includegraphics[width=\lgfig]{list_of_figures/8.png} -\caption{Circuit schematic for optimisation} -\label{optim-circuit} -\end{figure} +\noindent \textbf{The steps to create digital models are given below}: \begin{enumerate} -\item Follow all the steps as above and generate the Modelica model using the Ngspice to Modelica converter. - -\item The objective function is $Power = i^2 \times R2$ . -To define the objective function, the line $power := i^2 \times R1+ i^2 \times R2$ -is added under the keyword algorithm, in the Modelica model file. - -\item Select {\tt OMOptim} from eSim left toolbar, in the displayed window click on {\tt New Project}. Then save the project. It is stored with an extension {\tt .min}. Now select {\tt Models} and then {\tt Load Modelica Library}. Now select {\tt Load mo file} under {\tt Models}. It will be added on the left. - -\item Click {\tt Problems} and then {\tt Optimisation}. Select the model to be optimised. \textit {Note that for optimising, that model has to be loaded in OpenModelica as stated before}. Clicking -blue turnover icon will display all the variables used in the model. Add details like optimsation variables and objective. - -The OMOptim project for this problem is given in \figref{om-project}. Power is the objective function that has to be maximized. {\tt r2.R} is the variable that will be varied. {\tt r2.R} is limited between 0 and 1000. - -\begin{figure}[h] -\centering -\includegraphics[width=\hgfig]{list_of_figures/9.png} -\caption{OMOptim project} -\label{om-project} -\end{figure} - -\item Click on Parameters tab to select the type of algorithm and its parameters. In this example, the optimisation algorithm used is PSO (Particle Swarm Optimisation). The various parameter values given are as follows: population size as 50, Inertia factor as 1, Learning factor: alpha and beta as 2, Population saving frequency was 1. Iteration limit is also specified. Select the .mo file to be simulated from {\tt Files} tab. Click on {\tt Launch}. The results of optimisation for various values of Iteration Limit are given in \figref {table}. - -\begin{figure}[h] -\centering -\includegraphics[width=\lgfig]{list_of_figures/10.png} -\caption{Optimisation values for various Iteration Limit } -\label{table} -\end{figure} +\item Click on NGHDL button on left side pane of main window, the Ngspice Digital Model Creator window will appear as shown in \figref{screen3} + \begin{figure}[!htp] + \centering + \includegraphics[height=10cm, width =\lgfig]{./NGHDL/screen3.png} + \caption{NGHDL interface} + \label{screen3} + \end{figure} + + +\item Now browse and locate the VHDL file to upload. Select the VHDL file and click on the Upload button. This process will create Ngspice model and corresponding component drawing inside the KiCad library (eSim\_Nghdl.lib) of the VHDL block to be used in mixed-signal simulations. An acknowledgement message will appear upon sucessful processing of the VHDL code as shown in \figref{upload}. \\ + + \begin{figure}[!htp] + \centering + \includegraphics[width =\smfig]{./NGHDL/screen4.png} + \caption{Uploading of digital model} + \label{upload} + \end{figure} + +Note : \texttt{"Add files"} option allow you to use a smaller entity / subpart / submodule to support the main VHDL file. That is, a digital model will be generated corresponding to that file that has been browsed. The file that has been \texttt{"added"} to Nghdl upload window will only be placed along with the model under model’s DUTghdl folder to support the model. + +Hence, \texttt{"browsing"} one file and \texttt{"adding"} several files won’t create that many number of models, but only one model will be created corresponding to the browsed file. +\end{enumerate} -\item Depending on the type of algorithm, the time for optimisation varies. Optimised result is graphically displayed as shown in \figref {om-optimised}. +\section{Schematic Creation} +Steps for schematic creation are as follows: +\begin{enumerate} +\item Click on New Project icon to create a new project as shown in \figref{screen1}, be careful of the naming conventions. +%To access nghdl click on the NGHDL button on the left pane of window as shown in figure \figref{screen3}: -\begin{figure} +\begin{figure}[!htp] \centering -\includegraphics[width=\hgfig]{list_of_figures/11.png} -\caption{Optimised value of resistance for maximum power } -\label{om-optimised} +\includegraphics[width = 13cm, height = 7cm]{./NGHDL/screen1.png} +\caption{Creation of a new project} +\label{screen1} \end{figure} -\end{enumerate} - +\item After successful upload of the model using the VHDL code, you can create the schematic of your design by clicking on \texttt{Open Schematic} button on the left pane of the eSim window. Then go to \texttt{Preferences} option on top of the schematic editor window and click on \texttt{Component Libraries} to add the library eSim\_Nghdl.lib in KiCad. Following window will appear as shown in \figref{screen6}, where you will have to click on \textit {Add} button and select the \texttt{eSim\_Nghdl} library. Refer \figref{screen6} and \figref{screen7}. %%last sentence may not be required + + \begin{figure}[!htp] + \centering + \includegraphics[width =\smfig]{./NGHDL/screen6.png} + \caption{Adding the digital model library in KiCad} + \label{screen6} + \end{figure} + + + \begin{figure}[!htp] + \centering + \includegraphics[width =\smfig]{./NGHDL/screen7.png} + \caption{Selection of library} %%this may not be required either + \label{screen7} + \end{figure} + + + + \pagebreak + \item Next step is to locate the component in \texttt{eSim\_Nghdl} library as shown in \figref{screen9} and place it on the schematic editor as shown in \figref{screen10}. + \begin{figure}[!htp] + \centering + \includegraphics[width =\smfig]{./NGHDL/screen9.png} %%Change this image + \caption{Locating the component in library} + \label{screen9} + \end{figure} + + + \begin{figure}[!htp] + \centering + \includegraphics[width =\smfig]{./NGHDL/screen10.png} + \caption{Placement of component on editor} + \label{screen10} + \end{figure} +\pagebreak + +\item Now create the schematic as shown in \figref{screen14}, annotate, perform ERC, create the netlist and save the schematic by following the steps given in \chapref{chap5}. +\begin{figure}[!htp] + \centering + \includegraphics[width =\hgfig]{./NGHDL/screen14.png} + \caption{Example of an AND gate characteristics circuit} + \label{screen14} + \end{figure} + +\item After creating the schematic, click on \texttt{KiCad-to-Ngspice converter} and select the type of analysis as transient as shown in \figref{screen15} and set the start, step and stop time as shown in \figref{screen16} + \begin{figure}[!htp] + \centering + \includegraphics[width =\hgfig]{./NGHDL/screen15.png} + \caption{Analysis Part I} + \label{screen15} + \end{figure} + \begin{figure}[!htp] + \centering + \includegraphics[width =\hgfig]{./NGHDL/screen16.png} + \caption{Analysis Part II} + \label{screen16} + \end{figure} +\pagebreak + +\item Now click on \texttt{Source Details} and enter the values for Source v1 and source v2 as shown in figure \figref{val1} and \figref{val2} +\begin{figure}[!htp] + \centering + \includegraphics[width =\hgfig]{./NGHDL/val1.png} + \caption{Value of Source v1} + \label{val1} + \end{figure} + \begin{figure}[!htp] + \centering + \includegraphics[width =\hgfig]{./NGHDL/val2.png} + \caption{Value of Source v2} + \label{val2} + \end{figure} + +\item Now select the option \texttt{Ngspice Model}, window as shown in \figref{screen17} will appear. The values of the parameters listed can be changed per user's requirement. If you have used any semicnductor devices and Subcircuits in your design, then please specify the Spice models and subcircuits in the \texttt{Device Modeling} and \texttt{Subcircuits} tabs of the \texttt{KiCad-to-Ngspice converter} window. After that click on \texttt{Convert} button. This step will create the simulation compatible netlist. + \begin{figure}[!htp] + \centering + \includegraphics[width =\hgfig]{./NGHDL/screen17.png} %Change the figure + \caption{Model Parameters} + \label{screen17} + \end{figure} +\item Now click on \texttt{Simulation} button, it will display the following windows as shown in \figref{screen19}. This is the Ngspice terminal and Python plot window. +\begin{figure}[!htp] + \centering + \includegraphics[width =\hgfig]{./NGHDL/screen19.png} + \caption{Simulation window} + \label{screen19} + \end{figure} +\pagebreak +\item Now select the required nodes and click on \texttt {Plot} button. You can see the plots of input source v1, input source v2 and output as shown in \figref{plotv1}, \figref{plotv2}, and \figref{plotout} respectively. +\begin{figure}[!htp] + \centering + \includegraphics[width =\lgfig]{./NGHDL/plotv1.png} + \caption{Plot of Source V1} + \label{plotv1} + \end{figure} +\begin{figure}[!htp] + \centering + \includegraphics[width =\lgfig]{./NGHDL/plotv2.png} + \caption{Plot of source V2} + \label{plotv2} + \end{figure} +\begin{figure}[!htp] + \centering + \includegraphics[width =\lgfig]{./NGHDL/plotout.png} + \caption{Plot of output} + \label{plotout} + \end{figure} + + \pagebreak + +\end{enumerate}
\ No newline at end of file diff --git a/chap_11.tex b/chap_11.tex index 63e1320a..25436e56 100644 --- a/chap_11.tex +++ b/chap_11.tex @@ -1,692 +1,548 @@ -\chapter{Solved Examples} +\chapter{Makerchip-NgVeri: Mixed Signal Simulation} +\label{chap10} \thispagestyle{empty} -\label{chap11} -\section{Solved Examples} +NgVeri is a simulator in eSim which facilitates mixed-signal circuit simulation. Digital models are simulated using Verilator and analog models are simulated using XSPICE engine of Ngspice. NgVeri links Ngspice and Verilator to support mixed-mode simulations in eSim as shown in \figref{ngveriblock}. -%---------------RC circuit------------------- -\subsection{Basic RC Circuit} -\subsubsection{Problem Statement:} Plot the Input and Output Waveform of an RC circuit whose input voltage (Vs) is 50Hz, 3V peak to peak. The values of Resistor (R) and Capacitor(C) are $1k$ and $1uf$ respectively. -\subsubsection{Solution:} -\begin{itemize} -\item Creating a Project: -The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given in the pop up window as shown in \figref{rc1}. -\begin{figure}[!htp] - \centering - \includegraphics[width=\hgfig]{figures/rc1.png} - %\includegraphics[width=\linewidth]{figures/rc1.png} - \caption{Creating New Project} - \label{rc1} + +\begin{figure}[H] +\centering +\includegraphics[ height = 2cm]{./NgVeri/ngveri_block.png} +\caption{NgVeri Block} +\label{ngveriblock} \end{figure} -\item Creating the Schematic: -To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema. + +\noindent {Makerchip is a web browser IDE to develop/simulate/debug Verilog, SystemVerilog and TL-Verilog Code developed by Redwood EDA, LLC. It provides seamless design experience by integrating code, debug window, block diagrams, waveforms together in one screen. Makerchip is integrated with NgVeri in the latest version of eSim (eSim 2.2). Makerchip provides the digital side of eSim's mixed-signal environment.} -\begin{figure}[!htp] - \centering - \includegraphics[width=\smfigp]{figures/rc2.png} - %\includegraphics[width=\linewidth]{figures/rc2.png} - \caption{Open Schematic Editor} - \label{rc2} + +\section{Familiarizing the Makerchip-NgVeri interface in eSim} + +In this section, we will explain Makerchip-NgVeri interface in eSim and the various menus and tabs. + +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height = 7cm]{./NgVeri/MakerchipNgVeriicon.png} +\caption{Makerchip NgVeri Tab} +\label{makerchipngveri} \end{figure} -To create a schematic in KiCad, we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library. +%description of makerchip: +\figref{makerchipngveri} shows the Makerchip-NgVeri tab (newly added in eSim 2.2). In order to open this tab click on the Makerchip button on LHS vertical bar. Makerchip interface opens up as shown in the \figref{makerchipinterface}. -\begin{figure}[!htp] - \centering - \includegraphics[width=\tnfig]{figures/rc_component.png} - %\includegraphics[width=\linewidth]{figures/rc_component.png} - \caption{Place Component Icon} - \label{rc_component} +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height = 7cm]{./NgVeri/makerchipinterface.png} +\caption{Makerchip Interface} +\label{makerchipinterface} \end{figure} \pagebreak -After all the required components of the simple RC circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire} +\section{Makerchip Interface} -\begin{figure}[!htp] - \centering - \includegraphics[width=\tnfig]{figures/rc_wire.png} - %\includegraphics[width=\linewidth]{figures/rc_wire.png} - \caption{Place Wire Icon} - \label{rc_wire} -\end{figure} - -Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. +%Description of Makerchip interface +Makerchip interface working space is shown in the \figref{makerchipinterface}. Various buttons of Makerchip interface are shown in the \figref{makerchipbuttons} -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/erc1.png} - %\includegraphics[width=\linewidth]{figures/erc1.png} - \caption{Electric Rules Check Icon} - \label{erc1} +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height = 7cm]{./NgVeri/makerchipbuttons.png} +\caption{Makerchip buttons} +\label{makerchipbuttons} \end{figure} -\figref{rc_complete1} shows the RC circuit after connecting the components by wire. +\noindent \textbf{The components of the Makerchip tab are}: -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/rc_complete1.png} - \caption{RC circuit} - \label{rc_complete1} -\end{figure} +\begin{enumerate} +\item Add Top Level Verilog file: This button helps the user to load the verilog file. -\pagebreak +\item Refresh: It enables refreshing of the file locally edited. -After clicking the {\tt ERC} icon a window opens up. Click the {\tt Run} button to run rules check. The errors are listed in as shown in \figref{erc2}. This error is handled by adding {\tt Power Flag} as shown in \figref{rc_pwr}. +\item Save: It saves the edited file. -\begin{figure}[!htp] - \centering - \subfloat[ERC Run]{ - \includegraphics[width=\smfig]{figures/erc2.png} - \label{erc2}} \hfill - \subfloat[Power Flag]{ - \includegraphics[width= 5cm, height=5cm]{figures/rc_pwr.png} - \label{rc_pwr}} - \caption{ERC check and POWER FLAG} -\end{figure} +\item Edit in Makerchip: It opens the Makerchip App and the user can edit and simulate the verilog file in Makerchip IDE. -After adding the {\tt Power Flag} the completed RC circuit is shown in \figref{rc_schematic} and the netlist is generated as shown in \figref{rc_netlist}. +\item .tlv Code Editor: After loading the top level verilog file, the verilog code appears in this editor. The user can then edit the verilog code within this editor workspace. +\item Path to .tlv file: The path or the directory where the verilog file exists locally appears here after uploading the verilog file. -\begin{figure}[!htp] - \centering - \subfloat[Schematic of RC circuit]{ - \includegraphics[width=\smfig]{figures/rc_schematic.png} - \label{rc_schematic}} \hfill - \subfloat[Generating KiCad Netlist of RC circuit]{ - \includegraphics[width=\smfig]{figures/rc_netlistgeneration.png} - \label{rc_netlist}} - \caption{RC Schematic and Netlist Generation} -\end{figure} +\item Accept Makerchip TOS: This button when pressed accepts the Terms of Service of Makerchip. After accepting this, the button vanishes in the rerun of eSim. + +\end{enumerate} \pagebreak -\item Convert KiCad to Ngspice: -To convert KiCad netlist of RC circuit to NgSpice compatible netlist click on KiCad to Ngspice icon as shown in \figref{rcki2ng}. + +\section{NgVeri Interface} + +%Description of Makerchip interface +NgVeri interface is shown in the \figref{ngveriinterface}. Various components of NgVeri interface are shown in the \figref{ngveributtons} \begin{figure}[!htp] \centering -\includegraphics[width=\tnfig]{figures/rc_ki2ng.png} -\caption{Convert KiCad to Ngspice Icon} -\label{rcki2ng} +\includegraphics[width = 13cm, height = 7cm]{./NgVeri/ngveriinterface.png} +\caption{NgVeri Interface} +\label{ngveriinterface} \end{figure} -Now you can enter the type of analysis and source details as shown in \figref{rc_analysistab} and \figref{rc_sourcedetailstab} respectively. -\begin{figure}[!htp] - \centering - \subfloat[RC Analysis]{ - \includegraphics[width=\smfig]{figures/rc_analysistab.png} - \label{rc_analysistab}} \hfill - \subfloat[RC Source Details]{ - \includegraphics[width=\smfig]{figures/rc_sourcedetailstab.png} - \label{rc_sourcedetailstab}} - \caption{RC Analysis and Source Detail} -\end{figure} -The other tab will be empty as RC circuit do not use any Ngspice model, device library and subcircuit. +\noindent \textbf{The important components of NgVeri are:} -After entering the value, press the convert button. It will convert the netlist into Ngspice compatible netlist. +\begin{enumerate} -\pagebreak +\item Terminal : This is the terminal where the user can view all the commands and processes running. -\item Simulation: -To run Ngspice simulation click the simulation icon in the tool bar as shown in the \figref{rcplot}. -\begin{figure}[!htp] +\item Run Verilog to Ngspice Converter: This button when pressed run NgVeri and builds the model for Ngspice. + +\item Add Other file: Using this option, the user can add all the dependency files which are needed by the Top level verilog file in Makerchip. + +\item Add Folder: Using this option, the user can add all the dependency folders which are needed by the Top level verilog file. + +\item Clear terminal: This button when pressed erases the content of the terminal i.e it clears the terminal. + +\item Edit modlst: Using this option, the user can see the existing models present and the user can remove the models from the Model list. + +\begin{figure}[H] \centering -\includegraphics[width=\tnfig]{figures/rc_plot.png} -\caption{Simulation Icon} -\label{rcplot} +\includegraphics[width = 15cm, height = 8cm]{./NgVeri/ngveributtons.png} +\caption{NgVeri buttons} +\label{ngveributtons} \end{figure} -In eSim, there are two types of plot. First is normal Ngspice plot and second is interactive python plot as shown in \figref{rc_ngspiceplot} and \figref{rc_pythonplot} respectively. +\item Edit lint off: When this button is pressed, the user can see all the lint-off commands list and the user can remove the lint-off from the list. -\begin{figure}[!htp] - \centering - \subfloat[Ngspice Plot of RC]{ - \includegraphics[width=\lgfig]{figures/rc_ngspiceplot.png} - \label{rc_ngspiceplot}} \hfill - \subfloat[Python Plot of RC]{ - \includegraphics[width=\lgfig]{figures/rc_pythonplot.png} - \label{rc_pythonplot}} - \caption{Ngspice and Interactive Python Plotting} -\end{figure} +\item Add Lint off: The user can add lint-off command by using this button. This lint-off command is used if user gets a lint-off error in the terminal. -In the interactive python plot you can select any node or branch to plot voltage or current across it. Also it has the facility to plot basic functions across the node like addition, substraction, multiplication, division and v/s. +\end{enumerate} -\end{itemize} -%-----------------------Half Wave Rectifier--------------------------- -\pagebreak +\newpage -\subsection{Half Wave Rectifier} +\section{Counter example using Makerchip and NgVeri in eSim} -\subsubsection{Problem Statement:} Plot the Input and Output Waveform of Half Wave Rectifier circuit where the input voltage (Vs) is 50Hz, 2V peak to peak. The value for Resistor (R) is 1k. +%Description of Sample schematic creation +In this section, a digital 8 bit counter example using NgVeri and Makerchip tabs in eSim is discussed. Kindly note that steps shown over here are carried out with eSim 2.2 in Ubuntu version 20.04. Steps remain same for eSim in Windows version. -\subsubsection{Solution:} -The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given in the window shown in \figref{rc1}. -\begin{itemize} -\item Creating Schematic: -To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ +\subsection {Makerchip steps in eSim} -After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the -right toolbar which opens the component library.\\ +Steps for verilog code compilation and verification using Makerchip IDE are as follows: -After all the required components of the simple Half Wave rectifier circuits are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}\\ +\begin{enumerate} -Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. After completing all the above steps the final Half Wave Rectifier schematic will look like \figref{hwr_schematic}.\\ +\item Open eSim and select the default eSim workspace by clicking on \textbf{OK} as shown in \figref{workspaceeSim}. Its format is /home/$<$username$>$/eSim-Workspace. User-name can be user specific but be careful of the naming conventions(space is not allowed). If the user wants to select they can chose the same by using the \textbf{Browse} button in the dialog box. -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/hwr_schematic.png} - \caption{Schematic of Half Wave Rectifier circuit} - \label{hwr_schematic} +\begin{figure}[H] +\centering +\includegraphics[width = 9cm, height = 5cm]{./NgVeri/defaultworkspace.png} +\caption{eSim workspace} +\label{workspaceeSim} \end{figure} -\pagebreak +\item Open a blank Text Editor and write verilog code of 8 bit counter and save the file as either filename.v in the eSim-Workspace as shown in \figref{savingv}. +\item \textbf{Please Note}: The filename should be the same as top-level module name, otherwise eSim will throw an error as discussed in Common error sections.\\ +The file extensions allowed are: +\begin{itemize} + \item .v for Verilog + \item .sv for SystemVerilog + \item .tlv for Transaction-Level Verilog +\end{itemize} + +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height = 5cm]{./NgVeri/savingvfile.png} +\caption{Saving verilog file in eSim workspace} +\label{savingv} +\end{figure} -KiCad netlist is generated as shown in the \figref{hwr_netlistgeneration} \\ +\item The verilog code for 8 bit counter is written inside the Text Editor with .v file as extension saved in eSim workspace is shown in \figref{vcode} -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/hwr_netlistgeneration.png} - \caption{Half Wave Rectifier circuit Netlist Generation} - \label{hwr_netlistgeneration} +\begin{figure}[H] +\centering +\includegraphics[width = 11cm, height = 5cm]{./NgVeri/verilogcode.png} +\caption{8 bit Counter verilog code} +\label{vcode} \end{figure} -\item Convert KiCad to Ngspice: After creating KiCad netlist, click on the {\tt KiCad-Ngspice converter} button. This will open converter window where you can enter details of Analysis, Source values and Device library. +\item Click on Makerchip-NgVeri button on the left toolbar of eSim window which opens Makerchip interface in eSim as shown in \figref{addingv}. -\begin{figure}[!htp] - \centering - \subfloat[Half Wave Rectifier Analysis]{ - \includegraphics[width=\smfig]{figures/hwr_analysistab.png} - \label{hwr_analysistab}} \hfill - \subfloat[Half Wave Rectifier Source Details]{ - \includegraphics[width=\smfig]{figures/hwr_sourcedetailstab.png} - \label{hwr_sourcedetailstab}} \hfill - \subfloat[Half Wave Rectifier Device Modeling]{ - \includegraphics[width=\smfig]{figures/hwr_devicemodelingtab.png} - \label{hwr_devicemodelingtab}} - \caption{Analysis, Source and Device Tab} +\begin{figure}[H] +\centering +\includegraphics[width = 15cm, height =7cm]{./NgVeri/addingvfile.png} +\caption{Adding verilog file in Makerchip editor} +\label{addingv} \end{figure} -Under device library you can add the library for diode used in the circuit. If you do not add any library it will take default Ngspice model. +\item Click on the button shown in Step 2 as shown in \figref{addingv} to add the verilog file for 8 bit counter. The path to top level verilog file along with the verilog code get added in the Makerchip editor terminal shown in Step 3 of \figref{addingv} +\item User can refresh locally edited verilog file by clicking on the \textbf{Refresh} button as shown in Step 4 of \figref{addingv}. If the file is edited using some other editor and also loaded in Makerchip Tab at the same time, the \textbf{Refresh} button starts toggling. The user must click on the Refresh button to get the new version of the file in the editor. -\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. -\begin{figure}[!htp] - \centering - \subfloat[Ngspice Plot of Half Wave Rectifier]{ - \includegraphics[width=\lgfig]{figures/hwr_ngspiceplot.png} - \label{hwr_ngspiceplot}} \hfill - \subfloat[Python Plot of Half Wave Rectifier]{ - \includegraphics[width=\lgfig]{figures/hwr_pythonplot.png} - \label{hwr_pythonplot}} - \caption{Half Wave Rectifier Simulation Output} +\item User can save the verilog code edited in the Makerchip editor terminal by clicking on the \textbf{Save} button shown in Step 5 of \figref{addingv} + +\item For the first run, the user needs to accept the Term of Service by clicking on \textbf{Accept Makerchip TOS} as shown in \figref{TOS}. This button will disappear after rerun of eSim as shown in \figref{addingv}. + +\begin{figure}[H] +\centering +\includegraphics[width = 13cm, height = 4cm]{./NgVeri/acceptTOS.png} +\caption{Accepting Terms of Service of Makerchip} +\label{TOS} \end{figure} +\item Now click on \textbf{Edit in Makerchip} button to open and edit the verilog code in Makerchip IDE. A pop-up window will appear as shown in \figref{editinmakerchip}. By clicking on \textbf{Yes}, a top level verilog file i.e .tlv file will be created in the same directory of current verilog file and the Makerchip IDE will be run in a new web browser as shown in \figref{makerchipide}. By clicking on \textbf{No}, the current raw verilog file i.e .v file will open up in Makerchip IDE web browser. -\end{itemize} +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height = 6cm]{./NgVeri/editinmakerchip.png} +\caption{Opening Makerchip IDE} +\label{editinmakerchip} +\end{figure} -\pagebreak -%-------------- Precision rectifier-------------------------------------- - -%\pagebreak - -%\subsection{Precision Rectifier} -%\subsubsection{Problem Statement:} Plot the input and output waveform of the Precision Rectifier circuit where input voltage (Vs) is $50Hz$ , $3V$ peak to peak. - -%\subsubsection{Solution:} -%The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given as shown in the \figref{rc1}. - -%\begin{itemize} -%\item Creating Schematic: -%To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ -%After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library.\\ -%After all the required components of the precision rectifier circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}.\\ -%Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. -%The \figref{pr_schematic} shows the complete Precision Rectifier schematic after removing the errors. - -%\begin{figure}[!htp] -%\centering -%\includegraphics[width=\hgfig]{figures/pr_schematic.png} -%\caption{Schematic of Precision Rectifier circuit} -%\label{pr_schematic} -%\end{figure} - -%The KiCad netlist is generated as shown in \figref{pr_netlistgeneration}.\\ - -%\begin{figure}[!htp] -% \centering -% \includegraphics[width=\lgfig]{figures/pr_netlistgeneration.png} -% \caption{Precision Rectifier circuit Netlist Generation} -% \label{pr_netlistgeneration} -%\end{figure} - -%\pagebreak - -%\item Convert KiCad to Ngspice: After creating KiCad netlist, click on KiCad-Ngspice converter button.\\ - -% This will open converter window where you can enter details of Analysis, Source values, Device library and Subcircuit. - -%\begin{figure}[!htp] -% \centering -% \subfloat[Precision Rectifier Analysis]{ -% \includegraphics[width=\smfig]{figures/pr_analysistab.png} -% \label{pr_analysistab}} \hfill -% \subfloat[Precision Rectifier Source Details]{ -% \includegraphics[width=\smfig]{figures/pr_sourcedetailstab.png} -% \label{pr_sourcedetailstab}} \vfill -% \subfloat[Precision Rectifier Device Modeling]{ -% \includegraphics[width=\smfig]{figures/pr_devicemodelingtab.png} -% \label{pr_devicemodelingtab}}\hfill -% \subfloat[Precision Rectifier Subcircuit]{ -% \includegraphics[width=\smfig]{figures/pr_subcircuitstab.png} -% \label{pr_subcircuitstab}} -% \caption{Analysis, Source, Device library and Subcircuit tab} -%\end{figure} - -%Under device library you can add the library for the diode used in the circuit. If you do not add any library it will take default Ngspice -%model for diode.\\ - -%Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to add subcircuit it will throw an error. - - -%\pagebreak -%\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run the simulation by clicking the simulation button in the toolbar. -%\begin{figure}[!htp] -% \centering -% \subfloat[Ngspice Plot of Precision Rectifier]{ -% \includegraphics[width=\lgfig]{figures/pr_ngspiceplot.png} -% \label{pr_ngspiceplot}} \hfill -% \subfloat[Python Plot of Precision Rectifier]{ -% \includegraphics[width=\lgfig]{figures/pr_pythonplot.png} -% \label{pr_pythonplot}} -% \caption{Precision Rectifier Simulation Output} -%\end{figure} - -%\end{itemize} - -%-------------- Inverting Amplifier-------------------------------------- +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height = 6cm]{./NgVeri/makerchipIDE.png} +\caption{Makerchip IDE interface} +\label{makerchipide} +\end{figure} -\pagebreak -\subsection{Inverting Amplifier} -\subsubsection{Problem Statement:} -Plot the Input and Output Waveform of Inverting Amplifier circuit where the input voltage (Vs) is $50Hz$, $2V$ peak to peak and gain is 2. -\subsubsection{Solution:} +\item User can check for errors by clicking on \textbf{LOG} tab in Makerchip IDE interface as shown in the \figref{makerchipide}. Following window will appear as shown in \figref{makerchiperror}, where you can check the Verilator lint-off errors. -\begin{itemize} -\item Creating Schematic: -To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ -After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library.\\ -After all the required components of the inverting amplifier circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}.\\ -Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =7cm]{./NgVeri/makerchiperrors.png} +\caption{Verilator lintoff errors} +\label{makerchiperror} +\end{figure} -The \figref{ia_schematic} shows the complete Precision Rectifier schematic after removing the errors. +\item As shown in the \figref{makerchiperror}, verilator lint-off commands which caused error in the Log section needs to be removed from Line 3 in the editor window. Two such commands which needs to be removed are shown in the \figref{lintofferror}. -\begin{figure}[!htp] - \centering - \includegraphics[width=\hgfig]{figures/ia_schematic.png} - \caption{Schematic of Inverting Amplifier circuit} - \label{ia_schematic} +\begin{figure}[H] +\centering +\includegraphics[width = 12cm, height =4cm]{./NgVeri/lintofferror.png} +\caption{Removal of lintoff errors} +\label{lintofferror} \end{figure} -The KiCad netlist is generated as shown in \figref{ia_netlistgeneration}.\\ -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/ia_netlistgeneration.png} - \caption{Inverting Amplifier circuit Netlist Generation} - \label{ia_netlistgeneration} -\end{figure} - - -\item Convert KiCad to Ngspice: -After creating KiCad netlist, click on KiCad-Ngspice converter button.\\ - -This will open converter window where you can enter details of Analysis, Source values, Device library and Subcircuit. - -Subcircuit of Op-Amp is shown in \figref{ia_sub} - \begin{figure}[!htp] - \centering - \subfloat[Inverting Amplifier Analysis]{ - \includegraphics[width=\smfig]{figures/ia_analysistab.png} - \label{ia_analysistab}} \hfill - \subfloat[Inverting Amplifier Source Details]{ - \includegraphics[width=\smfig]{figures/ia_sourcedetailstab.png} - \label{ia_sourcedetailstab}} \vfill - \subfloat[Inverting Amplifier Subcircuit]{ - \includegraphics[width=\smfig]{figures/ia_subcircuitstab.png} - \label{ia_subcircuitstab}}\hfill - \subfloat[Sub-Circuit of Op-Amp]{ - \includegraphics[width=\lgfig]{figures/ia_sub.png} - \label{ia_sub}} - \caption{Analysis, Source, and Subcircuit tab} - \end{figure} +\item Next, click on the \textbf{Editor} tab in the editor as shown in \figref{compile1}, then click on \textbf{Compile/Sim} button to compile the verilog code. -\pagebreak -Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to add subcircuit, it will throw an error.\\ +\begin{figure}[H] +\centering +\includegraphics[width = 12cm, height =5cm]{./NgVeri/compile1.png} +\caption{Compiling after removing lintoff errors} +\label{compile1} +\end{figure} + +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =6cm]{./NgVeri/regerror.png} +\caption{ Unexpected reg error in the code} +\label{regerror} +\end{figure} +\item After compiling, \textbf{Unexpected reg error} remains in the Log section (Refer \figref{regerror}) which can be rectified by removing \textit{reg} from top level verilog code as shown in \figref{removereg}. By clicking \textbf{Yes} button in \figref{editinmakerchip}, a Top Level Verilog (TLV) code automatically gets added in the editor. Refer \figref{removereg}. The value of \textit{rst} value is by default as random value and it can be replaced if user wants to assign values. We have assigned \textit{rst} with \textit{reset} in this counter example. -\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. -\begin{figure} - \centering - \subfloat[Inverting Amplifier Ngspice Plot]{ - \includegraphics[width=\lgfig]{figures/ia_ngspiceplot.png} - \label{ia_ngspiceplot}}\vfill - \subfloat[Inverting Amplifier Python Plot]{ - \includegraphics[width=\lgfig]{figures/ia_pythonplot.png} - \label{ia_pythonplot}} - \caption{Inverting Amplifier Simulation Output} +\begin{figure}[H] +\centering +\includegraphics[width = 12cm, height =6cm]{./NgVeri/removereg.png} +\caption{Top level verilog code} +\label{removereg} \end{figure} +\item Now click on the \textbf{Editor} tab and then click on \textbf{Compile/Sim} button in the editor as shown in \figref{compile1}, it will display the following waveform window as shown in \figref{output1}. This means that the verilog code of 8 bit Counter is successfully compiled. Kindly, note that in \figref{output1}, inputs and output waveform are in the compressed form. +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =6cm]{./NgVeri/makerchipoutput1.png} +\caption{Output waveforms in compressed form of 8 bit Counter } +\label{output1} +\end{figure} -\end{itemize} +\item \figref{output2} shows the expanded view of inputs and output waveforms of 8 bit counter. The waveforms in \figref{output1} can be expanded by clicking on \textbf{Zoom In} button as shown in \figref{output2}. -%-------------------------Half Adder------------------------------------------ +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =6cm]{./NgVeri/makerchipoutput2.png} +\caption{Output waveforms in expanded form of 8 bit Counter } +\label{output2} +\end{figure} -\pagebreak +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =7cm]{./NgVeri/makerchipoutput3.png} +\caption{8 bit Counter counting from 0 to 255} +\label{output3} +\end{figure} -\subsection{Half Adder} +\item To view the output waveform forward in time, click on forward button as shown in \figref{output3}. It can be clearly seen, the 8 bit counter counts from to 0 to 255 in decimal (FF in hexadecimal) and it resets after counting up to 255. -\subsubsection{Problem Statement:} Plot the Input and Output Waveform of Half Adder circuit. +\item Next, close the Makerchip window. This completes the 8 bit counter verilog code compilation and verification process using Makerchip IDE. -\subsubsection{Solution:} +\end{enumerate} -\begin{itemize} +\subsection {Steps to run NgVeri in eSim} -\item Creating Schematic: To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ -After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library.\\ -After all the required components of the Half Adder circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}.\\ -Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. +Steps for schematic creation and simulation using NgVeri in eSim are as follows: -The \figref{ha_schematic} shows the complete Half Adder schematic after removing the errors. -\begin{figure}[!htp] - \centering - \includegraphics[width=\hgfig]{figures/ha_schematic.png} - \caption{Schematic of Half Adder circuit} - \label{ha_schematic} -\end{figure} +\begin{enumerate} +\item The verilog code named counter8bit.v is loaded in editor space of Makerchip tab as shown in \figref{addingv}. -The KiCad netlist is generated as shown in \figref{ha_netlistgeneration}.\\ -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/ha_netlistgeneration.png} - \caption{Half Adder circuit Netlist Generation} - \label{ha_netlistgeneration} -\end{figure} -\pagebreak +\item Click on \textbf{NgVeri} button and then click on \textbf{Run Verilog to Ngspice converter} button as shown in \figref{ngclick}. This step will convert 8 bit counter's verilog file to Ngspice model. The commands that run in the NgVeri terminal leads to creation of Ngspice(XSPICE) model of 8 bit counter are mentioned in following steps. -\item Convert KiCad to Ngspice: -After creating KiCad netlist click on KiCad-Ngspice converter button.\\ +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =6cm]{./NgVeri/ngvericlick.png} +\caption{NgVeri interface buttons} +\label{ngclick} +\end{figure} -This will open converter window where you can enter details of Analysis, Source values, Ngspice model and Subcircuit. +\item First command after clicking \textbf{Run Verilog to Ngspice Converter} button in NgVeri terminal is \textbf{RUN VERILATOR} highlighted as 1 in red color in \figref{ngvericommands}. -\begin{figure}[!htp] - \centering - \subfloat[Half Adder Analysis]{ - \includegraphics[width=\smfig]{figures/ha_analysistab.png} - \label{ha_analysistab}} \hfill - \subfloat[Half Adder Source Details]{ - \includegraphics[width=\smfig]{figures/ha_sourcedetailstab.png} - \label{ha_sourcedetailstab}} \vfill - \subfloat[Half Adder Ngspice Model]{ - \includegraphics[width=\smfig]{figures/ha_ngspicemodeltab.png} - \label{ha_ngspicemodeltab}} \hfill - \subfloat[Half Adder Subcircuit Model]{ - \includegraphics[width=\smfig]{figures/ha_subcircuitstab.png} - \label{ha_subcircuitstab}} - \caption{Analysis, Source, Ngspice Model and Subcircuit tab} -\end{figure} - -Subcircuit of Half Adder in \figref{ha_sub} -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/ha_sub.png} - \caption{Half Adder Subcircuit} - \label{ha_sub} + +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =10cm]{./NgVeri/runverilator.png} +\caption{Commands in NgVeri} +\label{ngvericommands} \end{figure} -\pagebreak +\item Verilator converts the verilog file into C++ objects. Next command is\textbf{ MAKE VERILATOR} for obtaining the C++ objects. Next is \textbf{MAKE COMMAND}, which links the verilator's C++ objects and Ngspice objects.\textbf{ MAKE INSTALL COMMAND} is the last command in the process before Ngspice model creation. + +\item When the \textbf{Model Created Successfully} message appears in the terminal as shown in green color in \figref{ngmodel}, it indicates that the Ngspice model is created. -\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. - \begin{figure}[!htp] - \centering - \subfloat[Half Adder Ngspice Plot]{ - \includegraphics[width=\lgfig]{figures/ha_ngspiceplot.png} - \label{ha_ngspiceplot}} \hfill - \subfloat[Half Adder Python Plot]{ - \includegraphics[width=\lgfig]{figures/ha_pythonplot.png} - \label{ha_pythonplot}} - \caption{Half Adder Simulation Output} +\item An optional command \textbf{RUN SANDPIPER-SAAS} gets run Transaction-Level Verilog Code(.tlv) before the \textbf{RUN VERILATOR} command. This command in run to convert the Transaction-Level Verilog Code to the SystemVerilog Code which is easily accessible to the verilator. +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =5cm]{./NgVeri/modelcreated.png} +\caption{NgVeri Model created} +\label{ngmodel} \end{figure} -\end{itemize} -%-------------------------Full Wave Rectifier using SCR------------------------------------------ +\begin{figure}[H] +\centering +\includegraphics[width = 12cm, height =10cm]{./NgVeri/error1.png} +\caption{NgVeri Model creation error} +\label{ngverierror} +\end{figure} +\item In case of any error encountered in NgVeri terminal after running Verilog to Ngspice converter, then those errors will be displayed in the terminal in Red color in any of the commands discussed above. Debug the errors as per the messages displayed in the terminal. In \figref{ngverierror}, the error message is displayed in Red color in NgVeri terminal. -\pagebreak +\end{enumerate} -\subsection{Full Wave Rectifier using SCR} +\subsection {Creating of Schematic of 8 bit counter} -\subsubsection{Problem Statement:} Plot the Input and Output Waveform of Full Wave Rectifier using SCR. +In this section, we will create a new project in eSim, create the schematic and run the simulation for 8 bit counter. Steps for schematic creation are as follows: -\subsubsection{Solution:} +\begin{enumerate} -\begin{itemize} +\item Click on \textbf{New Project} icon to create a new project as shown in \figref{newproject}, be careful of the naming conventions. -\item Creating Schematic: To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ -After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library.\\ -After all the required components of the Full Wave Rectifier using SCR circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}.\\ -Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. +\item After successful creation of NgVeri model using the Verilog code, you can create the schematic of your design by clicking on \textbf{Open Schematic} button on the left pane of the eSim window as shown in \figref{newschematic}. A confirmation pop-up window appears. Click on \textbf{Yes} to create a new schematic. A blank schematic created is shown in \figref{blankschematic} -The \figref{fwrscr_schematic} shows the complete Rectifier circuit using SCR after removing the errors. -\begin{figure}[!htp] - \centering - \includegraphics[width=\hgfig]{figures/fwrscr_schematic.png} - \caption{Schematic of Full Wave Rectifier using SCR} - \label{fwrscr_schematic} +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =5cm]{./NgVeri/newproject.png} +\caption{Creation of new project in eSim} +\label{newproject} \end{figure} -The KiCad netlist is generated as shown in \figref{fwrscr_netlistgeneration}.\\ -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/fwrscr_netlistgeneration.png} - \caption{Full Wave Rectifier using SCR Netlist Generation} - \label{fwrscr_netlistgeneration} -\end{figure} +\item Next step is to click on \textbf{Place component} icon to place the components in the schematic editor as shown in \figref{blankschematic}. -\pagebreak +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =7cm]{./NgVeri/newschematic.png} +\caption{Creation of new schematic in eSim} +\label{newschematic} +\end{figure} -\item Convert KiCad to Ngspice: -After creating KiCad netlist click on KiCad-Ngspice converter button.\\ +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =7cm]{./NgVeri/blankschematic.png} +\caption{Blank schematic created in eSim} +\label{blankschematic} +\end{figure} -This will open converter window where you can enter details of Analysis, Source values, Ngspice model and Subcircuit. +\item To locate the components in eSim library, click on \textbf{Place component} icon as shown in \figref{blankschematic}. A pop-up window named \textbf{Choose Component} appears. User can type component name in the space as shown in \figref{choosemodel}. -\begin{figure}[!htp] - \centering - \subfloat[Full Wave Rectifier using SCR Analysis]{ - \includegraphics[width=\smfig]{figures/fwrscr_analysistab.png} - \label{fwrscr_analysistab}} \hfill - \subfloat[Full Wave Rectifier using SCR Source Details]{ - \includegraphics[width=\smfig]{figures/fwrscr_sourcedetailstab.png} - \label{fwrscr_sourcedetailstab}} \vfill - \subfloat[Full Wave Rectifier using SCR Subcircuit Model]{ - \includegraphics[width=\smfig]{figures/fwrscr_subcircuitstab.png} - \label{fwrscr_subcircuitstab}} - \caption{Analysis, Source and Subcircuit tab} -\end{figure} - -Subcircuit of SCR in \figref{scr_sub} -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/scr_sub.png} - \caption{SCR Subcircuit} - \label{scr_sub} +\begin{figure}[H] +\centering +\includegraphics[width = 12cm, height =7cm]{./NgVeri/choosemodel.png} +\caption{Locating the model in library} +\label{choosemodel} \end{figure} -\pagebreak +\item In this example, counter8bit model is created under eSim NgVeri library. The model view is visible with two input pins reset and clock and 8 output pins from out0 to out7 as shown in \figref{choosemodel}. Click on \textbf{OK} to place the component on the schematic editor as shown in \figref{placemodel}. -\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. - \begin{figure}[!htp] - \centering - \subfloat[Full Wave Rectifier using SCR Ngspice Plot]{ - \includegraphics[width=\lgfig]{figures/fwrscr_ngspiceplot.png} - \label{fwrscr_ngspiceplot}} \hfill - \subfloat[Full Wave Rectifier using SCR Python Plot]{ - \includegraphics[width=\lgfig]{figures/fwrscr_pythonplot.png} - \label{fwrscr_pythonplot}} - \caption{Full Wave Rectifier using SCR Simulation Output} +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =7cm]{./NgVeri/placingmodel.png} +\caption{Placement of component in Schematic Editor} +\label{placemodel} \end{figure} -\end{itemize} - +\item Now create the schematic as shown in \figref{circuitschematic}, annotate, perform electrical rules check (ERC), create the netlist and save the schematic by following the steps given in \chapref{chap5}. -%-------------------------Oscillator------------------------------------------ -\pagebreak +\begin{figure}[H] +\centering +\includegraphics[width = 16cm, height =6cm]{./NgVeri/schematicwithblockdescription.png} +\caption{Example of a 8 bit Counter circuit in eSim} +\label{circuitschematic} +\end{figure} -\subsection{Oscillator Circuit} +\end{enumerate} -\subsubsection{Problem Statement:} Plot the Oscillation Waveforms for Phase Shift Oscillator circuit. +\subsection{Ngspice Simulation of 8 bit counter} -\subsubsection{Solution:} -The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given in the window shown in \figref{rc1}. +In this section, we will run the simulation and plot input-output waveforms for 8 bit counter. Steps for Ngspice simulation and plotting results are as follows: -\begin{itemize} -\item Creating Schematic: -To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ +\begin{enumerate} -After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the -right toolbar which opens the component library.\\ +\item After creating the schematic, click on \textbf{KiCad to Ngspice Converter} icon and select the type of analysis as transient and set the start, step and stop time as shown in \figref{kitong} -After all the required components of the Oscillator circuits are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}\\sss +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =6cm]{./NgVeri/KiCadtoNgspice.png} +\caption{KiCad to Ngspice conversion steps} +\label{kitong} +\end{figure} + + +\item Now click on Source Details and enter the values for Source v1 and Source v2 as shown in \figref{sourcev1} and \figref{sourcev2} -Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. After completing all the above steps the Oscillator schematic will look like \figref{osc_schematic}.\\ +\begin{figure}[H] +\centering +\includegraphics[width = 13cm, height =5cm]{./NgVeri/sourcev1.png} +\caption{Values for Source v1} +\label{sourcev1} +\end{figure} -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/osc_schematic.png} - \caption{Schematic of Phase Shift Oscillator circuit} - \label{osc_schematic} +\begin{figure}[H] +\centering +\includegraphics[width = 13cm, height =5cm]{./NgVeri/sourcev2.png} +\caption{Values for Source v2} +\label{sourcev2} \end{figure} -\pagebreak +\item In this counter example, no device modeling and sub-circuit build up is required. Now click on the \textbf{Convert} button as shown in \figref{KiCadconv}. This will convert KiCad schematic into Ngspice code i.e it creates the simulation compatible netlist. -KiCad netlist is generated as shown in the \figref{osc_netlistgeneration} \\ +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =6cm]{./NgVeri/KiCadconv.png} +\caption{KiCad to Ngspice conversion} +\label{KiCadconv} +\end{figure} -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/osc_netlistgeneration.png} - \caption{Phase Shift Oscillator circuit Netlist Generation} - \label{osc_netlistgeneration} +\item Next, right click on \textbf{Counter} and click on \textbf{Refresh} as shown in \figref{refresh}. It can be seen that Project\_Name.cir.out file (Note: In this example, project name is Counter, so the file name is Counter.cir.out) is added after pressing refresh. Repeat this step for every rerun of KiCad to Ngspice conversion. + +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =7cm]{./NgVeri/refreshbefore.png} +\caption{Cir.out file added after conversion} +\label{refresh} \end{figure} -\item Convert KiCad to Ngspice: After creating KiCad netlist, click on the {\tt KiCad-Ngspice converter} button. This will open converter window where you can enter details of Analysis, Source values and Device library. +\item Next, right click on \textbf{Counter.cir.out} file and open it as shown in \figref{cirout1}. This file consists of Ngspice netlist of 8 bit counter including information of source, input and output plot labels, transient analysis parameters and control and plot statements. Refer \figref{cirout1} and \figref{cirout2} -\begin{figure}[!htp] - \centering - \subfloat[Phase Shift Oscillator Analysis]{ - \includegraphics[width=\smfig]{figures/osc_analysistab.png} - \label{osc_analysistab}} \hfill - \subfloat[Phase Shift Oscillator Details]{ - \includegraphics[width=\smfig]{figures/osc_sourcedetailstab.png} - \label{osc_sourcedetailstab}} \hfill - \subfloat[Phase Shift Oscillator Device Modeling]{ - \includegraphics[width=\smfig]{figures/osc_devicemodelingtab.png} - \label{osc_devicemodelingtab}} - \caption{Analysis, Source and Device Tab} +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =8cm]{./NgVeri/cirout1.png} +\caption{Cir.out file details Part 1} +\label{cirout1} \end{figure} -Under device library you can add the library for diode used in the circuit. If you do not add any library it will take default Ngspice model. +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =8cm]{./NgVeri/cirout2.png} +\caption{Cir.out file details Part 2} +\label{cirout2} +\end{figure} +\item To run simulation click on \textbf{Simulation} icon as shown in \figref{cirout2}. It will display input and output plots for 8 bit counter as shown in \figref{outputsim1}. You can see the plots of input clock, input reset and outputs out0 to out7. However, these plots are not in order. -\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. -\begin{figure}[!htp] - \centering - \subfloat[Ngspice Plot of Phase Shift Oscillator]{ - \includegraphics[width=\lgfig]{figures/osc_ngspiceplot.png} - \label{osc_ngspiceplot}} \hfill - \subfloat[Python Plot of Phase Shift Oscillator]{ - \includegraphics[width=\lgfig]{figures/osc_pythonplot.png} - \label{osc_pythonplot}} - \caption{Phase Shift Oscillator Simulation Output} +\begin{figure}[H] +\centering +\includegraphics[width = 15cm, height =7cm]{./NgVeri/output1.png} +\caption{Input and Output simulation plots of 8 bit Counter} +\label{outputsim1} \end{figure} +\item Close the simulations plots, and right click on \textbf{Counter} button and click on \textbf{Refresh} button as shown in \figref{refresh} to update the plot data files in the Projects folder. -\end{itemize} +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =7cm]{./NgVeri/control1.png} +\caption{Editing the plots statements for stacked waveforms} +\label{control1} +\end{figure} -%-------------------------BJT CB Characteristics------------------------------------------ -\pagebreak +\begin{figure}[H] +\centering +\includegraphics[width = 15cm, height =7cm]{./NgVeri/finalouput.png} +\caption{Stacked Input and Output Simulation plots of 8 bit counter} +\label{finaloutput} +\end{figure} -\subsection{Characteristics of BJT in Common Base Configuration} +\item To view the plots in order and stacked manner, open Counter.cir.out file, do the changes in the plot statements as shown in \figref{control1}. -\subsubsection{Problem Statement:} Plot Characteristics of BJT in Common Base Configuration. +\item Running simulation again will result in the output of 8 bit counter as shown in \figref{finaloutput}. -\subsubsection{Solution:} -The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given in the window shown in \figref{rc1}. +\end{enumerate} -\begin{itemize} -\item Creating Schematic: -To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ +\section {Common errors encountered in Makerchip-NgVeri:} -After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the -right toolbar which opens the component library.\\ +This section describes the most common errors faced by the user while building projects using Makerchip-NgVeri feature in eSim. -After all the required components of the simple Half Wave rectifier circuits are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}\\ +\begin{enumerate} -Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. After completing all the above steps the BJT in CB Configuration schematic will look like \figref{cb_schematic}.\\ +\item In Makerchip tab, when the user clicks on Add Top Level Verilog button to load the file, the allowed file extension's should be either .v, .sv or .tlv as shown in \figref{filext}. It will not accept any other file extension. -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/cb_schematic.png} - \caption{Schematic of BJT in CB Configuration circuit} - \label{cb_schematic} +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =11cm]{./NgVeri/svfile.png} +\caption{File extension allowed in NgVeri} +\label{filext} \end{figure} -\pagebreak -KiCad netlist is generated as shown in the \figref{cb_netlistgeneration} \\ +\item User should avoid spaces or special characters in the path to file. \figref{path} shows file path and workspace path without any spaces and special characters. -\begin{figure}[!htp] - \centering - \includegraphics[width=\lgfig]{figures/cb_netlistgeneration.png} - \caption{BJT in CB Configuration circuit Netlist Generation} - \label{cb_netlistgeneration} + +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =8cm]{./NgVeri/path.png} +\caption{File and workspace path without spaces and special characters} +\label{path} \end{figure} -\item Convert KiCad to Ngspice: After creating KiCad netlist, click on the {\tt KiCad-Ngspice converter} button. This will open converter window where you can enter details of Analysis, Source values and Device library. +\item The verilog file should have Read and write Permissions. To set read and write permissions of the verilog file, right click on verilog file and click on \textbf{Properties}. Next click on \textbf{Permissions} and select access as \textbf{Read and write} as shown in \figref{rdwr}. -\begin{figure}[!htp] - \centering - \subfloat[BJT in CB Configuration Analysis]{ - \includegraphics[width=\smfig]{figures/cb_analysistab.png} - \label{cb_analysistab}} \hfill - \subfloat[BJT in CB Configuration Source Details]{ - \includegraphics[width=\smfig]{figures/cb_sourcedetailstab.png} - \label{cb_sourcedetailstab}} \hfill - \subfloat[BJT in CB Configuration Device Modeling]{ - \includegraphics[width=\smfig]{figures/cb_devicemodelingtab.png} - \label{cb_devicemodelingtab}} - \caption{Analysis, Source and Device Tab} +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =7cm]{./NgVeri/readwritepermission.png} +\caption{Read-Write Permissions for Verilog file} +\label{rdwr} \end{figure} -Under device library you can add the library for diode used in the circuit. If you do not add any library it will take default Ngspice model. +\item Do not delete or rename the verilog file while it is loaded in eSim. +\item If one gets an error in the NgVeri terminal, please clear the terminal and rerun. -\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. -\begin{figure}[!htp] - \centering - \subfloat[Ngspice Plot of BJT in CB Configuration]{ - \includegraphics[width=\lgfig]{figures/cb_ngspiceplot.png} - \label{cb_ngspiceplot}} \hfill - \subfloat[Python Plot of BJT in CB Configuration]{ - \includegraphics[width=\lgfig]{figures/cb_pythonplot.png} - \label{cb_pythonplot}} - \caption{BJT in CB Configuration Simulation Output} +\item Do not use delays in the verilog code (as verilator does not support it). + +\item Verilog filename should be the same as top-level verilog module name, otherwise the following error message will appear as shown in \figref{error1}. This error appears when a user tries to open TL verilog in Makerchip by clicking \textbf{Edit in Makerchip} button. + +\begin{figure}[H] +\centering +\includegraphics[width = 14cm, height =6cm]{./NgVeri/modulenameerror.png} +\caption{Verilog file and module name error} +\label{error1} \end{figure} +\item \textbf{Verilator lint-off errors:} Lint-off commands will create this error in verilog code in Makerchip IDE can be resolved by removing such lint-off commands as shown in \figref{makerchiperror} and \figref{lintofferror}. Details about dealing with removal of such errors are already discussed in Makerchip steps in eSim. + +\item \textbf{Unexpected reg error:} This type of error can occur after compiling TL verilog code in Makerchip IDE visible in Log section (Refer \figref{regerror}). This error can be rectified by removing word \textit{reg} from top level verilog code as shown in \figref{removereg}. More details are discussed in Makerchip steps in eSim. + +\end{enumerate} + + -\end{itemize} diff --git a/chap_12.tex b/chap_12.tex index df84884d..5e5e518c 100644 --- a/chap_12.tex +++ b/chap_12.tex @@ -1,409 +1,153 @@ -\chapter{PCB Design} +\chapter{OpenModelica} \thispagestyle{empty} -\label{chap12} - -Printed Circuit Board (PCB) \index{PCB} design is an important -step in electronic system design. Every component of the circuit -needs to be placed and connections routed to minimise delay and -area. Each component has an associated footprint. Footprint refers to -the physical layout of a component that is required to mount it on the -PCB. PCB design involves associating footprints to all components, placing them appropriately to -minimise wire length and area, connecting the footprints using -tracks or vias and finally extracting the required files needed for -printing the PCB. Let us see the steps to design PCB using eSim. - -\section{Schematic creation for PCB design} -In \chapref{chap5}, we have seen the differences between schematic for -simulation and schematic for PCB design. Let us design a PCB Layout for a 'constant 5V DC supply' circuit named as \texttt{7805VoltageRegulator}. First, we will simulate the circuit. Refer to \figref{pcbschfin} for the schematic used for simulation. After satisfying simulation results, we will move to PCB design. For this, we will remove the Source(s), Probes (plot\_v , plot\_db etc.), and global labels connected \texttt{solely} for the purpose of viewing simulation plots conveniently. \\ Connectors are the physical components that are used to interface/connect the board to external peripherals or sources. +\label{chap11} -\begin{figure} -\centering -\includegraphics[width=\lgfig]{NGHDL/pcbschinitial.png} -\caption{Schematic for simulation of the constant 5V DC supply circuit} -\label{pcbschfin} -\end{figure} - -%Create the circuit schematic as shown in \figref{pcbschfin}. The two pin female -%connector (\texttt{Conn\_01x02\_Female}) can be placed from the Eeschema's \texttt {Conn} library. Do the annotation and -%test for ERC. Refer to \chapref{chap5} to know more about -%basic steps in schematic creation. - - -\subsection{Removing components required for simulation from the schematic} -\begin{itemsize} -\item We will remove the components which were placed for simulation purpose only. -\item Components that will be placed on the board need to be added in the schematic. -\item Modify the circuit schematic as shown in \figref{pcbschconn}. The two pin female connector (\texttt{Conn\_01x02\_Female}) is placed for the taking the 5V output supply meanwhile a 2 pin Screw Terminal (\textt{Screw\_Terminal\_01x02}) is used to transmit the input signal on board. Do the annotation and test for ERC. Refer to \chapref{chap5} to know more about basic steps in schematic creation. -\begin{figure} -\centering -\includegraphics[width=\lgfig]{NGHDL/pcbschwithconn.png} -\caption{Schematic after adding connectors and removing the probes and sources.} -\label{pcbschconn} -\end{figure} -\end{itemsize} - -\subsection{Mapping of components using Cvpcb} -%\index{Footprints!mapping} \index{Footprint Editor} -\index{Component!footprint!mapping} +\section {Introduction} +OpenModelica (OM) is an open source modeling and simulation tool based on +Modelica language. Modelica is an object oriented language. As a result, it has all the +features of an object oriented language such as inheritance. Models or circuits are +defined in the form of classes, with in which there are components, functions, +connection and placement information. The OM suite has the following major tools. -\item Once the schematic for PCB Design is created, one needs to map each component -in the schematic to the appropriate footprint. The tool \texttt{Cvpcb} is -used for this. -\item Cvpcb can be launched by clicking the icon \texttt{Run Cvpcb to associate footprints and components} in Eeschema or by going under the \textt{Tools} menu and selecting \texttt{Assign Component Footprint} option. +\subsection {OMEdit} +An IDE for modeling and simulation. It supports a lot of electrical components. It +has a good graphical interface to drag and drop components and create the circuit. +One can only do transient simulation using this interface. An attractive feature of +OMEdit is the plotting interface. All the parameters in the circuit like voltages and currents through each component, +parameters like frequency, delay etc. will be displayed as +a list, after simulation. The user can choose the variables to be plotted in an +interactive manner from this list. On choosing the variable to plot, it will be plotted +on the plot window. One can also create multiple plot windows. -\subsection{Familiarising with Cvpcb Window} -\index{Cvpcb} -\begin{itemsize} -\item I. When one opens \texttt{Cvpcb} after annotating and running ERC on the schematic intended for PCB Design a window as shown in \figref{cvpcb} will be obtained. The Toolbar for using Cvpcb will be available in the top-most left corner. -\begin{figure} -\centering -\includegraphics[width=\lgfig]{NGHDL/cvpcb_unassigned.png} -\caption{Cvpcb window} -\label{cvpcb} -\end{figure} -\item II. The left pane has a list of all footprint libraries in the database. -\item III. The middle pane displays the list of components present in the schematic and if any footprint is assigned/associated to them. -\item IV. The right pane has a list of available footprints for each component depending upon how of libraries. -\end{itemsize} +\subsection {OMOptim} +An IDE for optimisation. It lists all the variables in the given model. One can choose +the variables to be optimised from the list. Multiple models can be loaded for a given +optimisation problem. One can do multi objective optimisations as well. It supports +various optimisation algorithms such as Particle Swarm Optimisation (PSO) and +Simulated Annealing (SA). The results are displayed graphically. +\section {OpenModelica in eSim} +The above two functionalities can be accessed through the {\tt Modelica Converter} and {\tt OM Optimisation} tools on the eSim left toolbar. The two examples given below illustrates how to use OpenModelica in eSim. +\subsubsection {Low Pass Filter circuit} +Let us now see how to simulate a low pass filter in OpenModelica. +\begin{enumerate} +\item Open the schematic and create the circuit as shown in \figref{lowpass}. -\subsubsection{ Cvpcb Toolbar} -Some of the important tools in the toolbar are shown in -\figref{tb_fe}. They are explained below (Order of operation should ideally be from RIGHT to LEFT): -\begin{figure} +\begin{figure}[h] \centering -\includegraphics[width=\hgfig]{tb_fe.png} -\caption{Cvpcb Toolbar} -\label{tb_fe} +\includegraphics[width=\lgfig]{list_of_figures/1.png} +\caption{Circuit schematic: Low pass filter} +\label{lowpass} \end{figure} -\begin{compactenum} -\item Filter footprints list by library : We recommend the use of only this as a filtering method if you are completely new to eSim and/or PCB Design as it narrows down footprints based on libraries of the type of the component. When a filter is selected, it's icon will be highlighted in light red color as seen in \figref{tb_fe}. -\item Filter footprints list by pin count : This will filter the footprints based on number of pins the footprint has. This can be used to narrow down your search after sorting footprints by their library type. -\item Filter footprints list by keyword - This filters the footprints in the database based on keywords. -\item Automatic footprint association - Perform footprint association - for each component automatically. Footprints will be selected from - the list of footprints available.\\ - Note: This method of association is not recommended at all. -\item Delete all associations - Delete all the footprint associations made. This will erase all your association till now so be very careful in selecting this. - \item Select next unlinked component: Using this you can go to the next component in the list of components for associating a footprint. - \item Select previous unlinked component: Using this you can go to the previous component in the list of components for associating a footprint. -\item View selected footprint - View the selected footprint in 2D. See \secref{viewfp} for more details. \\ - Before clicking on this, make sure that a footprint is selected. Order of this operation should be - \\ 1. Selection of footprint library from the left-most pane - \\ 2. Selecting a footprint from the right-most pane - \\ 3. Click on \textt{View selected footprint} -\item Edit footprint library table - One should familiarize themselves with Cvpcb first and then only choose to use this. This impacts the footprints that you can choose, so be careful before making any severe changes. -\item Save netlist and footprint files - Save the netlist and the - footprints that are associated with it. One ought to save the association after having assigned proper footprints to all the components. -\end{compactenum} - -\subsection{Viewing footprints in 2D and 3D} -\index{Footprints!view!2D} -\index{Footprints!view!3D} -\label{viewfp} -\item To view a footprint in 2D, select the component for which you wish to view the available footprints, then select the library from left-most pane and now from the right pane and click on the desired footprint and click on \texttt{View selected footprint} from the menu bar. -Let us view a footprint for \texttt{C1} from the \texttt{Capacitors\_THT} footprint library. Choose C1 from the middle pane as shown, click on \texttt{Capacitors\_THT} in the left-most pane and select the -\textit{View selected footprint} tool. -On clicking the \textbf{View selected footprint} tool, the {\tt Footprint} window with the view in 2D will be displayed. 2D view of the footprint \texttt{CP\_Radial\_D5.0mm\_P2.50mm} is shown in \figref{2dview}. -\begin{figure} +\item Create the KiCad netlist. Now the analysis and analysis parameters are given as shown in \figref{lowpass-analysis}. + +\begin{figure}[h] \centering -\includegraphics[width=\lgfig]{smnew.png} -\caption{Viewing footprint for C1} -\label{sm} +\includegraphics[width=\lgfig]{list_of_figures/2.png} +\caption{Analysis parameters: Low pass filter} +\label{lowpass-analysis} \end{figure} -\item Click on the \texttt{3D Display} icon in the {\tt Footprint} -window, as shown in \figref{2dview}. A top view of the selected footprint -in 3D is obtained. Click on the footprint and rotate it using the computer mouse to -get 3D views from various angles. One such view of the footprint -in 3D is shown in \figref{3dv}. +\item The source details are given as in \figref{lowpass-source}. The generated KiCad netlist is then converted to ngspice compatible netlist. -\begin{figure} +\begin{figure}[h] \centering -\includegraphics[width=\lgfig]{manual_images/2dviewofcp.png} -\caption{Footprint \texttt{CP\_Radial\_D5.0mm\_P2.50mm}'s view in 2D.} -\label{2dview} +\includegraphics[width=\lgfig]{list_of_figures/3.png} +\caption{Source details: Low pass filter} +\label{lowpass-source} \end{figure} -\begin{figure} -\centering -\includegraphics[width=\lgfig]{manual_images/3dv.png} -\caption{3D view of the footprint} -\label{3dv} -\end{figure} - -\subsection{Mapping of components in the circuit} -\begin{itemsize} -\begin{compactenum} -\item Click on {\tt C1} from the middle pane. Choose the footprint library \textit{Capacitors\_THT} -from the left pane and locate the footprint \texttt{CP\_Radial\_D5.0mm\_P2.50mm}. By double clicking on it, the said footprint will be assigned to {\tt C1}. -\item Similarly choose the footprints per \figref{map} where the footprint association for all the footprints is shown in \figref{map}. Save the footprint association by clicking on the -\texttt{Save footprint association in schematic component footprint fields} tool from the {\tt CvPcb toolbar}. -\end{compactenum} -\end{itemsize} +\item Simulate the ngspice netlist. The simulation curves are shown in \figref{lowpass-simulation}. -\begin{figure} -\centering -\includegraphics[width=0.85\linewidth]{manual_images/map.png} -\caption{Footprint mapping completed for the circuit} -\label{map} -\end{figure}. - -\subsection{Netlist generation for PCB} -\index{Netlist!for PCB} \index{Netlist} -\label{netc} -\begin{figure} +\begin{figure}[h] \centering -\includegraphics[width=\lgfig]{manual_images/netlistpcb.png} -\caption{Netlist generation for PCB} -\label{netlistpcb} -\end{figure} -\begin{itemsize} -\begin{compactenum} -\item After having saved your footprint association, switch back to the Eeschema window and press Ctrl+S. -\item The netlist for PCB is different from that for simulation. To generate -netlist for PCB, click on the \textit{Generate netlist} tool from the -top toolbar in Schematic editor. -\item In the \textt{Netlist} window, under the tab \textit{Pcbnew}, Select the option \texttt{Default format}. This is shown in \figref{netlistpcb}. Click on \texttt{Generate} option. -\item Click on \texttt{Save} in the Save netlist file dialog box that opens up. Do not change the directory or the name of the netlist file. \texttt{Note that the netlist for PCB has an extension \emph{.net}. The netlist created for simulation has an extension \emph .cir}. -\end{compactenum} -\end{itemsize} - - -\section{Creation of PCB layout} -\index{PCB Layout!creation} \index{Layout Editor} - -The next step is to place the footprints and lay tracks between them -to get the layout. This is done using the \textit{Layout Editor} -tool. eSim uses {\tt Pcbnew}, the layout creation tool in KiCad, as -its layout editor. - -\subsection{Launching Pcbnew} -\begin{compactenum} -\item To Launch the layout editor, \texttt{Pcbnew}, click on the \texttt{Run Pcbnew to layout printed circuit board} icon on the top right corner of the Schematic window. -\item Similarly, you can also click on \texttt{Tools}, and select the \texttt{Layout printed circuit board} option. -\item After doing either of the steps above, click \textbf{yes} on the \textit{Confirmation Box} that will appear on the screen. -\end{compactenum} - -\subsection{Familiarizing the Layout Editor tool} -\index{Layout Editor} - -The layout editor with the various menu bar and toolbars is shown in -\figref{pcbnew}. -\begin{figure} -\centering -\includegraphics[width=0.68\linewidth]{NGHDL/toptble.png} -\caption{Layout editor with menu bar, toolbars and layer options} -\label{pcbnew} +\includegraphics[width=\lgfig]{list_of_figures/4.png} +\caption{Simulation: Low pass filter} +\label{lowpass-simulation} \end{figure} +\item Now to use OpenModelica, click on {\tt Modelica Converter} in the bottom left of eSim left toolbar.{\textit Make sure you have OpenModelica installed in the system}. This converter converts the spice netlist to Modelica format. Click on the LPF in the left that is appended in OpenModelica main window. Make sure you are in text view to see the Modelica code as shown in \figref{om-convert} Figure shows that LPF circuit is being used as a model, the initialisation of sources and components are in the beginning followed by the connection information. n3, n0,n2 are the nodes. -\subsubsection{Top toolbar} -Some of the important menu options in the top menu bar are shown in -\figref{pcbnew}. They are explained below: -\begin{compactenum} -\item Save board - Save the printed circuit board -%\item Module editor - Open module editor to edit footprint modules or - % libraries - \item Plot - This enables users to import their design in Gerber, PDF, SVG and few more formats depending on the requirement. -\item Read netlist - Import the netlist whose layout needs to be - created. -\item Perform design rules check - Check for design rules, unconnected - nets, etc., in the layout. -\item Select working layer - Selection of working layer.\\ -Note: Selection of working layer can also be done from the \texttt{Layers toolbar} on the right-most side of the Pcbnew tool window. -\end{compactenum} - -\subsection{Hotkeys} -\index{Hotkeys!Layout editor} -A list of few important hotkeys is given below: -\begin{compactenum} -\item F1 - Zoom in -\item F2 - Zoom out -\item Delete - Delete Track or Footprint -\item X - Add new track -\item V - Add Via -\item M - Move Item -\item F - Flip Footprint -\item R - Rotate Item -\item G - Drag Footprint -\item Ctrl+Z - Undo -\item E - Edit Item -\end{compactenum} -The entire list of Hotkeys can be viewed by selecting \textit{Preferences} from the top -menu bar and choosing \textit{List Current Keys} from the option \textit{Hotkeys}. -\begin{figure} +\begin{figure}[h] \centering -\includegraphics[height=0.4\textwidth]{manual_images/hotkeys.png} -\caption{Default Hotkeys} -\label{netlisttop} +\includegraphics[width=\lgfig]{list_of_figures/5.png} +\caption{OpenModelica: Text view} +\label{om-convert} \end{figure} -%[width=0.5\textwidth] -\subsection{Designing PCB layout for 7805VoltageRegulator circuit} \index{PCB design} -Click on \textit{Read Netlist} tool from the top toolbar of Pcbnew. Click on -\textit{Browse Netlist files} on the Netlist window that opens -up. Select the {\tt .net} file that was modified \\\texttt{after} -assigning footprints. Click on \textit{Open}. Now Click on -\textit{Read Current Netlist} on the Netlist window. The -sequence of operations is shown in \figref{brnet}. -\index{PCB design!move modules} \index{PCB design!lay tracks} +Default Modelica libary is used for electrical sources and components. This has to imported so that it can be used in the current circuit. This is available in the left side of main window. -\begin{figure} -\centering -\includegraphics[width=0.67\linewidth]{manual_images/readnetlist.png} -\includegraphics[width=0.67\textwidth]{manual_images/browsenetlistforpcb.png} -\caption{Importing netlist file to layout editor: 1. Browse netlist - Files, 2. Choose the appropriate .net file, 3. Read Netlist file, 4. Close} -\label{brnet} -\end{figure} - -\subsubsection{Arranging the footprints} -\begin{compactenum} -\item After clicking on Read Netlist button and closing the Read Netlist window, the footprints that we assigned will appear on the Pcbnew screen in a cluttered fashion, stacked on top of each other as shown in \figref{cluttered} -\begin{figure} -\centering -\includegraphics[height=0.4\textwidth]{cluterredFPs.png} -\caption{Cluttered footprints} -\label{cluttered} -\end{figure} +\item Click on Simulation Setup on the toolbar at the top. A window opens as shown in \figref{om-simsetup}. Give start and stop time. Click {\tt OK}. -\item Let us separate these footprints and place them in proper orientation per the requirement of the circuit. Let us start with Screw\_Terminal\_01x02 footprint. -\item Right Click on the text \textt{Screw\_Terminal\_01x02} in the Pcbnew window, and select \texttt{Footprint J1 on F.Cu.} and select the \texttt{Move} option from the list. -\item The footprint will be glued to the cursor and it can be placed in the location of one's choice by moving the cursor at the desired location and clicking once to place it there. -\begin{figure} +\begin{figure}[h] \centering -\includegraphics[height=0.4\textwidth]{FPMove.png} -\caption{Moving the footprint} -\label{movingFP} +\includegraphics[width=\lgfig]{list_of_figures/6.png} +\caption{OpenModelica: Simulation setup} +\label{om-simsetup} \end{figure} -\item We have moved the Screw\_Terminal\_01x02 footprint to the left side of the Pcbnew window. -\item Once again right click on the text \textt{Screw\_Terminal\_01x02} in the Pcbnew window, and select \texttt{Footprint J1 on F.Cu.} and select the \texttt{Rotate +} option from the list as shown in \figref{rotateFP} -\begin{figure} -\centering -\includegraphics[height=0.4\textwidth]{rotatefp.png} -\caption{Rotating the footprint} -\label{rotateFP} -\end{figure} -\item Using similar methods, we have moved and rotated all other footprints as shown in \figref{rotateall} -\begin{figure} +\item A plotting window opens. Click on the node at the right to display the waveform. The window is shown in \figref{om-simulation}. + +\begin{figure}[h] \centering -\includegraphics[height=0.4\textwidth]{fpsmovedandrotated.png} -\caption{All footprints moved and rotated} -\label{rotateall} +\includegraphics[width=\lgfig]{list_of_figures/7.png} +\caption{OpenModelica: Simulation} +\label{om-simulation} \end{figure} -\end{compactenum} -\subsubsection{Setting Design Rules} +\end{enumerate} -\begin{compactenum} -\item Click on \texttt{Design Rules on top of the Pcbnew window, select Design Rules option from the drop down menu there.} -\item \texttt{Design Rules Editor} window will open, Under the \texttt{Net Classes Editor}, locate the \texttt{Track Width} box, erase the default value from the window placed under the \texttt{Track Width} box and enter 1.25 as the track width. -\item Click on \texttt{Global Design Rules}, under Minimum Allowed Values, locate \texttt{Min track width}, erase the default value and enter 1.25 in the data entry field on the right side of it as shown in \figref{DRC_GDR}. This will ensure that all tracks placed are of width 1.25mm and that when we perform Design Rules Check, the checks will be made such that all tracks are of the width 1.25mm will be checked. -\item Click on Ok button and close the Design Editor Rules window. -\end{compactenum} +\subsection {OM Optimisation} -\begin{figure} -\centering -\includegraphics[height=0.4\textwidth]{druleseditor.png} -\caption{Design Rules Editor Window: Global Design Rules} -\label{DRC_GDR} -\end{figure} - -\subsubsection{Drawing the Board Outline} -\begin{compactenum} -\item Board outline defines the physical dimensions of your board. After the fabricator is done placing tracks and other processes, he/she will cut your design from the copper cladded sheet or the material used per your choice, as per your board outline dimensions. Say, if your board outline is of rectangular shape with dimensions 80mmx50mm, the fabricator will cut the copper sheet of the said dimension. Its important to know that all the tracks(physical electrically conductive connections between two nodes or points on a PCB) must lie inside this board outline. -\item We will also choose a board outline of rectangular shape. Select working layer as \texttt{Edge.Cuts} from the Layers menu on the far-right side of Pcbnew. -\item Click on \texttt{Place} from the top-left tool bar of the Pcbnew window and select \texttt{Line or Polygon}. A pencil icon will appear to be tied to the cursor. -\item Click once on the layout editor to start drawing the outline. Drag the cursor either horizontally or vertically. When it comes to the corner of the board, click once and drag the cursor in perpendicular direction. Do this till you reach the origin of the outline, and double click to finish drawing the rectangular outline. Completed outline is as shown in \figref{brdoutline}. -\end{compactenum} +Now let us explore how to use OpenModelica for optimisation through an example. Find the value of resistance R2 that maximises the power dissipated through it for the circuit in \figref{optim-circuit}. This is an illustration of the Maximum Power Transfer Theorem. The power is maximum when R2 = R1, i.e., when R2 = 100. So maximum power would be Pmax = 0.0625. Let us now see the steps to be followed find the value of R2 using eSim. -\begin{figure} +\begin{figure}[h] \centering -\includegraphics[height=0.4\textwidth]{boardoutline.png} -\caption{Drawing a board outline} -\label{brdoutline} +\includegraphics[width=\lgfig]{list_of_figures/8.png} +\caption{Circuit schematic for optimisation} +\label{optim-circuit} \end{figure} -\subsubsection{Placing Tracks} -\begin{compactenum} -\item Select the working layer as B.Cu from the Layers menu on the far-right side of Pcbnew. -\item Click on \texttt{Place} from the top-left tool bar of the Pcbnew window and select \texttt{Track}. A pencil icon will appear to be tied to the cursor. -\item The procedure to place a track between Node 2 of Screw\_Terminal\_01x02 to Node 1 of D3 diode, as shown in \figref{brdoutline} is described in below steps. -\item Working layer is B.Cu., \texttt{Place Track tool} is selected earlier. Click the pencil icon tied to cursor on the Node 2 of Screw\_Terminal\_01x02 and drag the cursor till Node 1 of D3 diode and double click on Node 2 of D3. By double clicking the track will end at Node 2 of D3. Please refer \figref{D3node1track} for the mentioned track being placed. -\begin{figure} -\centering -\includegraphics[height=0.4\textwidth]{firsttrack.png} -\caption{Track placed on B.Cu. between Screw\_Terminal\_01x02 connector and D3 Diode} -\label{D3node1track} -\end{figure} -\item Similarly, all the tracks have been placed as shown in \figref{alltracks}. Please note that tracks shown in green color are on B.Cu. layer whereas the tracks in red color are placed on the F.Cu. layer. -\begin{figure} -\centering -\includegraphics[height=0.4\textwidth]{alltracks.png} -\caption{All tracks placed} -\label{alltracks} -\end{figure} -\end{compactenum} +\begin{enumerate} +\item Follow all the steps as above and generate the Modelica model using the Ngspice to Modelica converter. -\subsubsection{Performing Design Rules Check(DRC)} -\begin{compactenum} -\item After tracks are placed, it is important that the design created by used should not violate any design rules set earlier. -\item Click on \texttt{Perform Design Rules check} button from the top menu bar of Pcbnew. DRC Control Window will pop-up as shown in \figref{DRC}. -\item Click on \texttt{Start DRC}, and observe if any messages/warnings appear in the \texttt{error messages} window at the bottom of the DRC Control window. If there are no errors in the design present, there will not be any errors in the message window as shown in \figref{DRC} -\end{compactenum} +\item The objective function is $Power = i^2 \times R2$ . +To define the objective function, the line $power := i^2 \times R1+ i^2 \times R2$ +is added under the keyword algorithm, in the Modelica model file. -\begin{figure} -\centering -\includegraphics[height=0.4\textwidth]{drc1.png} -\caption{DRC Control Window} -\label{DRC} -\end{figure} +\item Select {\tt OMOptim} from eSim left toolbar, in the displayed window click on {\tt New Project}. Then save the project. It is stored with an extension {\tt .min}. Now select {\tt Models} and then {\tt Load Modelica Library}. Now select {\tt Load mo file} under {\tt Models}. It will be added on the left. -\subsubsection{Exporting the Design to Gerber format} -\begin{compactenum} -\item Click on \texttt{Plot} tool from the top toolbar, select the Plot Format as \texttt{gerber} from the drop down menu of Plot Format. -\item Select the directory in which the user wishes to save the gerber files. -\item Select F.Cu, B.Cu, B.Silks, F.Mask, B.Mask, Margin and Edge.Cuts from the \textit{Layers} on the left side of the Plot window as shown in \figref{plotbef}. -\item After clicking on 'Plot' button, acknowledgment messages can be seen in the 'Messages' window at the bottom of the \texttt{Plot} tool window as shown in \figref{plotaf}. -\end{compactenum} +\item Click {\tt Problems} and then {\tt Optimisation}. Select the model to be optimised. \textit {Note that for optimising, that model has to be loaded in OpenModelica as stated before}. Clicking +blue turnover icon will display all the variables used in the model. Add details like optimsation variables and objective. +The OMOptim project for this problem is given in \figref{om-project}. Power is the objective function that has to be maximized. {\tt r2.R} is the variable that will be varied. {\tt r2.R} is limited between 0 and 1000. -\begin{figure} +\begin{figure}[h] \centering -\includegraphics[height=0.4\textwidth]{plotwindowbefore.png} -\caption{Plot Window before generating gerber files} -\label{plotbef} +\includegraphics[width=\hgfig]{list_of_figures/9.png} +\caption{OMOptim project} +\label{om-project} \end{figure} -\begin{figure} +\item Click on Parameters tab to select the type of algorithm and its parameters. In this example, the optimisation algorithm used is PSO (Particle Swarm Optimisation). The various parameter values given are as follows: population size as 50, Inertia factor as 1, Learning factor: alpha and beta as 2, Population saving frequency was 1. Iteration limit is also specified. Select the .mo file to be simulated from {\tt Files} tab. Click on {\tt Launch}. The results of optimisation for various values of Iteration Limit are given in \figref {table}. + +\begin{figure}[h] \centering -\includegraphics[height=0.4\textwidth]{plotafter.png} -\caption{Plot window after generating gerber files} -\label{plotaf} +\includegraphics[width=\lgfig]{list_of_figures/10.png} +\caption{Optimisation values for various Iteration Limit } +\label{table} \end{figure} -\subsubsection{Viewing the Gerber files generated} -\begin{compactenum} -\item Open the terminal by Ctrl+Alt+T keys, and type \texttt{gerbview} and press enter. Gerbview tool of KiCad will open up. For windows OS users, search for \texttt{gerbview} application through Windows' search application option. -\item Click on File from top-left menu, and select Load Gerber File option. -\item Go to the directory where you have stored the earlier created gerber files as shown in \figref{gerbviewloading} and click on Open. -\item The design created earlier will appear in the gerbview window as shown in \figref{gerbviewcapture}. -\end{compactenum} +\item Depending on the type of algorithm, the time for optimisation varies. Optimised result is graphically displayed as shown in \figref {om-optimised}. \begin{figure} \centering -\includegraphics[height=0.4\textwidth]{gerbviewloading.png} -\caption{Loading gerber files in the gerbview} -\label{gerbviewloading} +\includegraphics[width=\hgfig]{list_of_figures/11.png} +\caption{Optimised value of resistance for maximum power } +\label{om-optimised} \end{figure} -\begin{figure} -\centering -\includegraphics[height=0.4\textwidth]{gerbviewcapture.png} -\caption{Observing the design in Gerber format} -\label{gerbviewcapture} -\end{figure}
\ No newline at end of file +\end{enumerate} + diff --git a/chap_13.tex b/chap_13.tex new file mode 100644 index 00000000..9757ce28 --- /dev/null +++ b/chap_13.tex @@ -0,0 +1,692 @@ +\chapter{Solved Examples} +\thispagestyle{empty} +\label{chap12} + +\section{Solved Examples} + +%---------------RC circuit------------------- +\subsection{Basic RC Circuit} +\subsubsection{Problem Statement:} Plot the Input and Output Waveform of an RC circuit whose input voltage (Vs) is 50Hz, 3V peak to peak. The values of Resistor (R) and Capacitor(C) are $1k$ and $1uf$ respectively. +\subsubsection{Solution:} +\begin{itemize} +\item Creating a Project: +The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given in the pop up window as shown in \figref{rc1}. +\begin{figure}[!htp] + \centering + \includegraphics[width=\hgfig]{figures/rc1.png} + %\includegraphics[width=\linewidth]{figures/rc1.png} + \caption{Creating New Project} + \label{rc1} +\end{figure} + +\item Creating the Schematic: +To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema. + +\begin{figure}[!htp] + \centering + \includegraphics[width=\smfigp]{figures/rc2.png} + %\includegraphics[width=\linewidth]{figures/rc2.png} + \caption{Open Schematic Editor} + \label{rc2} +\end{figure} + +To create a schematic in KiCad, we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library. + +\begin{figure}[!htp] + \centering + \includegraphics[width=\tnfig]{figures/rc_component.png} + %\includegraphics[width=\linewidth]{figures/rc_component.png} + \caption{Place Component Icon} + \label{rc_component} +\end{figure} + +\pagebreak + +After all the required components of the simple RC circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire} + +\begin{figure}[!htp] + \centering + \includegraphics[width=\tnfig]{figures/rc_wire.png} + %\includegraphics[width=\linewidth]{figures/rc_wire.png} + \caption{Place Wire Icon} + \label{rc_wire} +\end{figure} + +Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. + +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/erc1.png} + %\includegraphics[width=\linewidth]{figures/erc1.png} + \caption{Electric Rules Check Icon} + \label{erc1} +\end{figure} + +\figref{rc_complete1} shows the RC circuit after connecting the components by wire. + +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/rc_complete1.png} + \caption{RC circuit} + \label{rc_complete1} +\end{figure} + +\pagebreak + +After clicking the {\tt ERC} icon a window opens up. Click the {\tt Run} button to run rules check. The errors are listed in as shown in \figref{erc2}. This error is handled by adding {\tt Power Flag} as shown in \figref{rc_pwr}. + +\begin{figure}[!htp] + \centering + \subfloat[ERC Run]{ + \includegraphics[width=\smfig]{figures/erc2.png} + \label{erc2}} \hfill + \subfloat[Power Flag]{ + \includegraphics[width= 5cm, height=5cm]{figures/rc_pwr.png} + \label{rc_pwr}} + \caption{ERC check and POWER FLAG} +\end{figure} + +After adding the {\tt Power Flag} the completed RC circuit is shown in \figref{rc_schematic} and the netlist is generated as shown in \figref{rc_netlist}. + + +\begin{figure}[!htp] + \centering + \subfloat[Schematic of RC circuit]{ + \includegraphics[width=\smfig]{figures/rc_schematic.png} + \label{rc_schematic}} \hfill + \subfloat[Generating KiCad Netlist of RC circuit]{ + \includegraphics[width=\smfig]{figures/rc_netlistgeneration.png} + \label{rc_netlist}} + \caption{RC Schematic and Netlist Generation} +\end{figure} + +\pagebreak +\item Convert KiCad to Ngspice: +To convert KiCad netlist of RC circuit to NgSpice compatible netlist click on KiCad to Ngspice icon as shown in \figref{rcki2ng}. + +\begin{figure}[!htp] +\centering +\includegraphics[width=\tnfig]{figures/rc_ki2ng.png} +\caption{Convert KiCad to Ngspice Icon} +\label{rcki2ng} +\end{figure} + +Now you can enter the type of analysis and source details as shown in \figref{rc_analysistab} and \figref{rc_sourcedetailstab} respectively. + +\begin{figure}[!htp] + \centering + \subfloat[RC Analysis]{ + \includegraphics[width=\smfig]{figures/rc_analysistab.png} + \label{rc_analysistab}} \hfill + \subfloat[RC Source Details]{ + \includegraphics[width=\smfig]{figures/rc_sourcedetailstab.png} + \label{rc_sourcedetailstab}} + \caption{RC Analysis and Source Detail} +\end{figure} +The other tab will be empty as RC circuit do not use any Ngspice model, device library and subcircuit. + +After entering the value, press the convert button. It will convert the netlist into Ngspice compatible netlist. + +\pagebreak + +\item Simulation: +To run Ngspice simulation click the simulation icon in the tool bar as shown in the \figref{rcplot}. +\begin{figure}[!htp] +\centering +\includegraphics[width=\tnfig]{figures/rc_plot.png} +\caption{Simulation Icon} +\label{rcplot} +\end{figure} + +In eSim, there are two types of plot. First is normal Ngspice plot and second is interactive python plot as shown in \figref{rc_ngspiceplot} and \figref{rc_pythonplot} respectively. + +\begin{figure}[!htp] + \centering + \subfloat[Ngspice Plot of RC]{ + \includegraphics[width=\lgfig]{figures/rc_ngspiceplot.png} + \label{rc_ngspiceplot}} \hfill + \subfloat[Python Plot of RC]{ + \includegraphics[width=\lgfig]{figures/rc_pythonplot.png} + \label{rc_pythonplot}} + \caption{Ngspice and Interactive Python Plotting} +\end{figure} + +In the interactive python plot you can select any node or branch to plot voltage or current across it. Also it has the facility to plot basic functions across the node like addition, substraction, multiplication, division and v/s. + +\end{itemize} +%-----------------------Half Wave Rectifier--------------------------- +\pagebreak + +\subsection{Half Wave Rectifier} + +\subsubsection{Problem Statement:} Plot the Input and Output Waveform of Half Wave Rectifier circuit where the input voltage (Vs) is 50Hz, 2V peak to peak. The value for Resistor (R) is 1k. + +\subsubsection{Solution:} +The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given in the window shown in \figref{rc1}. + +\begin{itemize} +\item Creating Schematic: +To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ + +After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the +right toolbar which opens the component library.\\ + +After all the required components of the simple Half Wave rectifier circuits are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}\\ + +Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. After completing all the above steps the final Half Wave Rectifier schematic will look like \figref{hwr_schematic}.\\ + +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/hwr_schematic.png} + \caption{Schematic of Half Wave Rectifier circuit} + \label{hwr_schematic} +\end{figure} + +\pagebreak + +KiCad netlist is generated as shown in the \figref{hwr_netlistgeneration} \\ + +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/hwr_netlistgeneration.png} + \caption{Half Wave Rectifier circuit Netlist Generation} + \label{hwr_netlistgeneration} +\end{figure} + +\item Convert KiCad to Ngspice: After creating KiCad netlist, click on the {\tt KiCad-Ngspice converter} button. This will open converter window where you can enter details of Analysis, Source values and Device library. + +\begin{figure}[!htp] + \centering + \subfloat[Half Wave Rectifier Analysis]{ + \includegraphics[width=\smfig]{figures/hwr_analysistab.png} + \label{hwr_analysistab}} \hfill + \subfloat[Half Wave Rectifier Source Details]{ + \includegraphics[width=\smfig]{figures/hwr_sourcedetailstab.png} + \label{hwr_sourcedetailstab}} \hfill + \subfloat[Half Wave Rectifier Device Modeling]{ + \includegraphics[width=\smfig]{figures/hwr_devicemodelingtab.png} + \label{hwr_devicemodelingtab}} + \caption{Analysis, Source and Device Tab} +\end{figure} + +Under device library you can add the library for diode used in the circuit. If you do not add any library it will take default Ngspice model. + + +\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. +\begin{figure}[!htp] + \centering + \subfloat[Ngspice Plot of Half Wave Rectifier]{ + \includegraphics[width=\lgfig]{figures/hwr_ngspiceplot.png} + \label{hwr_ngspiceplot}} \hfill + \subfloat[Python Plot of Half Wave Rectifier]{ + \includegraphics[width=\lgfig]{figures/hwr_pythonplot.png} + \label{hwr_pythonplot}} + \caption{Half Wave Rectifier Simulation Output} +\end{figure} + + +\end{itemize} + +\pagebreak +%-------------- Precision rectifier-------------------------------------- + +%\pagebreak + +%\subsection{Precision Rectifier} +%\subsubsection{Problem Statement:} Plot the input and output waveform of the Precision Rectifier circuit where input voltage (Vs) is $50Hz$ , $3V$ peak to peak. + +%\subsubsection{Solution:} +%The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given as shown in the \figref{rc1}. + +%\begin{itemize} +%\item Creating Schematic: +%To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ +%After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library.\\ +%After all the required components of the precision rectifier circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}.\\ +%Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. +%The \figref{pr_schematic} shows the complete Precision Rectifier schematic after removing the errors. + +%\begin{figure}[!htp] +%\centering +%\includegraphics[width=\hgfig]{figures/pr_schematic.png} +%\caption{Schematic of Precision Rectifier circuit} +%\label{pr_schematic} +%\end{figure} + +%The KiCad netlist is generated as shown in \figref{pr_netlistgeneration}.\\ + +%\begin{figure}[!htp] +% \centering +% \includegraphics[width=\lgfig]{figures/pr_netlistgeneration.png} +% \caption{Precision Rectifier circuit Netlist Generation} +% \label{pr_netlistgeneration} +%\end{figure} + +%\pagebreak + +%\item Convert KiCad to Ngspice: After creating KiCad netlist, click on KiCad-Ngspice converter button.\\ + +% This will open converter window where you can enter details of Analysis, Source values, Device library and Subcircuit. + +%\begin{figure}[!htp] +% \centering +% \subfloat[Precision Rectifier Analysis]{ +% \includegraphics[width=\smfig]{figures/pr_analysistab.png} +% \label{pr_analysistab}} \hfill +% \subfloat[Precision Rectifier Source Details]{ +% \includegraphics[width=\smfig]{figures/pr_sourcedetailstab.png} +% \label{pr_sourcedetailstab}} \vfill +% \subfloat[Precision Rectifier Device Modeling]{ +% \includegraphics[width=\smfig]{figures/pr_devicemodelingtab.png} +% \label{pr_devicemodelingtab}}\hfill +% \subfloat[Precision Rectifier Subcircuit]{ +% \includegraphics[width=\smfig]{figures/pr_subcircuitstab.png} +% \label{pr_subcircuitstab}} +% \caption{Analysis, Source, Device library and Subcircuit tab} +%\end{figure} + +%Under device library you can add the library for the diode used in the circuit. If you do not add any library it will take default Ngspice +%model for diode.\\ + +%Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to add subcircuit it will throw an error. + + +%\pagebreak +%\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run the simulation by clicking the simulation button in the toolbar. +%\begin{figure}[!htp] +% \centering +% \subfloat[Ngspice Plot of Precision Rectifier]{ +% \includegraphics[width=\lgfig]{figures/pr_ngspiceplot.png} +% \label{pr_ngspiceplot}} \hfill +% \subfloat[Python Plot of Precision Rectifier]{ +% \includegraphics[width=\lgfig]{figures/pr_pythonplot.png} +% \label{pr_pythonplot}} +% \caption{Precision Rectifier Simulation Output} +%\end{figure} + +%\end{itemize} + +%-------------- Inverting Amplifier-------------------------------------- + +\pagebreak +\subsection{Inverting Amplifier} +\subsubsection{Problem Statement:} +Plot the Input and Output Waveform of Inverting Amplifier circuit where the input voltage (Vs) is $50Hz$, $2V$ peak to peak and gain is 2. +\subsubsection{Solution:} + +\begin{itemize} +\item Creating Schematic: +To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ +After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library.\\ +After all the required components of the inverting amplifier circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}.\\ +Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. + +The \figref{ia_schematic} shows the complete Precision Rectifier schematic after removing the errors. + +\begin{figure}[!htp] + \centering + \includegraphics[width=\hgfig]{figures/ia_schematic.png} + \caption{Schematic of Inverting Amplifier circuit} + \label{ia_schematic} +\end{figure} + +The KiCad netlist is generated as shown in \figref{ia_netlistgeneration}.\\ +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/ia_netlistgeneration.png} + \caption{Inverting Amplifier circuit Netlist Generation} + \label{ia_netlistgeneration} +\end{figure} + + +\item Convert KiCad to Ngspice: +After creating KiCad netlist, click on KiCad-Ngspice converter button.\\ + +This will open converter window where you can enter details of Analysis, Source values, Device library and Subcircuit. + +Subcircuit of Op-Amp is shown in \figref{ia_sub} + \begin{figure}[!htp] + \centering + \subfloat[Inverting Amplifier Analysis]{ + \includegraphics[width=\smfig]{figures/ia_analysistab.png} + \label{ia_analysistab}} \hfill + \subfloat[Inverting Amplifier Source Details]{ + \includegraphics[width=\smfig]{figures/ia_sourcedetailstab.png} + \label{ia_sourcedetailstab}} \vfill + \subfloat[Inverting Amplifier Subcircuit]{ + \includegraphics[width=\smfig]{figures/ia_subcircuitstab.png} + \label{ia_subcircuitstab}}\hfill + \subfloat[Sub-Circuit of Op-Amp]{ + \includegraphics[width=\lgfig]{figures/ia_sub.png} + \label{ia_sub}} + \caption{Analysis, Source, and Subcircuit tab} + \end{figure} + +\pagebreak +Under subcircuit tab you have to add the subciruit used in your circuit. If you forget to add subcircuit, it will throw an error.\\ + + +\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. +\begin{figure} + \centering + \subfloat[Inverting Amplifier Ngspice Plot]{ + \includegraphics[width=\lgfig]{figures/ia_ngspiceplot.png} + \label{ia_ngspiceplot}}\vfill + \subfloat[Inverting Amplifier Python Plot]{ + \includegraphics[width=\lgfig]{figures/ia_pythonplot.png} + \label{ia_pythonplot}} + \caption{Inverting Amplifier Simulation Output} +\end{figure} + + + +\end{itemize} + +%-------------------------Half Adder------------------------------------------ + +\pagebreak + +\subsection{Half Adder} + +\subsubsection{Problem Statement:} Plot the Input and Output Waveform of Half Adder circuit. + +\subsubsection{Solution:} + +\begin{itemize} + +\item Creating Schematic: To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ +After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library.\\ +After all the required components of the Half Adder circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}.\\ +Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. + +The \figref{ha_schematic} shows the complete Half Adder schematic after removing the errors. +\begin{figure}[!htp] + \centering + \includegraphics[width=\hgfig]{figures/ha_schematic.png} + \caption{Schematic of Half Adder circuit} + \label{ha_schematic} +\end{figure} + +The KiCad netlist is generated as shown in \figref{ha_netlistgeneration}.\\ +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/ha_netlistgeneration.png} + \caption{Half Adder circuit Netlist Generation} + \label{ha_netlistgeneration} +\end{figure} + +\pagebreak + +\item Convert KiCad to Ngspice: +After creating KiCad netlist click on KiCad-Ngspice converter button.\\ + +This will open converter window where you can enter details of Analysis, Source values, Ngspice model and Subcircuit. + +\begin{figure}[!htp] + \centering + \subfloat[Half Adder Analysis]{ + \includegraphics[width=\smfig]{figures/ha_analysistab.png} + \label{ha_analysistab}} \hfill + \subfloat[Half Adder Source Details]{ + \includegraphics[width=\smfig]{figures/ha_sourcedetailstab.png} + \label{ha_sourcedetailstab}} \vfill + \subfloat[Half Adder Ngspice Model]{ + \includegraphics[width=\smfig]{figures/ha_ngspicemodeltab.png} + \label{ha_ngspicemodeltab}} \hfill + \subfloat[Half Adder Subcircuit Model]{ + \includegraphics[width=\smfig]{figures/ha_subcircuitstab.png} + \label{ha_subcircuitstab}} + \caption{Analysis, Source, Ngspice Model and Subcircuit tab} +\end{figure} + +Subcircuit of Half Adder in \figref{ha_sub} +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/ha_sub.png} + \caption{Half Adder Subcircuit} + \label{ha_sub} +\end{figure} + +\pagebreak + +\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. + \begin{figure}[!htp] + \centering + \subfloat[Half Adder Ngspice Plot]{ + \includegraphics[width=\lgfig]{figures/ha_ngspiceplot.png} + \label{ha_ngspiceplot}} \hfill + \subfloat[Half Adder Python Plot]{ + \includegraphics[width=\lgfig]{figures/ha_pythonplot.png} + \label{ha_pythonplot}} + \caption{Half Adder Simulation Output} +\end{figure} + +\end{itemize} + + +%-------------------------Full Wave Rectifier using SCR------------------------------------------ + + +\pagebreak + +\subsection{Full Wave Rectifier using SCR} + +\subsubsection{Problem Statement:} Plot the Input and Output Waveform of Full Wave Rectifier using SCR. + +\subsubsection{Solution:} + +\begin{itemize} + +\item Creating Schematic: To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ +After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the right toolbar which opens the component library.\\ +After all the required components of the Full Wave Rectifier using SCR circuit are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}.\\ +Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. + +The \figref{fwrscr_schematic} shows the complete Rectifier circuit using SCR after removing the errors. +\begin{figure}[!htp] + \centering + \includegraphics[width=\hgfig]{figures/fwrscr_schematic.png} + \caption{Schematic of Full Wave Rectifier using SCR} + \label{fwrscr_schematic} +\end{figure} + +The KiCad netlist is generated as shown in \figref{fwrscr_netlistgeneration}.\\ +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/fwrscr_netlistgeneration.png} + \caption{Full Wave Rectifier using SCR Netlist Generation} + \label{fwrscr_netlistgeneration} +\end{figure} + +\pagebreak + +\item Convert KiCad to Ngspice: +After creating KiCad netlist click on KiCad-Ngspice converter button.\\ + +This will open converter window where you can enter details of Analysis, Source values, Ngspice model and Subcircuit. + +\begin{figure}[!htp] + \centering + \subfloat[Full Wave Rectifier using SCR Analysis]{ + \includegraphics[width=\smfig]{figures/fwrscr_analysistab.png} + \label{fwrscr_analysistab}} \hfill + \subfloat[Full Wave Rectifier using SCR Source Details]{ + \includegraphics[width=\smfig]{figures/fwrscr_sourcedetailstab.png} + \label{fwrscr_sourcedetailstab}} \vfill + \subfloat[Full Wave Rectifier using SCR Subcircuit Model]{ + \includegraphics[width=\smfig]{figures/fwrscr_subcircuitstab.png} + \label{fwrscr_subcircuitstab}} + \caption{Analysis, Source and Subcircuit tab} +\end{figure} + +Subcircuit of SCR in \figref{scr_sub} +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/scr_sub.png} + \caption{SCR Subcircuit} + \label{scr_sub} +\end{figure} + +\pagebreak + +\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. + \begin{figure}[!htp] + \centering + \subfloat[Full Wave Rectifier using SCR Ngspice Plot]{ + \includegraphics[width=\lgfig]{figures/fwrscr_ngspiceplot.png} + \label{fwrscr_ngspiceplot}} \hfill + \subfloat[Full Wave Rectifier using SCR Python Plot]{ + \includegraphics[width=\lgfig]{figures/fwrscr_pythonplot.png} + \label{fwrscr_pythonplot}} + \caption{Full Wave Rectifier using SCR Simulation Output} +\end{figure} + +\end{itemize} + + +%-------------------------Oscillator------------------------------------------ +\pagebreak + +\subsection{Oscillator Circuit} + +\subsubsection{Problem Statement:} Plot the Oscillation Waveforms for Phase Shift Oscillator circuit. + +\subsubsection{Solution:} +The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given in the window shown in \figref{rc1}. + +\begin{itemize} +\item Creating Schematic: +To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ + +After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the +right toolbar which opens the component library.\\ + +After all the required components of the Oscillator circuits are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}\\sss + +Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. After completing all the above steps the Oscillator schematic will look like \figref{osc_schematic}.\\ + +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/osc_schematic.png} + \caption{Schematic of Phase Shift Oscillator circuit} + \label{osc_schematic} +\end{figure} + +\pagebreak + +KiCad netlist is generated as shown in the \figref{osc_netlistgeneration} \\ + +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/osc_netlistgeneration.png} + \caption{Phase Shift Oscillator circuit Netlist Generation} + \label{osc_netlistgeneration} +\end{figure} + +\item Convert KiCad to Ngspice: After creating KiCad netlist, click on the {\tt KiCad-Ngspice converter} button. This will open converter window where you can enter details of Analysis, Source values and Device library. + +\begin{figure}[!htp] + \centering + \subfloat[Phase Shift Oscillator Analysis]{ + \includegraphics[width=\smfig]{figures/osc_analysistab.png} + \label{osc_analysistab}} \hfill + \subfloat[Phase Shift Oscillator Details]{ + \includegraphics[width=\smfig]{figures/osc_sourcedetailstab.png} + \label{osc_sourcedetailstab}} \hfill + \subfloat[Phase Shift Oscillator Device Modeling]{ + \includegraphics[width=\smfig]{figures/osc_devicemodelingtab.png} + \label{osc_devicemodelingtab}} + \caption{Analysis, Source and Device Tab} +\end{figure} + +Under device library you can add the library for diode used in the circuit. If you do not add any library it will take default Ngspice model. + + +\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. +\begin{figure}[!htp] + \centering + \subfloat[Ngspice Plot of Phase Shift Oscillator]{ + \includegraphics[width=\lgfig]{figures/osc_ngspiceplot.png} + \label{osc_ngspiceplot}} \hfill + \subfloat[Python Plot of Phase Shift Oscillator]{ + \includegraphics[width=\lgfig]{figures/osc_pythonplot.png} + \label{osc_pythonplot}} + \caption{Phase Shift Oscillator Simulation Output} +\end{figure} + + +\end{itemize} + +%-------------------------BJT CB Characteristics------------------------------------------ + +\pagebreak + +\subsection{Characteristics of BJT in Common Base Configuration} + +\subsubsection{Problem Statement:} Plot Characteristics of BJT in Common Base Configuration. + +\subsubsection{Solution:} +The new project is created by clicking the {\tt New} icon on the menubar. The name of the project is given in the window shown in \figref{rc1}. + +\begin{itemize} +\item Creating Schematic: +To create the schematic, click the very first icon of the left toolbar as shown in the \figref{rc2}. This will open KiCad Eeschema.\\ + +After the KiCad window is opened, to create a schematic we need to place the required components. \figref{rc_component} shows the icon on the +right toolbar which opens the component library.\\ + +After all the required components of the simple Half Wave rectifier circuits are placed, wiring is done using the {\tt Place Wire} option as shown in the \figref{rc_wire}\\ + +Next step is {\tt ERC (Electric Rules Check)}. \figref{erc1} shows the icon for {\tt ERC}. After completing all the above steps the BJT in CB Configuration schematic will look like \figref{cb_schematic}.\\ + +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/cb_schematic.png} + \caption{Schematic of BJT in CB Configuration circuit} + \label{cb_schematic} +\end{figure} + +\pagebreak + +KiCad netlist is generated as shown in the \figref{cb_netlistgeneration} \\ + +\begin{figure}[!htp] + \centering + \includegraphics[width=\lgfig]{figures/cb_netlistgeneration.png} + \caption{BJT in CB Configuration circuit Netlist Generation} + \label{cb_netlistgeneration} +\end{figure} + +\item Convert KiCad to Ngspice: After creating KiCad netlist, click on the {\tt KiCad-Ngspice converter} button. This will open converter window where you can enter details of Analysis, Source values and Device library. + +\begin{figure}[!htp] + \centering + \subfloat[BJT in CB Configuration Analysis]{ + \includegraphics[width=\smfig]{figures/cb_analysistab.png} + \label{cb_analysistab}} \hfill + \subfloat[BJT in CB Configuration Source Details]{ + \includegraphics[width=\smfig]{figures/cb_sourcedetailstab.png} + \label{cb_sourcedetailstab}} \hfill + \subfloat[BJT in CB Configuration Device Modeling]{ + \includegraphics[width=\smfig]{figures/cb_devicemodelingtab.png} + \label{cb_devicemodelingtab}} + \caption{Analysis, Source and Device Tab} +\end{figure} + +Under device library you can add the library for diode used in the circuit. If you do not add any library it will take default Ngspice model. + + +\item Simulation: Once the KiCad-Ngspice converter runs successfully, you can run simulation by clicking the simulation button in the toolbar. +\begin{figure}[!htp] + \centering + \subfloat[Ngspice Plot of BJT in CB Configuration]{ + \includegraphics[width=\lgfig]{figures/cb_ngspiceplot.png} + \label{cb_ngspiceplot}} \hfill + \subfloat[Python Plot of BJT in CB Configuration]{ + \includegraphics[width=\lgfig]{figures/cb_pythonplot.png} + \label{cb_pythonplot}} + \caption{BJT in CB Configuration Simulation Output} +\end{figure} + + +\end{itemize} diff --git a/chap_14.tex b/chap_14.tex new file mode 100644 index 00000000..6418e832 --- /dev/null +++ b/chap_14.tex @@ -0,0 +1,416 @@ +\chapter{PCB Design} +\thispagestyle{empty} +\label{chap13} + +Printed Circuit Board (PCB) \index{PCB} design is an important +step in electronic system design. Every component of the circuit +needs to be placed and connections routed to minimise delay and +area. Each component has an associated footprint. Footprint refers to +the physical layout of a component that is required to mount it on the +PCB. PCB design involves associating footprints to all components, placing them appropriately to +minimise wire length and area, connecting the footprints using +tracks or vias and finally extracting the required files needed for +printing the PCB. Let us see the steps to design PCB using eSim. + +\section{Schematic creation for PCB design} +In \chapref{chap5}, we have seen the differences between schematic for +simulation and schematic for PCB design. Let us design a PCB Layout for a 'constant 5V DC supply' circuit named as \texttt{7805VoltageRegulator}. First, we will simulate the circuit. Refer to \figref{pcbschfin} for the schematic used for simulation. After satisfying simulation results, we will move to PCB design. For this, we will remove the Source(s), Probes (plot\_v , plot\_db etc.), and global labels connected \texttt{solely} for the purpose of viewing simulation plots conveniently. \\ Connectors are the physical components that are used to interface/connect the board to external peripherals or sources. + +\begin{figure} +\centering +\includegraphics[width=\lgfig]{NGHDL/pcbschinitial.png} +\caption{Schematic for simulation of the constant 5V DC supply circuit} +\label{pcbschfin} +\end{figure} + +%Create the circuit schematic as shown in \figref{pcbschfin}. The two pin female +%connector (\textt{Conn\_01x02\_Female}) can be placed from the Eeschema's \textt {Conn} library. Do the annotation and +%test for ERC. Refer to \chapref{chap5} to know more about +%basic steps in schematic creation. + + +\subsection{Removing components required for simulation from the schematic} +\begin{itemize} +\item We will remove the components which were placed for simulation purpose only. +\item Components that will be placed on the board need to be added in the schematic. +\item Modify the circuit schematic as shown in \figref{pcbschconn}. The two pin female connector (\texttt{Conn\_01x02\_Female}) is placed for the taking the 5V output supply meanwhile a 2 pin Screw Terminal (\texttt{Screw\_Terminal\_01x02}) is used to transmit the input signal on board. Do the annotation and test for ERC. Refer to \chapref{chap5} to know more about basic steps in schematic creation. + +\begin{figure} +\centering +\includegraphics[width=\lgfig]{NGHDL/pcbschwithconn.png} +\caption{Schematic after adding connectors and removing the probes and sources.} +\label{pcbschconn} +\end{figure} +\end{itemize} + +\subsection{Mapping of components using Cvpcb} +%\index{Footprints!mapping} \index{Footprint Editor} +\index{Component!footprint!mapping} +\begin{itemize} + +\item Once the schematic for PCB Design is created, one needs to map each component +in the schematic to the appropriate footprint. The tool \texttt{Cvpcb} is +used for this. +\item Cvpcb can be launched by clicking the icon \texttt{Run Cvpcb to associate footprints and components} in Eeschema or by going under the \texttt{Tools} menu and selecting \texttt{Assign Component Footprint} option. +\end{itemize} + +\subsection{Familiarising with Cvpcb Window} +\index{Cvpcb} +\begin{itemize} +\item I. When one opens \texttt{Cvpcb} after annotating and running ERC on the schematic intended for PCB Design a window as shown in \figref{cvpcb} will be obtained. The Toolbar for using Cvpcb will be available in the top-most left corner. +\begin{figure} +\centering +\includegraphics[width=\lgfig]{NGHDL/cvpcb_unassigned.png} +\caption{Cvpcb window} +\label{cvpcb} +\end{figure} +\item II. The left pane has a list of all footprint libraries in the database. +\item III. The middle pane displays the list of components present in the schematic and if any footprint is assigned/associated to them. +\item IV. The right pane has a list of available footprints for each component depending upon how of libraries. +\end{itemize} + + + +\subsubsection{ Cvpcb Toolbar} +Some of the important tools in the toolbar are shown in +\figref{tb_fe}. They are explained below (Order of operation should ideally be from RIGHT to LEFT): +\begin{figure} +\centering +\includegraphics[width=\hgfig]{tb_fe.png} +\caption{Cvpcb Toolbar} +\label{tb_fe} +\end{figure} +\begin{compactenum} +\item Filter footprints list by library : We recommend the use of only this as a filtering method if you are completely new to eSim and/or PCB Design as it narrows down footprints based on libraries of the type of the component. When a filter is selected, it's icon will be highlighted in light red color as seen in \figref{tb_fe}. +\item Filter footprints list by pin count : This will filter the footprints based on number of pins the footprint has. This can be used to narrow down your search after sorting footprints by their library type. +\item Filter footprints list by keyword - This filters the footprints in the database based on keywords. +\item Automatic footprint association - Perform footprint association + for each component automatically. Footprints will be selected from + the list of footprints available.\\ + Note: This method of association is not recommended at all. +\item Delete all associations - Delete all the footprint associations made. This will erase all your association till now so be very careful in selecting this. + \item Select next unlinked component: Using this you can go to the next component in the list of components for associating a footprint. + \item Select previous unlinked component: Using this you can go to the previous component in the list of components for associating a footprint. +\item View selected footprint - View the selected footprint in 2D. See \secref{viewfp} for more details. \\ + Before clicking on this, make sure that a footprint is selected. Order of this operation should be + \\ 1. Selection of footprint library from the left-most pane + \\ 2. Selecting a footprint from the right-most pane + \\ 3. Click on \texttt{View selected footprint} +\item Edit footprint library table - One should familiarize themselves with Cvpcb first and then only choose to use this. This impacts the footprints that you can choose, so be careful before making any severe changes. +\item Save netlist and footprint files - Save the netlist and the + footprints that are associated with it. One ought to save the association after having assigned proper footprints to all the components. +\end{compactenum} + +\subsection{Viewing footprints in 2D and 3D} +\index{Footprints!view!2D} +\index{Footprints!view!3D} +\label{viewfp} + +\begin{itemize} + +\item To view a footprint in 2D, select the component for which you wish to view the available footprints, then select the library from left-most pane and now from the right pane and click on the desired footprint and click on \texttt{View selected footprint} from the menu bar. +Let us view a footprint for \texttt{C1} from the \texttt{Capacitors\_THT} footprint library. Choose C1 from the middle pane as shown, click on \texttt{Capacitors\_THT} in the left-most pane and select the +\textit{View selected footprint} tool. +On clicking the \textbf{View selected footprint} tool, the {\tt Footprint} window with the view in 2D will be displayed. 2D view of the footprint \texttt{CP\_Radial\_D5.0mm\_P2.50mm} is shown in \figref{2dview}. + +\begin{figure} +\centering +\includegraphics[width=\lgfig]{smnew.png} +\caption{Viewing footprint for C1} +\label{sm} +\end{figure} + +\item Click on the \texttt{3D Display} icon in the {\tt Footprint} +window, as shown in \figref{2dview}. A top view of the selected footprint +in 3D is obtained. Click on the footprint and rotate it using the computer mouse to +get 3D views from various angles. One such view of the footprint +in 3D is shown in \figref{3dv}. + +\end{itemize} + +\begin{figure} +\centering +\includegraphics[width=\lgfig]{manual_images/2dviewofcp.png} +\caption{Footprint \texttt{CP\_Radial\_D5.0mm\_P2.50mm}'s view in 2D.} +\label{2dview} +\end{figure} +\begin{figure} +\centering +\includegraphics[width=\lgfig]{manual_images/3dv.png} +\caption{3D view of the footprint} +\label{3dv} +\end{figure} + +\subsection{Mapping of components in the circuit} + +\begin{compactenum} +\item Click on {\tt C1} from the middle pane. Choose the footprint library \textit{Capacitors\_THT} +from the left pane and locate the footprint \linebreak \texttt{CP\_Radial\_D5.0mm\_P2.50mm}. By double clicking on it, the said footprint will be assigned to {\tt C1}. +\item Similarly choose the footprints per \figref{map} where the footprint association for all the footprints is shown in \figref{map}. Save the footprint association by clicking on the +\texttt{Save footprint association in schematic component footprint fields} tool from the {\tt CvPcb toolbar}. +\end{compactenum} + + +\begin{figure} +\centering +\includegraphics[width=0.85\linewidth]{manual_images/map.png} +\caption{Footprint mapping completed for the circuit} +\label{map} +\end{figure}. + +\subsection{Netlist generation for PCB} +\index{Netlist!for PCB} \index{Netlist} +\label{netc} +\begin{figure} +\centering +\includegraphics[width=\lgfig]{manual_images/netlistpcb.png} +\caption{Netlist generation for PCB} +\label{netlistpcb} +\end{figure} + +\begin{compactenum} +\item After having saved your footprint association, switch back to the Eeschema window and press Ctrl+S. +\item The netlist for PCB is different from that for simulation. To generate +netlist for PCB, click on the \textit{Generate netlist} tool from the +top toolbar in Schematic editor. +\item In the \texttt{Netlist} window, under the tab \textit{Pcbnew}, Select the option \texttt{Default format}. This is shown in \figref{netlistpcb}. Click on \texttt{Generate} option. +\item Click on \texttt{Save} in the Save netlist file dialog box that opens up. Do not change the directory or the name of the netlist file. \texttt{Note that the netlist for PCB has an extension \emph{.net}. The netlist created for simulation has an extension \emph .cir}. +\end{compactenum} + + + +\section{Creation of PCB layout} +\index{PCB Layout!creation} \index{Layout Editor} + +The next step is to place the footprints and lay tracks between them +to get the layout. This is done using the \textit{Layout Editor} +tool. eSim uses {\tt Pcbnew}, the layout creation tool in KiCad, as +its layout editor. + +\subsection{Launching Pcbnew} +\begin{compactenum} +\item To Launch the layout editor, \texttt{Pcbnew}, click on the \texttt{Run Pcbnew to layout printed circuit board} icon on the top right corner of the Schematic window. +\item Similarly, you can also click on \texttt{Tools}, and select the \texttt{Layout printed circuit board} option. +\item After doing either of the steps above, click \textbf{yes} on the \textit{Confirmation Box} that will appear on the screen. +\end{compactenum} + +\subsection{Familiarizing the Layout Editor tool} +\index{Layout Editor} + +The layout editor with the various menu bar and toolbars is shown in +\figref{pcbnew}. +\begin{figure} +\centering +\includegraphics[width=0.68\linewidth]{NGHDL/toptble.png} +\caption{Layout editor with menu bar, toolbars and layer options} +\label{pcbnew} +\end{figure} + + +\subsubsection{Top toolbar} +Some of the important menu options in the top menu bar are shown in +\figref{pcbnew}. They are explained below: +\begin{compactenum} +\item Save board - Save the printed circuit board +%\item Module editor - Open module editor to edit footprint modules or + % libraries + \item Plot - This enables users to import their design in Gerber, PDF, SVG and few more formats depending on the requirement. +\item Read netlist - Import the netlist whose layout needs to be + created. +\item Perform design rules check - Check for design rules, unconnected + nets, etc., in the layout. +\item Select working layer - Selection of working layer.\\ +Note: Selection of working layer can also be done from the \texttt{Layers toolbar} on the right-most side of the Pcbnew tool window. +\end{compactenum} + +\subsection{Hotkeys} +\index{Hotkeys!Layout editor} +A list of few important hotkeys is given below: +\begin{compactenum} +\item F1 - Zoom in +\item F2 - Zoom out +\item Delete - Delete Track or Footprint +\item X - Add new track +\item V - Add Via +\item M - Move Item +\item F - Flip Footprint +\item R - Rotate Item +\item G - Drag Footprint +\item Ctrl+Z - Undo +\item E - Edit Item +\end{compactenum} +The entire list of Hotkeys can be viewed by selecting \textit{Preferences} from the top +menu bar and choosing \textit{List Current Keys} from the option \textit{Hotkeys}. +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{manual_images/hotkeys.png} +\caption{Default Hotkeys} +\label{netlisttop} +\end{figure} +%[width=0.5\textwidth] + +\subsection{Designing PCB layout for 7805VoltageRegulator circuit} \index{PCB design} +Click on \textit{Read Netlist} tool from the top toolbar of Pcbnew. Click on +\textit{Browse Netlist files} on the Netlist window that opens +up. Select the {\tt .net} file that was modified \\\texttt{after} +assigning footprints. Click on \textit{Open}. Now Click on +\textit{Read Current Netlist} on the Netlist window. The +sequence of operations is shown in \figref{brnet}. +\index{PCB design!move modules} \index{PCB design!lay tracks} + +\begin{figure} +\centering +\includegraphics[width=0.67\linewidth]{manual_images/readnetlist.png} +\includegraphics[width=0.67\textwidth]{manual_images/browsenetlistforpcb.png} +\caption{Importing netlist file to layout editor: 1. Browse netlist + Files, 2. Choose the appropriate .net file, 3. Read Netlist file, 4. Close} +\label{brnet} +\end{figure} + +\subsubsection{Arranging the footprints} +\begin{compactenum} +\item After clicking on Read Netlist button and closing the Read Netlist window, the footprints that we assigned will appear on the Pcbnew screen in a cluttered fashion, stacked on top of each other as shown in \figref{cluttered} +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{cluterredFPs.png} +\caption{Cluttered footprints} +\label{cluttered} +\end{figure} + +\item Let us separate these footprints and place them in proper orientation per the requirement of the circuit. Let us start with Screw\_Terminal\_01x02 footprint. +\item Right Click on the text \texttt{Screw\_Terminal\_01x02} in the Pcbnew window, and select \texttt{Footprint J1 on F.Cu.} and select the \texttt{Move} option from the list. +\item The footprint will be glued to the cursor and it can be placed in the location of one's choice by moving the cursor at the desired location and clicking once to place it there. +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{FPMove.png} +\caption{Moving the footprint} +\label{movingFP} +\end{figure} +\item We have moved the Screw\_Terminal\_01x02 footprint to the left side of the Pcbnew window. +\item Once again right click on the text \texttt{Screw\_Terminal\_01x02} in the Pcbnew window, and select \texttt{Footprint J1 on F.Cu.} and select the \texttt{Rotate +} option from the list as shown in \figref{rotateFP} +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{rotatefp.png} +\caption{Rotating the footprint} +\label{rotateFP} +\end{figure} +\item Using similar methods, we have moved and rotated all other footprints as shown in \figref{rotateall} + +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{fpsmovedandrotated.png} +\caption{All footprints moved and rotated} +\label{rotateall} +\end{figure} +\end{compactenum} + +\subsubsection{Setting Design Rules} + +\begin{compactenum} +\item Click on \texttt{Design Rules on top of the Pcbnew window, select Design Rules option from the drop down menu there.} +\item \texttt{Design Rules Editor} window will open, Under the \texttt{Net Classes Editor}, locate the \texttt{Track Width} box, erase the default value from the window placed under the \texttt{Track Width} box and enter 1.25 as the track width. +\item Click on \texttt{Global Design Rules}, under Minimum Allowed Values, locate \texttt{Min track width}, erase the default value and enter 1.25 in the data entry field on the right side of it as shown in \figref{DRC_GDR}. This will ensure that all tracks placed are of width 1.25mm and that when we perform Design Rules Check, the checks will be made such that all tracks are of the width 1.25mm will be checked. +\item Click on Ok button and close the Design Editor Rules window. +\end{compactenum} + +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{druleseditor.png} +\caption{Design Rules Editor Window: Global Design Rules} +\label{DRC_GDR} +\end{figure} + +\subsubsection{Drawing the Board Outline} +\begin{compactenum} +\item Board outline defines the physical dimensions of your board. After the fabricator is done placing tracks and other processes, he/she will cut your design from the copper cladded sheet or the material used per your choice, as per your board outline dimensions. Say, if your board outline is of rectangular shape with dimensions 80mmx50mm, the fabricator will cut the copper sheet of the said dimension. Its important to know that all the tracks(physical electrically conductive connections between two nodes or points on a PCB) must lie inside this board outline. +\item We will also choose a board outline of rectangular shape. Select working layer as \texttt{Edge.Cuts} from the Layers menu on the far-right side of Pcbnew. +\item Click on \texttt{Place} from the top-left tool bar of the Pcbnew window and select \texttt{Line or Polygon}. A pencil icon will appear to be tied to the cursor. +\item Click once on the layout editor to start drawing the outline. Drag the cursor either horizontally or vertically. When it comes to the corner of the board, click once and drag the cursor in perpendicular direction. Do this till you reach the origin of the outline, and double click to finish drawing the rectangular outline. Completed outline is as shown in \figref{brdoutline}. +\end{compactenum} + +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{boardoutline.png} +\caption{Drawing a board outline} +\label{brdoutline} +\end{figure} + +\subsubsection{Placing Tracks} +\begin{compactenum} +\item Select the working layer as B.Cu from the Layers menu on the far-right side of Pcbnew. +\item Click on \texttt{Place} from the top-left tool bar of the Pcbnew window and select \texttt{Track}. A pencil icon will appear to be tied to the cursor. +\item The procedure to place a track between Node 2 of Screw\_Terminal\_01x02 to Node 1 of D3 diode, as shown in \figref{brdoutline} is described in below steps. +\item Working layer is B.Cu., \texttt{Place Track tool} is selected earlier. Click the pencil icon tied to cursor on the Node 2 of Screw\_Terminal\_01x02 and drag the cursor till Node 1 of D3 diode and double click on Node 2 of D3. By double clicking the track will end at Node 2 of D3. Please refer \figref{D3node1track} for the mentioned track being placed. +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{firsttrack.png} +\caption{Track placed on B.Cu. between Screw\_Terminal\_01x02 connector and D3 Diode} +\label{D3node1track} +\end{figure} +\item Similarly, all the tracks have been placed as shown in \figref{alltracks}. Please note that tracks shown in green color are on B.Cu. layer whereas the tracks in red color are placed on the F.Cu. layer. +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{alltracks.png} +\caption{All tracks placed} +\label{alltracks} +\end{figure} +\end{compactenum} + +\subsubsection{Performing Design Rules Check(DRC)} +\begin{compactenum} +\item After tracks are placed, it is important that the design created by used should not violate any design rules set earlier. +\item Click on \texttt{Perform Design Rules check} button from the top menu bar of Pcbnew. DRC Control Window will pop-up as shown in \figref{DRC}. +\item Click on \texttt{Start DRC}, and observe if any messages/warnings appear in the \texttt{error messages} window at the bottom of the DRC Control window. If there are no errors in the design present, there will not be any errors in the message window as shown in \figref{DRC} +\end{compactenum} + +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{drc1.png} +\caption{DRC Control Window} +\label{DRC} +\end{figure} + +\subsubsection{Exporting the Design to Gerber format} +\begin{compactenum} +\item Click on \texttt{Plot} tool from the top toolbar, select the Plot Format as \texttt{gerber} from the drop down menu of Plot Format. +\item Select the directory in which the user wishes to save the gerber files. +\item Select F.Cu, B.Cu, B.Silks, F.Mask, B.Mask, Margin and Edge.Cuts from the \textit{Layers} on the left side of the Plot window as shown in \figref{plotbef}. +\item After clicking on 'Plot' button, acknowledgment messages can be seen in the 'Messages' window at the bottom of the \texttt{Plot} tool window as shown in \figref{plotaf}. +\end{compactenum} + + +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{plotwindowbefore.png} +\caption{Plot Window before generating gerber files} +\label{plotbef} +\end{figure} + +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{plotafter.png} +\caption{Plot window after generating gerber files} +\label{plotaf} +\end{figure} + +\subsubsection{Viewing the Gerber files generated} +\begin{compactenum} +\item Open the terminal by Ctrl+Alt+T keys, and type \texttt{gerbview} and press enter. Gerbview tool of KiCad will open up. For windows OS users, search for \texttt{gerbview} application through Windows' search application option. +\item Click on File from top-left menu, and select Load Gerber File option. +\item Go to the directory where you have stored the earlier created gerber files as shown in \figref{gerbviewloading} and click on Open. +\item The design created earlier will appear in the gerbview window as shown in \figref{gerbviewcapture}. +\end{compactenum} + +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{gerbviewloading.png} +\caption{Loading gerber files in the gerbview} +\label{gerbviewloading} +\end{figure} + +\begin{figure} +\centering +\includegraphics[height=0.4\textwidth]{gerbviewcapture.png} +\caption{Observing the design in Gerber format} +\label{gerbviewcapture} +\end{figure}
\ No newline at end of file @@ -1,192 +1,110 @@ -\chapter{NGHDL: Mixed Signal Simulation} +\chapter{SKY130 Interface with eSim} \label{chap9} \thispagestyle{empty} +SkyWater Open Source PDK provides a completely open source Process Design Kit for the 130nm Technology Node. SKY130 PDK provides a lot many features and components to its library. The MPW Shuttle is a free chip fabrication shuttle program sponsored by the Google where the designs made using the SKY130 PDK may be fabricated at no cost. -NGHDL feature facilitates creation of user-defined models for mixed-signal circuit simulation in eSim. By interfacing GHDL and Ngspice, we achieve mixed-signal simulation. Digital models are simulated using GHDL and XSPICE engine of Ngspice. \\ +eSim being an Open Source EDA Tool has being interfaced with the SKY130 PDK. eSim-2.3 and above is supporting the PDK. Currently only the primitive libraries(sky130\_fd\_pr) are supported, however, the symbols for other libraries are also loaded in eSim, so even the other ones can be interfaced with eSim with few manual changes. +The various steps involved in simulating a circuit schematic in eSim interfaced with SKY130 are explained in the sections below: +\section {Schematic Creation} +\begin{itemize} -%To access NGHDL click on the NGHDL button on the left pane of window as shown in figure \figref{screen3}: -%\pagebreak +\item The steps of opening the Eeschema and editing are same as mentioned in the previous Chapters. +\item To create a Schematic in eSim for SKY130, one needs to use the SKY130 components. +\item The SKY130 components are available in the \textbf{eSim\_SKY130} library. It can be chosen by clicking on the \textbf{Place Component} button on the Right Toolbar and searching for the same in the \textbf{Choose Component} Dialog Box. -\section{Introduction} - -Ngspice supports mixed-signal simulation, i.e. it can simulate both digital and analog component. It defines a \texttt{model} which has the functionality of the circuit component, which can be used in the netlist. -For example you can create an \texttt{adder} model in Ngspice and use it in any circuit netlist of Ngspice. \\ - -However, it is not feasible to define complex digital models without a complete understanding of Ngspice and XSPICE architectures and is a time-consuming process. Also, most of the users are familiar with GHDL and can write the models using VHDL code with ease. -Hence, NGHDL provides an interface to write VHDL code for a digital model and install it as model in Ngspice. So whenever Ngspice looks for that model, it will actually interface with VHDL code to get the result. \\ - -\begin{figure}[!htp] +\begin{figure}[H] \centering -\includegraphics[width = 13cm, height = 7cm]{./NGHDL/NGHDL_Overview.png} -\caption{Overview of NGHDL} -\label{overview} +\includegraphics[ height = 5cm]{./SKY130/SKY130libraries.png} +\caption{eSim\_SKY130 Libraries} +\label{eSimSKY130 Libraries} \end{figure} -%description of Overview: -\figref{overview} shows the overview of NGHDL indicating its architecture at the abstract level. The values for the digital models present in the netlist are fetched from the GHDL side of the interface whereas the values of the analog part are fetched from Ngspice's spice3f5 engine. Digital and Analog components in \figref{overview} are connected to each other with the help of the hybrid ADC and DAC models provided by Ngspice. This helps in the signal level switching when simulation is performed. As analog signals are in continuous time domain and Digital signals are in discrete time domain, hybrid components help bridge the gap. More information on the parameters of ADC and DAC present in Appendix : D. - -\pagebreak - -\section{Digital Model creation using NGHDL} +\item One may even chose the predefined IPs made in SKY130 available in eSim. These IPs are available in the \textbf{eSim\_SKY130\_Subckts} library. It can be chosen by clicking on the \textbf{Place Component} button on the right Toolbar and searching for the same. -%Description of User Flow of NGHDL - -\begin{figure}[!htp] +\begin{figure}[H] \centering -\includegraphics[width = 13cm, height = 7cm]{./NGHDL/NGHDL_Flow.png} -\caption{User Flow for NGHDL} -\label{user_flow} +\includegraphics[ height = 5cm]{./SKY130/SKY130subcktlibraries.png} +\caption{eSim\_SKY130\_Subckts IP Libraries} +\label{eSimSKY130Subckts IP Libraries} \end{figure} - -\noindent \textbf{The steps to create digital models are given below}: - -\begin{enumerate} -\item Click on NGHDL button on left side pane of main window, the Ngspice Digital Model Creator window will appear as shown in \figref{screen3} - \begin{figure}[!htp] - \centering - \includegraphics[height=10cm, width =\lgfig]{./NGHDL/screen3.png} - \caption{NGHDL interface} - \label{screen3} - \end{figure} - - -\item Now browse and locate the VHDL file to upload. Select the VHDL file and click on the Upload button. This process will create Ngspice model and corresponding component drawing inside the KiCad library (eSim\_Nghdl.lib) of the VHDL block to be used in mixed-signal simulations. An acknowledgement message will appear upon sucessful processing of the VHDL code as shown in \figref{upload}. \\ - - \begin{figure}[!htp] - \centering - \includegraphics[width =\smfig]{./NGHDL/screen4.png} - \caption{Uploading of digital model} - \label{upload} - \end{figure} - -Note : \texttt{"Add files"} option allow you to use a smaller entity / subpart / submodule to support the main VHDL file. That is, a digital model will be generated corresponding to that file that has been browsed. The file that has been \texttt{"added"} to Nghdl upload window will only be placed along with the model under model’s DUTghdl folder to support the model. - -Hence, \texttt{"browsing"} one file and \texttt{"adding"} several files won’t create that many number of models, but only one model will be created corresponding to the browsed file. -\end{enumerate} - -\section{Schematic Creation} -Steps for schematic creation are as follows: -\begin{enumerate} -\item Click on New Project icon to create a new project as shown in \figref{screen1}, be careful of the naming conventions. -%To access nghdl click on the NGHDL button on the left pane of window as shown in figure \figref{screen3}: - -\begin{figure}[!htp] +\item \textbf{It is important to choose the SKY130mode from the eSim\_SKY130 to switch eSim into the SKY130 mode.} +\begin{figure}[H] \centering -\includegraphics[width = 13cm, height = 7cm]{./NGHDL/screen1.png} -\caption{Creation of a new project} -\label{screen1} +\includegraphics[ height = 5cm]{./SKY130/SKY130Mode.png} +\caption{SKY130Mode} +\label{SKY130Mode} \end{figure} +\item Let us look into the CMOS Inverter as an example. Here is an example schematic of a CMOS Inverter made from the SKY130 components: +\begin{figure}[H] +\centering +\includegraphics[ height = 8cm]{./SKY130/SKY130InverterSchematic.png} +\caption{CMOS Inverter Schematic using SKY130 components} +\label{eSimSKY130Subckts IP Libraries} +\end{figure} +\item Note: While using SKY130mode in eSim, use the components of designators `sc', `u', `x', `v', `i', `a'. This is to ensure that other necessary technology node does not get included while in the SKY130 mode. +\item Annotate the schematic and generate the netlist. Please follow the steps given in previous chapters to do the same. -\item After successful upload of the model using the VHDL code, you can create the schematic of your design by clicking on \texttt{Open Schematic} button on the left pane of the eSim window. Then go to \texttt{Preferences} option on top of the schematic editor window and click on \texttt{Component Libraries} to add the library eSim\_Nghdl.lib in KiCad. Following window will appear as shown in \figref{screen6}, where you will have to click on \textit {Add} button and select the \texttt{eSim\_Nghdl} library. Refer \figref{screen6} and \figref{screen7}. %%last sentence may not be required - - \begin{figure}[!htp] - \centering - \includegraphics[width =\smfig]{./NGHDL/screen6.png} - \caption{Adding the digital model library in KiCad} - \label{screen6} - \end{figure} - - - \begin{figure}[!htp] - \centering - \includegraphics[width =\smfig]{./NGHDL/screen7.png} - \caption{Selection of library} %%this may not be required either - \label{screen7} - \end{figure} - - - - \pagebreak - \item Next step is to locate the component in \texttt{eSim\_Nghdl} library as shown in \figref{screen9} and place it on the schematic editor as shown in \figref{screen10}. - \begin{figure}[!htp] - \centering - \includegraphics[width =\smfig]{./NGHDL/screen9.png} %%Change this image - \caption{Locating the component in library} - \label{screen9} - \end{figure} - - - \begin{figure}[!htp] - \centering - \includegraphics[width =\smfig]{./NGHDL/screen10.png} - \caption{Placement of component on editor} - \label{screen10} - \end{figure} -\pagebreak - -\item Now create the schematic as shown in \figref{screen14}, annotate, perform ERC, create the netlist and save the schematic by following the steps given in Chapter 5. -\begin{figure}[!htp] - \centering - \includegraphics[width =\hgfig]{./NGHDL/screen14.png} - \caption{Example of an AND gate characteristics circuit} - \label{screen14} - \end{figure} - -\item After creating the schematic, click on \texttt{KiCad-to-Ngspice converter} and select the type of analysis as transient as shown in \figref{screen15} and set the start, step and stop time as shown in \figref{screen16} - \begin{figure}[!htp] - \centering - \includegraphics[width =\hgfig]{./NGHDL/screen15.png} - \caption{Analysis Part I} - \label{screen15} - \end{figure} - \begin{figure}[!htp] - \centering - \includegraphics[width =\hgfig]{./NGHDL/screen16.png} - \caption{Analysis Part II} - \label{screen16} - \end{figure} -\pagebreak - -\item Now click on \texttt{Source Details} and enter the values for Source v1 and source v2 as shown in figure \figref{val1} and \figref{val2} -\begin{figure}[!htp] - \centering - \includegraphics[width =\hgfig]{./NGHDL/val1.png} - \caption{Value of Source v1} - \label{val1} - \end{figure} - \begin{figure}[!htp] - \centering - \includegraphics[width =\hgfig]{./NGHDL/val2.png} - \caption{Value of Source v2} - \label{val2} - \end{figure} +\end{itemize} -\item Now select the option \texttt{Ngspice Model}, window as shown in \figref{screen17} will appear. The values of the parameters listed can be changed per user's requirement. If you have used any semicnductor devices and Subcircuits in your design, then please specify the Spice models and subcircuits in the \texttt{Device Modeling} and \texttt{Subcircuits} tabs of the \texttt{KiCad-to-Ngspice converter} window. After that click on \texttt{Convert} button. This step will create the simulation compatible netlist. - \begin{figure}[!htp] - \centering - \includegraphics[width =\hgfig]{./NGHDL/screen17.png} %Change the figure - \caption{Model Parameters} - \label{screen17} - \end{figure} -\item Now click on \texttt{Simulation} button, it will display the following windows as shown in \figref{screen19}. This is the Ngspice terminal and Python plot window. -\begin{figure}[!htp] - \centering - \includegraphics[width =\hgfig]{./NGHDL/screen19.png} - \caption{Simulation window} - \label{screen19} - \end{figure} -\pagebreak -\item Now select the required nodes and click on \texttt {Plot} button. You can see the plots of input source v1, input source v2 and output as shown in \figref{plotv1}, \figref{plotv2}, and \figref{plotout} respectively. -\begin{figure}[!htp] - \centering - \includegraphics[width =\lgfig]{./NGHDL/plotv1.png} - \caption{Plot of Source V1} - \label{plotv1} - \end{figure} -\begin{figure}[!htp] - \centering - \includegraphics[width =\lgfig]{./NGHDL/plotv2.png} - \caption{Plot of source V2} - \label{plotv2} - \end{figure} -\begin{figure}[!htp] - \centering - \includegraphics[width =\lgfig]{./NGHDL/plotout.png} - \caption{Plot of output} - \label{plotout} - \end{figure} + \section {KiCad to Ngspice Conversion} - \pagebreak +\begin{itemize} +\item Click on the \textbf{Convert KiCad to Ngspice Button} available in the Left Toolbar of the eSim Main Window. +\item Add all the simulation parameters and the Source details in the \textbf{Analysis Tab} and the \textbf{Source Details Tab}. Refer previous chapters of this manual to do the same. +\item Click on the \textbf{Device Modeling Tab}. +\item The options for the SKY130 PDK are involved in the \textbf{Device Model Tab}. The Device Model Tab for the CMOS Inverter project is shown in Fig. \ref{DeviceModelTab}. +\begin{figure}[H] +\centering +\includegraphics[ height = 5cm]{./SKY130/DeviceModelTab.png} +\caption{Device Model Tab of CMOS Inverter using SKY130} +\label{DeviceModelTab} +\end{figure} +\item The user may select the \textbf{Add Default Path} option to add the Default Path of the PDK installed along with eSim. Note that only primitive libraries(sky130\_fd\_pr) are present here. +\item In order to select path to any other SKY130 PDK, the user may add the path by clicking on the \textbf{Add} button. +\item The user can add the SPICE model parameters for the components in the text-box provided. +\item If a SKY130 Subcircuit IP is added in the circuit. Then Click on the \textbf{Subcircuits Tab}. For Example, refer Fig.\ref{Subcircuits Tab}. +\begin{figure}[H] +\centering +\includegraphics[ height = 7cm]{./SKY130/Subcircuits.png} +\caption{Subcircuits Tab} +\label{Subcircuits Tab} +\end{figure} +\item Click on the \textbf{Add} button. +\item Browse to the SKY130 folder and Click on it. Click the IP Subcircuit to be included. Click on the Open Button on the top right corner. +\begin{figure}[H] +\centering +\includegraphics[ height = 6cm]{./SKY130/SubcircuitsPath.png} +\caption{Adding path to the Subcircuit} +\label{SubcircuitsPath} +\end{figure} +\item The Subcircuit chosen gets added. Refer Fig. \ref{SubcircuitsAdded}. +\begin{figure}[H] +\centering +\includegraphics[ height = 6cm]{./SKY130/Subcircuitsadded.png} +\caption{Subcircuit Added} +\label{SubcircuitsAdded} +\end{figure} +\item Click on the \textbf{Convert} button. +\item A Dialog Box \textbf{The KiCad to Ngspice conversion completed successfully!} appears on the screen showing that the conversion is successful. +\item If something needs to be added manually, Click on the \textbf{ \textit{Project\_Name}.cir.out} file in the left \textbf{Project Panel} and the file can be edited manually. Refer Fig. \ref{netlist} as an example. +\begin{figure}[H] +\centering +\includegraphics[ height = 6cm]{./SKY130/netlist.png} +\caption{Manually Editing the Netlist} +\label{netlist} +\end{figure} +\end{itemize} -\end{enumerate}
\ No newline at end of file +\section {Run Simulation} +\begin{itemize} +\item To run the simulation, Click on the \textbf{Simulate} button on the Left Toolbar. +\item Refer Fig. \ref{Simulation Results} for the simulation results of the CMOS Inverter using SKY130. +\begin{figure}[H] +\centering +\includegraphics[ height = 6cm]{./SKY130/Simulation.png} +\caption{Simulation Results of CMOS Inverter using SKY130} +\label{Simulation Results} +\end{figure} +\end{itemize} +In this way, the SKY130 PDK has been interfaced with eSim. |
