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authorfahimkhan2016-03-14 16:37:03 +0530
committerfahimkhan2016-03-14 16:37:03 +0530
commit0767e64446641553c7c08c77b53d4817599c4ae1 (patch)
treeccc60cf033e7d1f56fe52633462c9e659de8af1d /Integrator/scr.sub~
parent9182fa7645ca28bd5d2d8401c2e2f03c39943f92 (diff)
downloadeSim-Examples-0767e64446641553c7c08c77b53d4817599c4ae1.tar.gz
eSim-Examples-0767e64446641553c7c08c77b53d4817599c4ae1.tar.bz2
eSim-Examples-0767e64446641553c7c08c77b53d4817599c4ae1.zip
Adding all available eSim examples
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+* Subcircuit scr
+.subckt scr 3 7 1
+* /opt/esim/src/subcircuitlibrary/scr/scr.cir
+.include PowerDiode.lib
+* f2
+d1 5 2 PowerDiode
+c1 3 9 10u
+* f1
+v1 8 4 dc 0
+v2 6 5 dc 0
+* u1 9 1 6 aswitch
+r1 7 8 50
+r2 3 9 1
+Vf2 2 3 0
+f2 3 9 Vf2 100
+Vf1 4 3 0
+f1 3 9 Vf1 10
+a1 9 [1 6 ] u1
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 )
+* Control Statements
+
+.ends scr \ No newline at end of file