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| author | athulappadan | 2016-08-26 14:44:35 +0530 |
|---|---|---|
| committer | athulappadan | 2016-08-26 14:44:35 +0530 |
| commit | a95164b4a281ddec4d6ee4258a1829a5a5334f5d (patch) | |
| tree | d7384bcac3c95569201579348cf0dcd473db6de9 /AstableMultivibratorIC555/lm555n.cir.out | |
| parent | 130c3b397fda16d8b0147581b13bb1c090951f55 (diff) | |
| download | eSim-Examples-a95164b4a281ddec4d6ee4258a1829a5a5334f5d.tar.gz eSim-Examples-a95164b4a281ddec4d6ee4258a1829a5a5334f5d.tar.bz2 eSim-Examples-a95164b4a281ddec4d6ee4258a1829a5a5334f5d.zip | |
all examples tested for json storagev2.0
Diffstat (limited to 'AstableMultivibratorIC555/lm555n.cir.out')
| -rw-r--r-- | AstableMultivibratorIC555/lm555n.cir.out | 40 |
1 files changed, 18 insertions, 22 deletions
diff --git a/AstableMultivibratorIC555/lm555n.cir.out b/AstableMultivibratorIC555/lm555n.cir.out index f45920f..21ca75a 100644 --- a/AstableMultivibratorIC555/lm555n.cir.out +++ b/AstableMultivibratorIC555/lm555n.cir.out @@ -1,14 +1,11 @@ -* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 11:00:36 am ist +* eeschema netlist version 1.1 (spice format) creation date: monday 17 december 2012 10:57:49 am ist -* Inverter d_inverter -* SR Latch d_srlatch +* u5 5 21 d_inverter +* u6 1 4 5 21 21 8 10 d_srlatch e2 18 0 23 14 10000 -* Limiter limit8 -* Digital to Analog converter dac8 -* Analog to Digital converter adc8 -u1 22 14 7 6 15 16 3 13 port +* u1 22 14 7 6 15 16 3 13 port r8 9 2 1500 -q1 3 2 22 qnom +q1 22 2 3 qnom r7 18 20 25 r6 17 19 25 e1 17 0 16 15 10000 @@ -18,18 +15,17 @@ r3 23 22 5000 r2 15 23 5000 r1 13 15 5000 a1 5 21 u5 -.model u5 d_inverter(rise_delay=1e-12 fall_delay=1e-12 input_load=1e-12) a2 1 4 5 21 21 8 10 u6 -.model u6 d_srlatch(rise_delay=1e-12 fall_delay=1e-12 ic=0 -+sr_load=1e-12 enable_load=1e-12 set_load=1e-12 reset_load=1e-12 -+sr_delay=1e-12 enable_delay=1e-12 set_delay=1e-12 reset_delay=1e-12) -a3 19 11 u4 -a4 20 12 u4 -.model u4 limit(out_lower_limit=0.0 out_upper_limit=5.0 in_offset=0.0 gain=1.0) -a5 [8] [7] u3 -a6 [10] [9] u3 -.model u3 dac_bridge(out_low=0.2 out_high=5.0 out_undef=5.0 ) -a7 [11] [4] u2 -a8 [12] [1] u2 -a9 [6] [5] u2 -.model u2 adc_bridge(in_low=0.8 in_high=2.0 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_srlatch, NgSpice Name: d_srlatch +.model u6 d_srlatch(ic=0 sr_load=1.0e-12 set_delay=1.0e-9 set_load=1.0e-12 sr_delay=1.0e-9 reset_load=1.0e-12 enable_delay=1.0e-9 reset_delay=1.0e-9 rise_delay=1.0e-9 fall_delay=1.0e-9 enable_load=1.0e-12 ) +.ac oct 897897 kjadsfhHz jhdsakjHz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |