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-rw-r--r--analog circuits/RC/RC-cache.lib138
-rw-r--r--analog circuits/RC/RC.bak2
-rw-r--r--analog circuits/RC/RC.cir11
-rw-r--r--analog circuits/RC/RC.sch186
4 files changed, 158 insertions, 179 deletions
diff --git a/analog circuits/RC/RC-cache.lib b/analog circuits/RC/RC-cache.lib
index 6884347..4f7abcb 100644
--- a/analog circuits/RC/RC-cache.lib
+++ b/analog circuits/RC/RC-cache.lib
@@ -1,69 +1,69 @@
-EESchema-LIBRARY Version 2.4
-#encoding utf-8
-#
-# Device:C
-#
-DEF Device:C C 0 10 N Y 1 F N
-F0 "C" 25 100 50 H V L CNN
-F1 "Device:C" 25 -100 50 H V L CNN
-F2 "" 38 -150 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 20 -80 -30 80 -30 N
-P 2 0 1 20 -80 30 80 30 N
-X ~ 1 0 150 110 D 50 50 1 1 P
-X ~ 2 0 -150 110 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# Device:R
-#
-DEF Device:R R 0 0 N Y 1 F N
-F0 "R" 80 0 50 V V C CNN
-F1 "Device:R" 0 0 50 V V C CNN
-F2 "" -70 0 50 V I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- R_*
-$ENDFPLIST
-DRAW
-S -40 -100 40 100 0 1 10 N
-X ~ 1 0 150 50 D 50 50 1 1 P
-X ~ 2 0 -150 50 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# power:GND
-#
-DEF power:GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "power:GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# pspice:VSOURCE
-#
-DEF pspice:VSOURCE V 0 40 Y Y 1 F N
-F0 "V" -250 300 50 H V C CNN
-F1 "pspice:VSOURCE" 0 0 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-C 0 0 200 0 1 0 N
-T 0 -320 -10 50 0 0 1 V Normal 0 C C
-P 2 0 1 0 -250 -250 -250 150 F
-P 3 0 1 0 -300 150 -250 250 -200 150 F
-X E1 1 0 300 100 D 50 50 1 1 I
-X E2 2 0 -300 100 U 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Device:C
+#
+DEF Device:C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "Device:C" 25 -100 50 H V L CNN
+F2 "" 38 -150 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 110 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device:R
+#
+DEF Device:R R 0 0 N Y 1 F N
+F0 "R" 80 0 50 V V C CNN
+F1 "Device:R" 0 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+X ~ 1 0 150 50 D 50 50 1 1 P
+X ~ 2 0 -150 50 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# power:GND
+#
+DEF power:GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power:GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# pspice:VSOURCE
+#
+DEF pspice:VSOURCE V 0 40 Y Y 1 F N
+F0 "V" -250 300 50 H V C CNN
+F1 "pspice:VSOURCE" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 0 200 0 1 0 N
+T 0 -320 -10 50 0 0 1 V Normal 0 C C
+P 2 0 1 0 -250 -250 -250 150 F
+P 3 0 1 0 -300 150 -250 250 -200 150 F
+X E1 1 0 300 100 D 50 50 1 1 I
+X E2 2 0 -300 100 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/analog circuits/RC/RC.bak b/analog circuits/RC/RC.bak
index 8b6bea6..2ad644c 100644
--- a/analog circuits/RC/RC.bak
+++ b/analog circuits/RC/RC.bak
@@ -24,7 +24,7 @@ F 2 "" H 3600 3850 50 0001 C CNN
F 3 "" H 3600 3850 50 0001 C CNN
F 4 "V" H 3600 3850 50 0001 C CNN "Spice_Primitive"
F 5 "Y" H 3600 3850 50 0001 C CNN "Spice_Netlist_Enabled"
-F 6 "pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0)" H 3600 3850 50 0001 C CNN "Spice_Model"
+F 6 "pwl(50m 5 50.5m 0 100m 0 500u 5 0m 0)" H 3600 3850 50 0001 C CNN "Spice_Model"
1 3600 3850
1 0 0 -1
$EndComp
diff --git a/analog circuits/RC/RC.cir b/analog circuits/RC/RC.cir
index 5a513c7..98f9865 100644
--- a/analog circuits/RC/RC.cir
+++ b/analog circuits/RC/RC.cir
@@ -1,6 +1,5 @@
-.title KiCad schematic
-V1 ip GND pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0)
-R1 out ip 1k
-C1 out GND 10u
-.tran 5m 100m
-.end
+.title KiCad schematic
+V1 Net-_R1-Pad2_ GND pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0)
+R1 Net-_C1-Pad1_ Net-_R1-Pad2_ 1k
+C1 Net-_C1-Pad1_ GND 10u
+.end
diff --git a/analog circuits/RC/RC.sch b/analog circuits/RC/RC.sch
index ab0da2e..8b6bea6 100644
--- a/analog circuits/RC/RC.sch
+++ b/analog circuits/RC/RC.sch
@@ -1,103 +1,83 @@
-EESchema Schematic File Version 4
-LIBS:RC-cache
-EELAYER 26 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L pspice:VSOURCE V1
-U 1 1 5B07B93A
-P 3600 3850
-F 0 "V1" H 3828 3896 50 0000 L CNN
-F 1 "VSOURCE" H 3828 3805 50 0000 L CNN
-F 2 "" H 3600 3850 50 0001 C CNN
-F 3 "" H 3600 3850 50 0001 C CNN
-F 4 "V" H 3600 3850 50 0001 C CNN "Spice_Primitive"
-F 5 "Y" H 3600 3850 50 0001 C CNN "Spice_Netlist_Enabled"
-F 6 "pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0)" H 3600 3850 50 0001 C CNN "Spice_Model"
- 1 3600 3850
- 1 0 0 -1
-$EndComp
-$Comp
-L Device:R R1
-U 1 1 5B07B9AD
-P 4750 3100
-F 0 "R1" V 4543 3100 50 0000 C CNN
-F 1 "1k" V 4634 3100 50 0000 C CNN
-F 2 "" V 4680 3100 50 0001 C CNN
-F 3 "~" H 4750 3100 50 0001 C CNN
- 1 4750 3100
- 0 1 1 0
-$EndComp
-$Comp
-L Device:C C1
-U 1 1 5B07BB2F
-P 5650 3800
-F 0 "C1" H 5765 3846 50 0000 L CNN
-F 1 "10u" H 5765 3755 50 0000 L CNN
-F 2 "" H 5688 3650 50 0001 C CNN
-F 3 "~" H 5650 3800 50 0001 C CNN
- 1 5650 3800
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 3600 4150 3600 4350
-Wire Wire Line
- 3600 4350 4550 4350
-Wire Wire Line
- 5650 4350 5650 3950
-$Comp
-L power:GND #PWR01
-U 1 1 5B07BC3B
-P 4550 4600
-F 0 "#PWR01" H 4550 4350 50 0001 C CNN
-F 1 "GND" H 4555 4427 50 0000 C CNN
-F 2 "" H 4550 4600 50 0001 C CNN
-F 3 "" H 4550 4600 50 0001 C CNN
- 1 4550 4600
- 1 0 0 -1
-$EndComp
-Connection ~ 4550 4350
-Wire Wire Line
- 4550 4350 5650 4350
-Wire Wire Line
- 4550 4350 4550 4600
-Wire Wire Line
- 4900 3100 5550 3100
-Wire Wire Line
- 5650 3100 5650 3650
-Wire Wire Line
- 3600 3550 3600 3100
-Wire Wire Line
- 3600 3100 3700 3100
-Text GLabel 3450 2750 0 50 Input ~ 0
-ip
-Wire Wire Line
- 3450 2750 3700 2750
-Wire Wire Line
- 3700 2750 3700 3100
-Connection ~ 3700 3100
-Wire Wire Line
- 3700 3100 4600 3100
-Text GLabel 5350 2800 0 50 Output ~ 0
-out
-Wire Wire Line
- 5350 2800 5550 2800
-Wire Wire Line
- 5550 2800 5550 3100
-Connection ~ 5550 3100
-Wire Wire Line
- 5550 3100 5650 3100
-Text Notes 7400 5800 0 50 ~ 0
-.tran 5m 100m
-$EndSCHEMATC
+EESchema Schematic File Version 4
+LIBS:RC-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pspice:VSOURCE V1
+U 1 1 5B07B93A
+P 3600 3850
+F 0 "V1" H 3828 3896 50 0000 L CNN
+F 1 "VSOURCE" H 3828 3805 50 0000 L CNN
+F 2 "" H 3600 3850 50 0001 C CNN
+F 3 "" H 3600 3850 50 0001 C CNN
+F 4 "V" H 3600 3850 50 0001 C CNN "Spice_Primitive"
+F 5 "Y" H 3600 3850 50 0001 C CNN "Spice_Netlist_Enabled"
+F 6 "pwl(0m 0 0.5m 5 50m 5 50.5m 0 100m 0)" H 3600 3850 50 0001 C CNN "Spice_Model"
+ 1 3600 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L Device:R R1
+U 1 1 5B07B9AD
+P 4750 3100
+F 0 "R1" V 4543 3100 50 0000 C CNN
+F 1 "1k" V 4634 3100 50 0000 C CNN
+F 2 "" V 4680 3100 50 0001 C CNN
+F 3 "~" H 4750 3100 50 0001 C CNN
+ 1 4750 3100
+ 0 1 1 0
+$EndComp
+$Comp
+L Device:C C1
+U 1 1 5B07BB2F
+P 5650 3800
+F 0 "C1" H 5765 3846 50 0000 L CNN
+F 1 "10u" H 5765 3755 50 0000 L CNN
+F 2 "" H 5688 3650 50 0001 C CNN
+F 3 "~" H 5650 3800 50 0001 C CNN
+ 1 5650 3800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3600 4150 3600 4350
+Wire Wire Line
+ 3600 4350 4550 4350
+Wire Wire Line
+ 5650 4350 5650 3950
+$Comp
+L power:GND #PWR01
+U 1 1 5B07BC3B
+P 4550 4600
+F 0 "#PWR01" H 4550 4350 50 0001 C CNN
+F 1 "GND" H 4555 4427 50 0000 C CNN
+F 2 "" H 4550 4600 50 0001 C CNN
+F 3 "" H 4550 4600 50 0001 C CNN
+ 1 4550 4600
+ 1 0 0 -1
+$EndComp
+Connection ~ 4550 4350
+Wire Wire Line
+ 4550 4350 5650 4350
+Wire Wire Line
+ 4550 4350 4550 4600
+Wire Wire Line
+ 4900 3100 5650 3100
+Wire Wire Line
+ 5650 3100 5650 3650
+Wire Wire Line
+ 3600 3550 3600 3100
+Wire Wire Line
+ 3600 3100 4600 3100
+$EndSCHEMATC