From 476705d693c7122d34f9b049fa79b935405c9b49 Mon Sep 17 00:00:00 2001 From: prashantsinalkar Date: Tue, 14 Apr 2020 10:19:27 +0530 Subject: Initial commit --- .../1-Analog_Integrated_Circuit_Design.ipynb | 592 +++++++++++++++++++++ 1 file changed, 592 insertions(+) create mode 100644 Integrated_Circuits_by_P_Raja/1-Analog_Integrated_Circuit_Design.ipynb (limited to 'Integrated_Circuits_by_P_Raja/1-Analog_Integrated_Circuit_Design.ipynb') diff --git a/Integrated_Circuits_by_P_Raja/1-Analog_Integrated_Circuit_Design.ipynb b/Integrated_Circuits_by_P_Raja/1-Analog_Integrated_Circuit_Design.ipynb new file mode 100644 index 0000000..cef40a9 --- /dev/null +++ b/Integrated_Circuits_by_P_Raja/1-Analog_Integrated_Circuit_Design.ipynb @@ -0,0 +1,592 @@ +{ +"cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Chapter 1: Analog Integrated Circuit Design" + ] + }, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.10: Change_in_IO.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.10\n", +"clc;clear;close;\n", +"IREF=2;//mA\n", +"IO=IREF;//mA\n", +"VA2=90;//V\n", +"Vo1=1;//V\n", +"Vo2=10;//V\n", +"ro2=VA2/IO;//kohm\n", +"delVO=Vo2-Vo1;//V\n", +"delIO=delVO/ro2;//mA\n", +"Change=delIO/IO*100;//%\n", +"disp(Change,'Change in Io(%) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.11: Lowest_output_voltage.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.11\n", +"clc;clear;close;\n", +"VBE3=0.7;//V\n", +"VBE1=0.7;//V\n", +"IREF1=100;//micro A\n", +"IC1=IREF1;//micro A\n", +"IREF2=1;//mA\n", +"IC2=IREF2;//mA\n", +"Beta=200;//unitless\n", +"//IC2/IC1=(IS*exp(VBE2/VT))/(IS*exp(VBE1/VT))\n", +"VT=26;//mV\n", +"deltaVBE=VT*10^-3*log(IC2/IC1);//V(deltaVBE=VBE2-VBE1)\n", +"deltaVx=2*deltaVBE;//V\n", +"IO=IREF1/(1+2/(Beta^2+Beta));//micro A\n", +"delIO=IC1-IO;//micro A\n", +"Change=delIO/IO*100;//%\n", +"disp(Change,'Change in Io(%) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.12: Design_a_current_mirror_circuit.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.12\n", +"clc;clear;close;\n", +"format('v',5);\n", +"Iout=8;//micro A\n", +"VBE=0.7;//V\n", +"VCC=20;//V\n", +"Beta=80;//unitless\n", +"IREF=Iout*(1+2/Beta);//micro A\n", +"disp(IREF,'Reference current is(micro A) : ');\n", +"R=(VCC-VBE)/(IREF);//Mohm\n", +"disp(R,'Resistance is(Mohm) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.13: Design_a_current_mirror_circuit.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.13\n", +"clc;clear;close;\n", +"format('v',5);\n", +"Iout=1;//mA\n", +"VBE=0.7;//V\n", +"VCC=30;//V\n", +"Beta=100;//unitless\n", +"IREF=Iout*(1+2/Beta);//mA\n", +"disp(IREF,'Reference current is(mA) : ');\n", +"R=(VCC-VBE)/(IREF);//kohm\n", +"disp(R,'Resistance is(kohm) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.14: CIrcuit_of_current_source.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.14\n", +"clc;clear;close;\n", +"format('v',5);\n", +"Iout=0.5;//mA\n", +"VBE=0.7;//V\n", +"VCC=5;//V\n", +"Beta=50;//unitless\n", +"IREF=Iout*(1+2/Beta);//mA\n", +"disp(IREF,'Reference current is(mA) : ');\n", +"R=(VCC-VBE)/(IREF);//kohm\n", +"disp(R,'Resistance is(kohm) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.15: Modified_current_mirror_circuit.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.15\n", +"clc;clear;close;\n", +"format('v',5);\n", +"Iout=8;//micro A\n", +"VBE=0.7;//V\n", +"VCC=20;//V\n", +"Beta=100;//unitless\n", +"IREF=Iout*(1+2/Beta/(Beta+1));//micro A\n", +"disp(IREF,'Reference current is(micro A) : ');\n", +"R=(VCC-2*VBE)/(IREF);//Mohm\n", +"disp(R,'Resistance is(Mohm) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.16: Find_Iout.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.16\n", +"clc;clear;close;\n", +"format('v',5);\n", +"Beta=120;//unitless\n", +"VBE=0.7;//V\n", +"VCC=10;//V\n", +"R=5.6;//kohm\n", +"//IREF=IC1+I1;as Beta>>1\n", +"//I1=IC2+IB3;as Beta>>1\n", +"IREF=(VCC-VBE)/R;//mA\n", +"//IREF=IC*(2+1/Beta) or IREF=2*IC;as Beta>>1\n", +"IC=IREF/2;//mA\n", +"Iout=IC;//mA\n", +"disp(Iout,'Iout for the circuit is(mA) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.17: Design_a_widlar_current_source.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.17\n", +"clc;clear;close;\n", +"format('v',5);\n", +"Iout=6;//micro A\n", +"IREF=1.2;//mA\n", +"VBE2=0.7;//V\n", +"VT=26;//mV\n", +"VCC=20;//V\n", +"Beta=120;//unitless\n", +"R=(VCC-VBE2)/IREF;//kohm\n", +"IC2=(IREF-Iout/Beta)/(1+1/Beta);//mA\n", +"RS=VT/Iout*log(IC2*1000/Iout);//kohm\n", +"disp(RS,R,'Value of resistance R & Rs for widlar current source design is(kohm) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.18: Design_a_widlar_current_source.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.18\n", +"clc;clear;close;\n", +"format('v',5);\n", +"IREF=1;//mA\n", +"IO2=20;//micro A\n", +"IO3=40;//micro A\n", +"VBE1=0.7;//V\n", +"VT=26;//mV\n", +"VCC=10;//V\n", +"VEE=-VCC;//V\n", +"R=(VCC-VBE1-VEE)/IREF;//kohm\n", +"RE2=VT*10^-3/(IO2*10^-6)*log((IREF*10^-3)/(IO2*10^-6));//ohm\n", +"RE2=RE2/1000;//kohm\n", +"RE3=VT*10^-3/(IO3*10^-6)*log((IREF*10^-3)/(IO3*10^-6));//ohm\n", +"RE3=RE3/1000;//kohm\n", +"disp(RE3,RE2,R,'Value of resistance R, RE2 & RE3 for widlar current source design is(kohm) : ');\n", +"VBE2=VBE1-RE2*IO2*10^-3;//V\n", +"VBE3=VBE1-RE3*IO3*10^-3;//V\n", +"format('v',7);\n", +"disp(VBE3,VBE2,'Values of VBE2 & VBE3(V) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.19: Calculate_current.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.19\n", +"clc;clear;close;\n", +"format('v',5);\n", +"Beta=100;//unitless\n", +"VBE=0.715;//V\n", +"VEE=10;//V\n", +"R=5.6;//kohm\n", +"IREF=(VEE-VBE)/R;//mA\n", +"IC1=IREF/(1+2/Beta);//mA\n", +"disp(IC1,'Collector current in each transistor is equal as all are identical. It is(mA) : ');\n", +"IRC=3*IC1;//mA\n", +"disp(IRC,'Current through resistance Rc is (mA) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.1: Lowest_value_of_VO.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.1\n", +"clc;clear;close;\n", +"VDD=1.8;//V\n", +"IREF=50;//micro A\n", +"IO=IREF;//micro A\n", +"L=0.5;//micro m\n", +"W=5;//micro m\n", +"Vt=0.5;//V\n", +"Kn_dash=250;//micro A/V^2\n", +"VGS=sqrt(IO/(1/2*Kn_dash*(W/L)))+Vt;//V\n", +"disp(VGS,'Value of VGS(V) : ');\n", +"R=(VDD-VGS)/(IREF*10^-6);//ohm\n", +"disp(R/1000,'Value of R(kohm) : ');\n", +"VDS2=VGS-Vt;//V\n", +"VO=VDS2;//V\n", +"disp(VO,'Lowest value of VO(V) : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.20: IC1_IC2_and_RC.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.20\n", +"clc;clear;close;\n", +"format('v',6);\n", +"Vout=5;//V\n", +"Beta=180;//unitless\n", +"VBE=0.7;//V\n", +"VEE=10;//V\n", +"Vout=5;//V\n", +"R1=22;//kohm\n", +"R2=2.2;//kohm\n", +"IREF=(VEE-VBE)/R1;//mA\n", +"IC=(IREF-VBE/R2)/(1+2/Beta);//mA\n", +"IC1=IC*1000;//micro A(as VBE1=VBE2 IC1=IC2)\n", +"IC2=IC*1000;//micro A\n", +"disp(IC2,IC1,'Current IC1 & IC2 (micro A) : ');\n", +"RC=(VEE-Vout)/(IC1*10^-3);//kohm\n", +"disp(RC,'Value of Rc is (kohm) : ');\n", +"//Answer is wrong in the textbook." + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.21: IC2_IC3_IC4.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.21\n", +"clc;clear;close;\n", +"format('v',6);\n", +"AQ2byA1=0.5;\n", +"AQ3byA1=0.25;\n", +"AQ4byA1=0.125;\n", +"VBE=0.7;//V\n", +"VCC=15;//V\n", +"R=20;//kohm\n", +"IC1=(VCC-VBE)/R;//mA\n", +"IC2=IC1*AQ2byA1;//mA\n", +"IC3=IC1*AQ3byA1;//mA\n", +"IC4=IC1*AQ4byA1;//mA\n", +"disp(IC4,IC3,IC2,'Value of current IC2, IC3 & IC4 is (mA) : ');\n", +"//Value of IC4 is displayed wrong in the textbook." + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.3_1: Current_gain.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.3 at page no. 20\n", +"clc;\n", +"clear;\n", +"format('v',5);\n", +"close;\n", +"Beta=20;//unitless\n", +"IObyIREF=1/(1+2/Beta);//Current gain\n", +"disp(IObyIREF,'Current gain : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.3: Design_a_current_source.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.3\n", +"clc;clear;close;\n", +"VDD=1.8;//V\n", +"Vt=0.6;//V\n", +"mpCox=100;//micro A/V^2\n", +"IREF=80;//micro A\n", +"VOmax=1.6;//V\n", +"VSG=VDD-VOmax+Vt;//V\n", +"VGS=-VSG;//V\n", +"VS=VDD;//V\n", +"VG=VGS+VS;//V\n", +"R=VG/(IREF*10^-6);//ohm\n", +"ID=IREF;//micro A\n", +"WbyL=2*ID*10^-6/(mpCox*10^-6)/(VGS+Vt)^2;//unitless\n", +"disp(VGS,'Value of VGS(V) : ');\n", +"disp(VG,'Value of VG(V) : ');\n", +"disp(R/1000,'Value of R(kohm) : ');\n", +"disp(WbyL,'W/L ratio : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.4: Current_transfer_ratio.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.4\n", +"clc;clear;close;\n", +"format('v',5);\n", +"Beta=80;//unitless\n", +"disp('IREF=IC1+IC1/Beta+IO/Beta');\n", +"disp('IO/IREF=m implies IC1=IO/m as IC1=IREF');\n", +"disp('IREF=IO*(1/m+1/m/Beta+1/Beta');\n", +"disp('IO/IREF=m/(1+1/Beta+m/Beta');\n", +"disp('IO/IREF=m*(1-5/100);//for large Beta');\n", +"m=(1/(1-5/100)-1)*Beta-1;//Current transfer ratio\n", +"disp(m,'Largest current transfer ratio : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.7: Transistor_ratio.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.7\n", +"clc;clear;close;\n", +"format('v',5);\n", +"Beta=80;//untless\n", +"disp('IREF=IC1+IC1/Beta+IO/Beta');\n", +"disp('IO/IREF=m implies IC1=IO/m as IC1=IREF');\n", +"disp('IREF=IO*(1/m+1/m/Beta+1/Beta');\n", +"disp('IO/IREF=m/(1+1/Beta+m/Beta');\n", +"disp('IO/IREF=m*(1-5/100);//for large Beta');\n", +"m=(1/(1-5/100)-1)*Beta-1;//Current transfer ratio\n", +"disp(m,'Largest current transfer ratio : ');" + ] + } +, +{ + "cell_type": "markdown", + "metadata": {}, + "source": [ + "## Example 1.9: Current_gain.sce" + ] + }, + { +"cell_type": "code", + "execution_count": null, + "metadata": { + "collapsed": true + }, + "outputs": [], +"source": [ +"//Ex 1.9\n", +"clc;\n", +"clear;\n", +"close;\n", +"format('v',5);\n", +"Beta=20;//unitless\n", +"IObyIREF=1/(1+2/Beta);//Current gain\n", +"disp(IObyIREF,'Current gain : ');" + ] + } +], +"metadata": { + "kernelspec": { + "display_name": "Scilab", + "language": "scilab", + "name": "scilab" + }, + "language_info": { + "file_extension": ".sce", + "help_links": [ + { + "text": "MetaKernel Magics", + "url": "https://github.com/calysto/metakernel/blob/master/metakernel/magics/README.md" + } + ], + "mimetype": "text/x-octave", + "name": "scilab", + "version": "0.7.1" + } + }, + "nbformat": 4, + "nbformat_minor": 0 +} -- cgit