summaryrefslogtreecommitdiff
path: root/src/c/hardware/rasberrypi/interfaces
diff options
context:
space:
mode:
Diffstat (limited to 'src/c/hardware/rasberrypi/interfaces')
-rw-r--r--src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralPinISR.h25
-rw-r--r--src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralThreading.h25
-rw-r--r--src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralTiming.h20
3 files changed, 70 insertions, 0 deletions
diff --git a/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralPinISR.h b/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralPinISR.h
new file mode 100644
index 0000000..b2c1ed1
--- /dev/null
+++ b/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralPinISR.h
@@ -0,0 +1,25 @@
+ /* Copyright (C) 2016 - IIT Bombay - FOSSEE
+
+ This file must be used under the terms of the CeCILL.
+ This source file is licensed as described in the file COPYING, which
+ you should have received as part of this distribution. The terms
+ are also available at
+ http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt
+ Author: Siddhesh Wani
+ Organization: FOSSEE, IIT Bombay
+ Email: toolbox@scilab.in
+ */
+#ifndef __INT_RPIPERIPHERALPINISR_H__
+#define __INT_RPIPERIPHERALPINISR_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RPI_PinISR(pin,edge,funname) i16RPIPinISRs((uint8)pin,(uint8)edge,funname)
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*__INT_RPIPERIPHERALPINISR_H__*/
diff --git a/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralThreading.h b/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralThreading.h
new file mode 100644
index 0000000..68ed6e0
--- /dev/null
+++ b/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralThreading.h
@@ -0,0 +1,25 @@
+ /* Copyright (C) 2016 - IIT Bombay - FOSSEE
+
+ This file must be used under the terms of the CeCILL.
+ This source file is licensed as described in the file COPYING, which
+ you should have received as part of this distribution. The terms
+ are also available at
+ http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt
+ Author: Siddhesh Wani
+ Organization: FOSSEE, IIT Bombay
+ Email: toolbox@scilab.in
+ */
+#ifndef __INT_RPIPERIPHERALTHREADING_H__
+#define __INT_RPIPERIPHERALTHREADING_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RPI_ThreadCreate(fn) RPIThreadCreate(fn);
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /*__INT_RPIPERIPHERALTHREADING_H__*/
diff --git a/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralTiming.h b/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralTiming.h
index cbbb47a..c91fdfb 100644
--- a/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralTiming.h
+++ b/src/c/hardware/rasberrypi/interfaces/int_RPIPeripheralTiming.h
@@ -5,11 +5,19 @@
you should have received as part of this distribution. The terms
are also available at
http://www.cecill.info/licences/Licence_CeCILL_V2-en.txt
+<<<<<<< HEAD
Author: Jorawar Singh, Siddhesh Wani
+=======
+ Author: Siddhesh Wani
+>>>>>>> 9e5793a7b05b23e6044a6d7a9ddd5db39ba375f0
Organization: FOSSEE, IIT Bombay
Email: toolbox@scilab.in
*/
+<<<<<<< HEAD
+=======
+
+>>>>>>> 9e5793a7b05b23e6044a6d7a9ddd5db39ba375f0
#ifndef __INT_RPIPERIPHERALTIMING_H__
#define __INT_RPIPERIPHERALTIMING_H__
@@ -20,6 +28,7 @@
extern "C" {
#endif
+<<<<<<< HEAD
#define u320RPI_delay(time) u32RPI_delays(time);
#define d0RPI_delay(time) u32RPI_delays(time);
@@ -28,9 +37,20 @@ extern "C" {
#define RPI_millisu320() RPI_millis();
#define RPI_microsu320() RPI_micros();
+=======
+#define RPI_DelayMicro(in1) u16RPIDelayMicros((uint16) in1)
+#define RPI_DelayMilli(in1) u16RPIDelayMillis((uint16) in1)
+#define RPI_GetMicro() u32RPIGetMicros()
+#define RPI_GetMillis() u32RPIGetMillis()
+
+>>>>>>> 9e5793a7b05b23e6044a6d7a9ddd5db39ba375f0
#ifdef __cplusplus
} /* extern "C" */
#endif
+<<<<<<< HEAD
#endif /* !__INT_RPIPERIPHERALTIMING_H__ */
+=======
+#endif /* !__RPIPERIPHERALTIMING_H__ */
+>>>>>>> 9e5793a7b05b23e6044a6d7a9ddd5db39ba375f0